JPS61270870A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61270870A
JPS61270870A JP60112606A JP11260685A JPS61270870A JP S61270870 A JPS61270870 A JP S61270870A JP 60112606 A JP60112606 A JP 60112606A JP 11260685 A JP11260685 A JP 11260685A JP S61270870 A JPS61270870 A JP S61270870A
Authority
JP
Japan
Prior art keywords
film
semiconductor device
gate electrode
impurity diffusion
silicide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60112606A
Other languages
Japanese (ja)
Inventor
Tatsuro Okamoto
岡本　龍郎
Masahiro Shimizu
雅裕 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60112606A priority Critical patent/JPS61270870A/en
Priority to KR1019850008215A priority patent/KR890004464B1/en
Priority to DE19863614793 priority patent/DE3614793A1/en
Publication of JPS61270870A publication Critical patent/JPS61270870A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To contrive the improvement of electrical insulating characteristics between the gate electrode and the impurity diffusion layer and the reduction of the sheet resistivities of the gate electrode and the impurity diffusion layers by a method wherein the insulating films are each formed on the side parts of the gate electrode and the metal silicide films are each formed on the impurity diffusion layers and the gate electrode. CONSTITUTION:Side walls 5a and 5b, by which a polycrystalline Si film 40 to be used as the gate electrode is insulated from impurity diffusion layers 9a and 9b to be used as the source and drain regions, are formed on the side parts of the polycrystalline Si film 40. Moreover, Ti silicide films 7a, 7b and 7c are each formed on the films 9a and 9b and the film 40; a Ti oxide film 10a is formed on the film 7a, the wall 5a and the film 7c; a Ti oxide film 10b is formed on the film 7a, the wall 5b and the film 7c; and a Ti oxide film 10c is formed on the film 7a and an insulating film 2 for interelement isolation. Furthermore, interlayer insulating films 11a-11c are each formed on the films 10a-10c. By this constitution, the electrical insulating characteristics between the gate electrode 40 and the layers 9a and 9b are improved and the sheet resistivities of the electrode 40 and the layers 9a and 9b are reduced, and furthermore, the electrode 40 and the layers 9a and 9b are stabi lized to a heat treatment.

Description

【発明の詳細な説明】 ［産業上の利用分野コ この発明は半導体装置に関し、特に大規模集積回路（Ｖ
ＬＳＩ）に用いられるＭＯ８型電界効果トランジスタの
構造に関するものである。[Detailed Description of the Invention] [Industrial Application Field] This invention relates to semiconductor devices, particularly large-scale integrated circuits (V
The present invention relates to the structure of an MO8 field effect transistor used in LSI.

［従来の技術］ 第３図は従来のＭＯ８型電界効果トランジスタを示す断
面図である。初めにこのトランジスタの構成について説
明する。図において、シリコン基・板１上に素子間分離
用の比較的厚い絶縁１１１２が選択的に形成されており
、この絶縁膜はたとえばシリコン酸化膜からなっている
。また、シリコン基板１上にソース・ドレイン領域とな
る不純物拡散層１５ａ、１５ｂが間隔を隔てて形成され
ている。[Prior Art] FIG. 3 is a cross-sectional view showing a conventional MO8 field effect transistor. First, the structure of this transistor will be explained. In the figure, a relatively thick insulating film 1112 for isolation between elements is selectively formed on a silicon substrate/board 1, and this insulating film is made of, for example, a silicon oxide film. Further, impurity diffusion layers 15a and 15b, which become source/drain regions, are formed on the silicon substrate 1 at intervals.

さらに、シリコン基板１上の不純物拡散層１５ａ。Further, an impurity diffusion layer 15a on the silicon substrate 1.

１５ｂ１問にイオン注入法によりしきい値電圧制御用不
純物層１４が形成されている。このしき、い値電圧制御
用不純物層上にゲート絶縁膜となる比較的薄い絶縁膜３
０が形成されており、この絶縁膜はたとえばシリコン酸
化膜からなっている。絶縁膜３０上にＣＶＤ法などによ
りゲート電極となる多結晶シリコン膜４０が形成されて
おり、この多結晶シリコン膜は絶縁膜３０によりシリコ
ン基板１と絶縁されている。不純物拡散層１５ａ上およ
び多結晶シリコン１１４０上に＋ｉｖｙ絶縁１［１１ａ
が、不純物拡散層１５ｂ上および多結晶シリコンｌ１ｌ
Ｉ４０上に層間絶縁膜１１ｂが、不純物拡散層１５ｂ上
および絶縁膜２上に層間絶縁膜１１ｃがＣＶＤ法により
形成されている。１１問絶縁１１１１ａ、１１ｂにコン
タクト孔１２ａが、層間絶縁１１１１１）。A threshold voltage control impurity layer 14 is formed in one layer 15b by ion implantation. A relatively thin insulating film 3 which becomes a gate insulating film is formed on this threshold voltage control impurity layer.
0 is formed, and this insulating film is made of, for example, a silicon oxide film. A polycrystalline silicon film 40 serving as a gate electrode is formed on the insulating film 30 by CVD or the like, and this polycrystalline silicon film 40 is insulated from the silicon substrate 1 by the insulating film 30. +ivy insulation 1 [11a
However, on the impurity diffusion layer 15b and the polycrystalline silicon l1l
An interlayer insulating film 11b is formed on the I40, and an interlayer insulating film 11c is formed on the impurity diffusion layer 15b and the insulating film 2 by the CVD method. Contact hole 12a is provided in insulation 1111a and 11b, and interlayer insulation 11111).

１１ｃにコンタクト孔１２ｂが写真製版とエツチング法
により選択的に形成されている。これらコンタクト孔、
１２ａ、１２ｂにそれぞれ配線用のアルミニウム合金１
！１３ａ、１３ｂが形成されている。このように、ＭＯ
８型電界効果トランジスタはソース・ドレイン、ゲート
より構成され、絶縁膜２によって隣接するトランジスタ
同士が電気的に分離されている。A contact hole 12b is selectively formed in 11c by photolithography and etching. These contact holes,
Aluminum alloy 1 for wiring in 12a and 12b respectively
! 13a and 13b are formed. In this way, M.O.
The type 8 field effect transistor is composed of a source, a drain, and a gate, and adjacent transistors are electrically isolated from each other by an insulating film 2.

次にこのトランジスタの動作について説明する。Next, the operation of this transistor will be explained.

ソース領域／ドレイン領ｍ闇に電圧を印加した状態でゲ
ート電極へ加える電圧をＩＩＩすることにより、ゲート
電極下のシリコン基板１表面部にチャンネルを形成する
／しないことでトランジスタをＯＮ、ＯＦＦさせる。By applying a voltage to the gate electrode while applying a voltage to the source region/drain region, the transistor is turned on and off by forming/not forming a channel in the surface portion of the silicon substrate 1 under the gate electrode.

［発明が解決しようとする問題点コ ところで、ＭＯＳ型のダイナミックＲＡＭメモリ素子に
代表されるようにＬＳＩの高密度・高集積化が進むに従
い、平面方向だけでなく縦方向の素子構造の縮小化が行
なわれてきた。このような縮小化に伴い従来のＭＯ８型
電界効果トランジスタでは以下のような問題、ｒｊＩ題
が−あった。■ｉｉ！線膜の薄膜化、配線長の増大に伴
い配線抵抗が増し、素子の電気信号伝達特性が低下する
。このため、配線膜のシート抵抗を下げなければならな
い、■Ｍ　ＯＳ型電界効果トランジスタにおける短チャ
ンネル効果の防止に代表されるように、素子の不純物拡
散層の接合深さを浅くする必要があるが、その反面従来
のＭＯＳ型電界効果トランジスタではシート抵抗が上昇
し、不純物拡散層中での電気信号伝達特性が低下する。[Problems to be Solved by the Invention] Incidentally, as LSIs become more dense and highly integrated, as typified by MOS type dynamic RAM memory elements, the element structure becomes smaller not only in the planar direction but also in the vertical direction. has been carried out. With such miniaturization, the conventional MO8 type field effect transistor has had the following problems. ■ii! As the wire film becomes thinner and the wire length increases, the wire resistance increases and the electrical signal transmission characteristics of the device deteriorate. For this reason, it is necessary to reduce the sheet resistance of the wiring film, and it is necessary to reduce the junction depth of the impurity diffusion layer of the device, as typified by the prevention of short channel effects in MOSFET field effect transistors. On the other hand, in conventional MOS field effect transistors, sheet resistance increases and electrical signal transmission characteristics in the impurity diffusion layer deteriorate.

したがって、浅い接合を有しかつシート抵抗の低い不純
物拡散層を形成しなければならない。Therefore, it is necessary to form an impurity diffusion layer having a shallow junction and low sheet resistance.

以上のような点については、従来のＭＯＳ型電界効果ト
ランジスタそのままでは根本的な解決は難しいのが現実
である。The reality is that it is difficult to fundamentally solve the above-mentioned problems using conventional MOS field effect transistors as they are.

この発明は上記のような問題点を解消するためになされ
たもので、ゲート電極とソース・ドレイン不純物拡散層
間の電気的絶縁特性が優れ、かつゲート電極およびソー
ス・ドレイン不純物拡散層のシート抵抗がともに低く、
かつ熱処理に対して安定で、かつ浅い接合を有する不純
物拡散層を備えた半導体装置を得ることを目的とする。This invention was made to solve the above-mentioned problems, and it has excellent electrical insulation properties between the gate electrode and the source/drain impurity diffusion layer, and has a low sheet resistance of the gate electrode and the source/drain impurity diffusion layer. Both are low;
Another object of the present invention is to obtain a semiconductor device having an impurity diffusion layer that is stable against heat treatment and has a shallow junction.

［問題点を解決するための手段］ この発明に係る半導体装置は、半導体シリコン基板上に
ソース・ドレイン領域ｉ域となる不純物拡散層を形成し
、上記基板上にゲート絶縁膜を形成し。[Means for Solving the Problems] In a semiconductor device according to the present invention, an impurity diffusion layer serving as a source/drain region i is formed on a semiconductor silicon substrate, and a gate insulating film is formed on the substrate.

ゲート絶縁膜上に多結晶シリコンからなるゲート電極を
形成し、ゲート電極の側部に該ゲート電極と不純物拡散
層とを絶縁する絶縁膜を形成し、不純物拡散層上および
ゲート電極上に金属シリサイド膜を自己整合的に形成し
、金属シリサイド膜上および絶縁膜上に金属酸化膜を形
成し、金属酸化膜上に１１間絶縁膜を形成したものであ
る。A gate electrode made of polycrystalline silicon is formed on the gate insulating film, an insulating film is formed on the side of the gate electrode to insulate the gate electrode and the impurity diffusion layer, and metal silicide is formed on the impurity diffusion layer and the gate electrode. A film is formed in a self-aligned manner, a metal oxide film is formed on a metal silicide film and an insulating film, and an 11-layer insulating film is formed on the metal oxide film.

［作用］ この発明においては、金属シリサイド膜はゲニト電極お
よびソース・ドレイン領域のシート抵抗低減に寄与し、
金属酸化膜は、ゲートＮ極とソース・ドレイン領域間の
電気絶縁特性を向上させ、また金属シリサイド膜と層間
絶縁ＩＩ！間の熱処理に伴う反応を防止する。[Function] In this invention, the metal silicide film contributes to reducing the sheet resistance of the genit electrode and the source/drain region,
The metal oxide film improves the electrical insulation properties between the gate N-electrode and the source/drain regions, and also improves the electrical insulation properties between the gate N electrode and the source/drain regions, and the metal silicide film and interlayer insulation II! Prevents reactions associated with heat treatment during the process.

［実施例〕 以下、この発明の実施例を図について説明する。[Example〕 Embodiments of the present invention will be described below with reference to the drawings.

第１図はこの発明の実施例である半導体装置を示す断面
図である。この実施例においては、ゲート電極となる多
結晶シリコンｉｌｌ！４０の側部に該多結晶シリコン膜
とソース・ドレイン領域となる不純物拡散層９ａ　、９
１１とを絶縁する絶縁膜からなるサイドウオール５ａ　
、５ｂが形成されており、不純物拡散層９ａ上にチタン
シリサイド膜７ａが、多結晶シリコン１１４０上にチタ
ンシリサイド膜７Ｃが、不純物拡散層９ｂ上にチタンシ
リサイド膜７ｂが形成されており、チタンシリサイド膜
７ａ上、サイドウオール５ａ上、チタンシリサイド膜７
Ｃ上に酸化チタン１１１０ａが、チタシリサイド膜７ｂ
上、サイドウオール５ｂ上、チタンシリサイド膜７Ｃ上
に酸化チタン膜１０ｂが、チタンシリサイドｌ［７ｔｌ
上、比較的厚い絶縁膜２上に酸化チタンｌ１１１０ｃが
形成されており、これらの点を除いてはこの実施例の構
成は第３図の構成と同じである。FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the invention. In this example, polycrystalline silicon ill! serves as the gate electrode. On the sides of the polycrystalline silicon film and impurity diffusion layers 9a, 9, which will become source/drain regions.
A side wall 5a made of an insulating film that insulates the
, 5b are formed, a titanium silicide film 7a is formed on the impurity diffusion layer 9a, a titanium silicide film 7C is formed on the polycrystalline silicon 1140, a titanium silicide film 7b is formed on the impurity diffusion layer 9b, and the titanium silicide film 7a is formed on the impurity diffusion layer 9a. On the film 7a, on the sidewall 5a, titanium silicide film 7
Titanium oxide 1110a is formed on titanium silicide film 7b.
Above, on the sidewall 5b and on the titanium silicide film 7C, a titanium oxide film 10b is formed on the titanium silicide l[7tl
At the top, titanium oxide l1110c is formed on the relatively thick insulating film 2, and except for these points, the structure of this embodiment is the same as the structure of FIG. 3.

第２図（ａ）〜（ｈ）はこの発明の実施例である半導体
装置の製造方法の主要工程段階における状態を示す断面
図である。まず、シリコン基板１の主面上に素子間分離
用の、たとえばシリコン酸化膜からなる比較的厚い絶縁
膜２を選択的に形成。FIGS. 2(a) to 2(h) are cross-sectional views showing the main process steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. First, a relatively thick insulating film 2 made of, for example, a silicon oxide film is selectively formed on the main surface of a silicon substrate 1 for isolation between elements.

する［第２図（ａ）］。次に、イオン注入法などにより
不純物をシリコン基板１上面に導入してしきい値電圧制
御用不純物層、１４を形成し、この後シリコン基板１上
に、後でＭＯ８電界効果トランジスタのゲート絶ａｍと
なる比較的薄い絶縁膜３を形成し、さらにこの４１１Ｃ
ＶＤ法などにより厚い絶縁１！２上および薄い絶縁ｇｌ
１３上に多結晶シリコンＭ４を形成する。この多結晶シ
リコン膜は、たとえば躾形成時または形成後に熱拡散法
などにより燐などの不純物を含むものである［第２図（
ｂ　）コ。次に、多結晶シリコンｍ４と薄い絶縁膜３を
写真製版およびエツチング法により所望のパターンにパ
ターニングしてゲート絶縁膜となる薄い絶縁ｍ３０．ゲ
ート電極となる多結晶シリコン膜４０を形成した後、Ｃ
ＶＤ・スパッタ法などにより厚い絶縁１１１２上、シリ
コン基板１上、多結晶シリコン８４０上に、たとえばシ
リコン酸化膜などの絶縁１１５を形成するし第２図（Ｃ
）］。次に、絶縁１１５を異方性エツチングして多結晶
シリコン膜４０とシリコン基板１とで構成される段差部
に絶縁ＷＡ５の一部を残し、いわゆるサイドウオール（
または゛額ブチ゛°または゛サイドスペーサ”）５ａ、
５ｂを形成する［第２図（ｄ　）　］　、次に、スパッ
タ法などにより厚い絶縁膜２上、シリコン基板１の主面
上、サイドウオール５ａ、５ｂ上。[Figure 2(a)]. Next, impurities are introduced into the upper surface of the silicon substrate 1 by ion implantation or the like to form an impurity layer 14 for controlling the threshold voltage. A relatively thin insulating film 3 is formed, and this 411C
Thick insulation 1 and 2 and thin insulation GL by VD method etc.
Polycrystalline silicon M4 is formed on 13. This polycrystalline silicon film contains impurities such as phosphorus, for example, by thermal diffusion during or after formation [Fig.
b) Ko. Next, the polycrystalline silicon m4 and the thin insulating film 3 are patterned into a desired pattern by photolithography and etching to form a thin insulating film m30 that will become the gate insulating film. After forming the polycrystalline silicon film 40 that will become the gate electrode, C.
An insulator 115, such as a silicon oxide film, is formed on the thick insulator 1112, the silicon substrate 1, and the polycrystalline silicon 840 by VD/sputtering, etc., as shown in FIG.
)]. Next, the insulation 115 is anisotropically etched to leave a part of the insulation WA5 at the step formed by the polycrystalline silicon film 40 and the silicon substrate 1, forming a so-called sidewall (
or “Forehead Butch” or “Side Spacer”) 5a,
5b [FIG. 2(d)], and then, by sputtering or the like, on the thick insulating film 2, on the main surface of the silicon substrate 1, and on the side walls 5a and 5b.

多結晶シリコン膜４０上にチタンｌｌ！６を形成する［
第２図（ｅ）］。次に、チタン膜６をＮ２雰囲気中で熱
処理することによりシリコン基板１上および多結晶シリ
コン膜４０上にそれぞれ下からチタンシリサイド膜７ａ
、７ｂおよび７Ｃを、これらチタンシリサイド膜７ａ、
７ｂ、Ｔｏ上に比較的薄い窒化チタン１１８を形成し、
厚い絶縁膜２上。Titanium on the polycrystalline silicon film 40! form 6 [
Figure 2(e)]. Next, by heat-treating the titanium film 6 in an N2 atmosphere, a titanium silicide film 7a is formed on the silicon substrate 1 and the polycrystalline silicon film 40 from below.
, 7b and 7C, these titanium silicide films 7a,
7b, forming a relatively thin titanium nitride 118 on To;
On thick insulating film 2.

サイドウオール５ａ、５ｂ上のチタン膜６を窒化チタン
膜８に改質した後、イオン注入法などにより不純物をシ
リコン基板１上面に導入し熱処理を行なってソース・ド
レイン領域となる不純物拡散層９ａ　、９ｂを形成する
［第２図、（ｆ　）　］　、次に、０□を含む雰囲気中
で熱処理することにより窒化チタン膜８を酸化チタンｓ
１ｏに変え、その後ＣＶＤ法などにより酸化チタン膜１
０上に層間絶縁膜１１を形成する［第２図（Ｃ１＞］。After modifying the titanium film 6 on the sidewalls 5a and 5b into a titanium nitride film 8, impurities are introduced into the upper surface of the silicon substrate 1 by ion implantation or the like, and heat treatment is performed to form an impurity diffusion layer 9a which becomes a source/drain region. 9b [FIG. 2, (f)], the titanium nitride film 8 is converted into titanium oxide s by heat treatment in an atmosphere containing 0□.
1o, and then a titanium oxide film 1 by CVD method etc.
0 [FIG. 2 (C1>]).

次に、写真製版とエツチング法により層間絶縁膜１１．
１１化チタン膜１０の所望の位置にコンタクト孔１２８
゜１２１）を設けた後、スパッタ法などによりコンタク
ト孔１２ａ、１２ｂに配線用膜、たとえばアルミニウム
合金膜１３ａ、１３ｂを形成する［第２図（ｈ）］。Next, the interlayer insulating film 11 is formed by photolithography and etching.
A contact hole 128 is formed at a desired position in the titanium 11ide film 10.
121), wiring films, such as aluminum alloy films 13a and 13b, are formed in the contact holes 12a and 12b by sputtering or the like [FIG. 2(h)].

第２図（ｆ）で示した工程は、厚い絶縁１ＩＩ２上。The process shown in FIG. 2(f) is performed on the thick insulation 1II2.

サイドウオール５ａ、５ｂ上、シリコン基板１の主面上
、多結晶シリコン躾４０上に形成したチタンｌ１ｌＩ６
のシリサイド化を自己整合的に行ない、慢でソース・ド
レイン１１１ｗ１となるシリコン基板１の露出した部分
上とゲート電極となる多結晶シリコン膜４０上とにのみ
チタンシリサイド膜７ａ、７ｂ、７ｃを形成する工程で
ある。ここで重要なことは、素子間分離用の厚い絶縁ｌ
１１２上およびゲートとソース・ドイレン間の絶縁分離
に用いられているサイドウオール５ａ、５ｂ上にシリサ
イドを形成しないように、かつシリコン基板１の露出し
た部分および多結晶シリコン族４０は十分シリサイド化
させることである。責合ｍ以外の高融点金属シリサイド
はＳ＋原子の拡散に律速した反応で形成されるため、不
活性ガス（Ａｒなど）雰囲気中で高温・長時間のシリサ
イド化熱反応を行なうと、厚い絶縁１１！２上、サイド
ウオール５ａ　、　５ｂ上の未反応チタン膜６中にもシ
リコン基板１．多結晶シリコン１１４０から＄１原子が
拡散してシリサイドが形成される。これを防ぐためには
、シリサイド化のための熱処理温度・時間を厳密に制御
する必要があるが、これは非常に困難なことである。こ
の実施例で示したように、熱処理をＮ２雰囲気中で行な
うと、厚い絶縁膜２上、サイドウオール５ａ、５ｂ上の
チタンｌＩ６は急速に窒化チタンとなる。また窒化チタ
ンはシリサイド化しない。Titanium l1lI6 formed on the sidewalls 5a and 5b, on the main surface of the silicon substrate 1, and on the polycrystalline silicon layer 40.
silicide in a self-aligned manner, and titanium silicide films 7a, 7b, and 7c are formed only on the exposed portions of the silicon substrate 1 that will become the source/drain 111w1 and on the polycrystalline silicon film 40 that will become the gate electrode. This is the process of What is important here is the thick insulation l used for isolation between elements.
The exposed portion of the silicon substrate 1 and the polycrystalline silicon group 40 are sufficiently silicided so that silicide is not formed on the side walls 5a and 5b used for insulation separation between the gate and the source/drain. That's true. High-melting-point metal silicides other than silicides are formed by reactions controlled by the diffusion of S+ atoms. Therefore, if a high-temperature, long-term silicidation thermal reaction is performed in an inert gas (Ar, etc.) atmosphere, thick insulation 11 !2, and in the unreacted titanium film 6 on the sidewalls 5a and 5b, the silicon substrate 1. $1 atoms diffuse from the polycrystalline silicon 1140 to form silicide. In order to prevent this, it is necessary to strictly control the heat treatment temperature and time for silicidation, but this is extremely difficult. As shown in this embodiment, when the heat treatment is performed in an N2 atmosphere, the titanium lI6 on the thick insulating film 2 and on the sidewalls 5a and 5b rapidly turns into titanium nitride. Further, titanium nitride does not turn into silicide.

したがって、この実施例の場合、厚い絶縁Ｗａ２上。Therefore, in this example, on the thick insulation Wa2.

サイドウオール５ａ、５ｂ上のチタンｌＩ！６中にＳｌ
が拡散してきてシリサイド化する前に既に窒化している
ことになる。また、シリコン基板１上。Titanium lI on sidewalls 5a and 5b! Sl in 6
This means that it has already been nitrided before it diffuses and turns into silicide. Also, on the silicon substrate 1.

多結晶シリコン［１４０上の１１００ｎのチタン膜６を
Ｎ２雰囲気中で７００℃の熱処理を行なった場。A case where a 1100n titanium film 6 on polycrystalline silicon [140] was heat-treated at 700° C. in an N2 atmosphere.

合、ＲＢＳによる解析を行なったところ、それらの表面
には約２０ｒｖの薄い窒化チタンＩＩ　８が形成され、
その下には約２００ｎｓのチタンシリサイド膜（組成Ｇ
；ｔＴｌ　９１２　）７ａ、７ｂ、７ｃが形成されてい
ることがわかった。しかしながら、窒化チタン［１８は
導電体でこのままではゲートとソース・ドレイン閤、ま
た隣接するトランジスタ間が短絡するので、０□を含む
雰囲気中で熱処理を行なうと窒化チタン１１８は絶縁体
である酸化チタン−ｍｉｏとなる。最終的にはシリコン
基板１上、多結晶シリコン躾４０上に約２００＋ｖのチ
タンシリサイドＭ７ａ　、７ｂ　、７ａが、それらの上
に約２０ｎａ＋の酸化チタン１１１０が形成され、一方
、厚い絶縁膜２上、サイドウオール５ａ、５ｂ上に約１
００ｎ醜の酸化チタンｍｉｏが形成される。このとき、
シリサイド化されたゲート電−極、ソース・ドレイン領
域のシート抵抗は約１０／口であった。In this case, RBS analysis revealed that a thin layer of titanium nitride II 8 with a thickness of about 20 rv was formed on their surfaces.
Underneath it is a titanium silicide film (composition G
;tTl 912 ) 7a, 7b, and 7c were found to be formed. However, titanium nitride 118 is a conductor, and if left as it is, it will cause a short circuit between the gate, source/drain, and adjacent transistors, so if heat treatment is performed in an atmosphere containing 0 -mio. Finally, titanium silicides M7a, 7b, 7a of about 200+V are formed on the silicon substrate 1, on the polycrystalline silicon substrate 40, and titanium oxide 1110 of about 20Na+ is formed thereon, while on the thick insulating film 2, Approximately 1 on the side walls 5a and 5b
00n Ugly titanium oxide mio is formed. At this time,
The sheet resistance of the silicided gate electrode and source/drain regions was about 10/hole.

この実施例では、チタンシリサイドｌｌ７ａ、７ｂ、７
ｃ上に酸化チタン１１１０ａ、１０ｂ、１０Ｃ１さらに
層間絶縁１１１１ａ、１　ｌｂ　、１１ｃを形成してい
るが、一般的に層間絶縁膜の材料はシリコン酸化膜であ
る場合が多い。チタンシリサイド膜がシリコン酸化膜と
接している状態で熱処理を行なうと、両者の間に反応が
生じ、チタンシリサイド膜の膜質が劣化することがある
。しかし、この実施例のように、チタンシリサイドＭ７
ａ。In this example, titanium silicides 117a, 7b, 7
Titanium oxide 1110a, 10b, 10C1 and further interlayer insulation 1111a, 1 lb, 11c are formed on c, but the material of the interlayer insulation film is generally a silicon oxide film in many cases. If heat treatment is performed while the titanium silicide film is in contact with the silicon oxide film, a reaction may occur between the two and the quality of the titanium silicide film may deteriorate. However, as in this example, titanium silicide M7
a.

７ｂ、７ｃと層間絶縁膜１１ａ　、　１　ｌｂ　、　１
１ａ間に酸化チタン膜１０ａ　、１０ｂ　、　１ｏｃを
介するとチタンシリサイドｇ１７ａ　、７ｂ　、７ｃは
非常に安定である。但し、窒化チタン膜８を酸化チタン
暎１０に改質する際、酸化処理時間が長ずざると下のチ
タンシリサイドｌｌ１７ａ　、　　７ｂ　、　　７（！
も酸化される。このとき、約８００℃以下の温度で酸化
すればチタンシリサイドは酸化チタンとなり、チタンシ
リサイド１１７ａ　、７ｂ　、Ｔｏのシート抵抗が上昇
するため望ましくない。したがつ・て、約８００℃以上
の温度で酸化する必要があり、このときには、チタンシ
リサイド膜７ａ　、　　７ｂ　、　　７ｃ中のチタンは
酸化せずシリコンが酸化してこれらチタンシリサイド膜
上にシリコン醇化膜が形成されるが、チタンシリサイド
の抵抗はチタンで決まるのでシリコンの方が酸化しても
問題はなく、チタンシリサイド＠７ａ　、７ｂ　、７ｃ
のシート抵抗の上昇は生じない。7b, 7c and interlayer insulating film 11a, 1 lb, 1
When titanium oxide films 10a, 10b, 1oc are interposed between 1a, titanium silicides g17a, 7b, 7c are very stable. However, when modifying the titanium nitride film 8 to the titanium oxide film 10, if the oxidation treatment time is not long, the underlying titanium silicides 17a, 7b, 7(!
is also oxidized. At this time, if the titanium silicide is oxidized at a temperature of about 800° C. or lower, it becomes titanium oxide, which is not desirable because the sheet resistance of the titanium silicides 117a, 7b, and To increases. Therefore, it is necessary to oxidize at a temperature of about 800° C. or higher, and at this time, the titanium in the titanium silicide films 7a, 7b, 7c is not oxidized, but the silicon is oxidized and silicon molten is formed on these titanium silicide films. A film is formed, but since the resistance of titanium silicide is determined by titanium, there is no problem even if silicon is oxidized, and titanium silicide@7a, 7b, 7c
No increase in sheet resistance occurs.

また、チタンシリサイド膜７ａ、７ｂ、７ｃによりソー
ス・ドレイン領域のシート抵抗を低減させることができ
るので、その分不純物拡散層９ａ。Further, since the sheet resistance of the source/drain regions can be reduced by the titanium silicide films 7a, 7b, and 7c, the impurity diffusion layer 9a can be reduced accordingly.

９ｂの接合深さを浅くすることができ、ＬＳＩの高密度
・高集積化に当たって縦方向の素子構造の縮小化を容易
に実現することができる。The junction depth 9b can be made shallow, and the vertical element structure can be easily reduced in size when increasing the density and integration of LSI.

なお、上記実施例では、金属シリサイド膜としてチタン
シリサイド膜を示したが、金属シリサイド膜としてはＶ
、Ｚｒ　、Ｎｂ　、Ｈｆ　、Ｔａからなる群から任意に
選ばれた１物質のシリサイド膜であってもよく、これら
の場合にも上記実施例と同様の効果を奏する。In the above embodiment, a titanium silicide film was shown as the metal silicide film, but V
, Zr 2 , Nb 2 , Hf 2 , and Ta, and a silicide film made of one substance arbitrarily selected from the group consisting of , Zr 2 , Nb 2 , Hf 2 , and Ta may be used, and the same effects as in the above embodiment can be obtained in these cases as well.

また、上記実施例では、金属酸化膜として酸化チタン膜
を示したが、金属酸化膜上上てはｖ、ｚｒ　、Ｎｂ　、
Ｈｆ　、Ｔａからなる群から任意に選ばれた１物質の酸
化膜であってもよく、これらの場合にも上記実施例と同
様の効果を奏する。Further, in the above embodiment, a titanium oxide film was shown as the metal oxide film, but v, zr, Nb,
An oxide film of one substance arbitrarily selected from the group consisting of Hf and Ta may be used, and in these cases, the same effects as in the above embodiment can be achieved.

また、上記実施例では、コンタクト孔の配線用膜として
アルミニウム合金膜を示したが、配線用膜としては、Ｍ
Ｏ膜、またはＷｌｌ、またはＭＯ。In addition, in the above embodiment, an aluminum alloy film was used as the wiring film for the contact hole, but as the wiring film, M
O membrane, or Wll, or MO.

Ｗ、　Ｔａ　、　Ｔｉ　、　Ｖ、　Ｚｒ　、　Ｎｂ　、
　Ｈｆ　、　Ｃｒからなる群から任意に選ばれた１物質
のシリサイド膜もしくは３物質のシリサイド膜、または
ＴｉＷ。W, Ta, Ti, V, Zr, Nb,
A silicide film of one substance or a silicide film of three substances arbitrarily selected from the group consisting of Hf and Cr, or TiW.

Ｔｉ　Ｎ、Ｔａ　Ｎの群から任意に選ばれた１物質の金
属膜、またはこれらの膜およびアルミニウム合金膜の任
意の組合わせの多層膜であってもよく、これらの場合に
も上記実施例と同様の効果を秦する。It may be a metal film of one substance arbitrarily selected from the group of TiN and TaN, or a multilayer film of any combination of these films and an aluminum alloy film, and in these cases, the above embodiments may also be applied. Qin similar effect.

［発明の効果］ 以上のようにこの発明によれば、半導体シリコン基板上
にソース・ドレイン領域となる不純物拡散層を形成し、
上記基板上にゲート絶縁膜を形成し、ゲート絶縁膜上に
多結晶シリコンからなるゲート電極を形成し、ゲート、
電極の側部に該ゲート電極と不純物拡散層とを絶縁する
絶縁膜を゛形成し、不純物拡散層上およびゲート電極上
に金属シソサイド膜を自己整合的に形成し、金属シリサ
イド膜上および絶縁膜上に金属酸化膜を形成し、金属酸
化膜上に層間絶縁膜を形成したので、ゲート電極とソー
ス・ドイレン不純物層間の電気的絶縁特性が優れ、かつ
ゲート電極およびソース・ドレイン不純物拡散層のシー
ト抵抗がともに低く、かつ熱処理に対して安定で、かつ
浅い接合を有する不・耗物拡散層を備えた半導体装１を
得ることができる。[Effects of the Invention] As described above, according to the present invention, an impurity diffusion layer serving as a source/drain region is formed on a semiconductor silicon substrate,
A gate insulating film is formed on the substrate, a gate electrode made of polycrystalline silicon is formed on the gate insulating film, and the gate,
An insulating film is formed on the side of the electrode to insulate the gate electrode and the impurity diffusion layer, a metal silicide film is formed on the impurity diffusion layer and the gate electrode in a self-aligned manner, and a metal silicide film is formed on the metal silicide film and the insulation film. Since a metal oxide film is formed on the metal oxide film and an interlayer insulating film is formed on the metal oxide film, the electrical insulation properties between the gate electrode and the source/drain impurity layer are excellent, and the sheet of the gate electrode and source/drain impurity diffusion layer is It is possible to obtain a semiconductor device 1 including a consumable diffusion layer that has low resistance, is stable against heat treatment, and has a shallow junction.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の実施例である半導体装置を示す断面
図である。 第２図（ａ）〜（ｈ）はこの発明の実施例である半導体
装置の製造方法の主要工程段階における状態を示す断面
図である。 第３図は従来のＭＯ８型電界効果トランジスタを示す断
面図である。 図において、１はシリコン基板、２は厚い絶縁膜、３．
３０は薄い絶縁膜、４．４０は多結晶シリコン摸、５ａ
　、５ｂはサイドウオール、６はチタン膜、７ａ、７ｂ
、７ｃはチタンシリサイド膜、８は窒化チタン膜、９ａ
　、　９ｂ　、　１５ａ　、　１５ｂハネ純物拡ｗｌｌ
ｌｌ、１０．１０ａ　、１０ｂ　、１０ｃハＷｉ化チタ
ンＷＪ、１１．１１ａ、１１ｂ、１１ｃは層間絶縁膜、
１２８．１２ｔｌはコンタクト孔、１３ａ、１３ｂはア
ルミニウム合金膜、１４はしきい値電圧制御用不純物層
である。 なお、各図中同一符号は同一または相当部分を示す。 代　　理　　人　　　　　大　　岩　　増　　雄第１　
図 第２図 ３：噂−Ｉ絶縁膜 ４：り結晶シリコン謄 第２Ｉ１２１ ６　：　デ　７Ｚ−８莫 ８：４１化ナデンＩＩ笑 第３図 １５ａ５１ｓｂ　：　ＦＮ’Ｍｔ政層 手続補正書（自発） ｖ１％　１ 昭和　　　　　　　　日 １、事件の表示　　　特願昭６０−１１２６０６号２、
発明の名称 半導体装置 ３、補正をする者 ５、補正の対象 明細書の特許請求の範囲の欄および発明の詳細な説明の
欄 ６、補正の内容 （１）　明細書の特許請求の範囲を別紙のとおり。 （２）　明細書第１７頁第５行の「３物質の」を「２物
質の」に補正する。 以上 ２、特許請求の範囲 （１）　　ＭＯ３型電界効果トランジスタであって、 半導体シリコン基板と、 前記半導体シリコン基板上に形成され、ソース・ドレイ
ン領域となる不純物拡散層と、前記半導体シリコン基板
上に形成されるゲート絶縁膜と、 前記ゲート絶縁膜上に形成され、多結晶シリコンからな
るゲート電極と、 前記ゲート電極の側部に該ゲート電極および前記不純物
拡散層に接触して形成され、該ゲート電橋と該不純物拡
散層とを絶縁する絶縁膜と、前記不純物拡散層上および
前記、ゲート電極上に形成される金属シリサイド膜と、 前記金属シリサイド膜上および前記絶縁膜上に形成され
る金属酸化膜と、 前記金ｒＪＡＭ（ｔＳＢｉ上に形成されるＮ量線縁膜と
を備えた半導体装置。 （２）　前記層間絶縁膜および前記金属酸化膜を貫通す
るコンタクト孔が設けられ、 前記コンタクト孔には前記金属シリサイド膜と電気的に
接続する配線用属膜が形成される特許請求の範囲第１項
記載の半導体装置。 （３）　前記金属シリサイド膜は、Ｔｉ　、Ｖ。 Ｚｒ　、Ｎｂ　、Ｈｒ　、Ｔａからなる群から任意に選
ばれた１物質のシリサイド膜である特許請求の範囲第１
項記載の半導体装１゜ （４）　前記金属酸化膜は、ＴＩ　、Ｖ、Ｚｒ　。 Ｎｂ、Ｈｆ、”ｊａからなる群から任意に選ばれた１物
質の酸化膜である特許請求の範囲第１項記載の半導体装
置。 （５）　前記配線用膜は、ＭＯ膜である特許請求の範囲
第２項記載の半導体装１゜ ゛（６）　前記配線用膜は、ＷＳである特許請求の範囲
第２項記載の半導体装置。 （７）　前記配線用膜は、Ｍｏ　、　Ｗ、　Ｔａ　、　
ＴＩ　、Ｖ、Ｚｌ’　、Ｎｂ　、Ｈｒ　、　Ｃｒからな
る群から任意に選ばれた１物質のシリサイド膜である。 特許請求の範囲第２項記載の半導体装置。 （８）　前記配線用膜は、Ｍｏ、Ｗ、　Ｔａ　、　ＴＩ
　、Ｖ、Ｚｒ　、Ｎｂ　、Ｈｆ　、Ｃｒからなる群から
任意に選ばれた。？−物質のシリサイド膜である特許請
求の範囲第２項記載の半導体装置。 （９）　前記配線用膜は、ＴＩ　Ｗ、ＴＩ　Ｎ、ＴａＮ
、Ａｕ合金の群から任意に選ばれた１物質の腹である特
許請求の範囲第２項記載の半導体装置。 （１０）　前記配線用膜は、 ＭＯ膜、 ｗｍ、 Ｍｏ、Ｗ、Ｔａ、ＴＩ　、Ｖ、Ｚｒ、Ｎｂ、Ｈｆ。 Ｃｒからなる群から任意に選ばれた１物質のシリサイド
膜、 Ｍｏ、Ｗ、Ｔａ、Ｔｉ、Ｖ、Ｚｒ、Ｎｂ、Ｈｆ。 Ｃｒからなる群から任意に選ばれた２物質のシリサイド
膜、および ＴＩ　Ｗ、ＴＩ　Ｎ、Ｔａ　Ｎ、Ａｌ合金の群から任意
に選ばれた１物質の膜、 の任意の組合わせの多層膜である特許請求の範囲第２項
記載の半導体装置。FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the invention. FIGS. 2(a) to 2(h) are cross-sectional views showing the main process steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view showing a conventional MO8 type field effect transistor. In the figure, 1 is a silicon substrate, 2 is a thick insulating film, and 3.
30 is a thin insulating film, 4.40 is a polycrystalline silicon model, 5a
, 5b is a side wall, 6 is a titanium film, 7a, 7b
, 7c is a titanium silicide film, 8 is a titanium nitride film, 9a
, 9b , 15a , 15b pure substance expansion wll
11.11a, 11b, 11c are interlayer insulating films,
128.12tl is a contact hole, 13a and 13b are aluminum alloy films, and 14 is an impurity layer for controlling threshold voltage. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa 1st
Figure 2 Figure 3: Rumor-I Insulating Film 4: Crystalline Silicon Transcript No. 2 I121 6: De 7Z-8 Mo 8:41 Naden II LOL Figure 3 15a51sb: FN'Mt Political Class Procedures Amendment (Spontaneous) v1 % 1 Showa Day 1, Incident Display Patent Application No. 112606, 1986 2,
Name of the invention: Semiconductor device 3; Person making the amendment 5; Claims column of the specification to be amended; Detailed description of the invention column 6; Contents of the amendment (1) Attachment of the claims of the specification As of. (2) "3 substances" on page 17, line 5 of the specification is amended to "2 substances." Above 2, Claim (1) An MO3 field effect transistor comprising: a semiconductor silicon substrate; an impurity diffusion layer formed on the semiconductor silicon substrate and serving as a source/drain region; a gate insulating film to be formed; a gate electrode formed on the gate insulating film and made of polycrystalline silicon; and a gate electrode formed on a side of the gate electrode in contact with the gate electrode and the impurity diffusion layer; an insulating film that insulates the electric bridge and the impurity diffusion layer; a metal silicide film formed on the impurity diffusion layer and the gate electrode; and a metal formed on the metal silicide film and the insulating film. A semiconductor device comprising: an oxide film; and an N-domain edge film formed on the gold rJAM (tSBi). (2) A contact hole penetrating the interlayer insulating film and the metal oxide film is provided, and the contact hole 2. The semiconductor device according to claim 1, wherein a wiring metal film electrically connected to the metal silicide film is formed. (3) The metal silicide film includes Ti, V, Zr, Nb, Hr. Claim 1, which is a silicide film of one substance arbitrarily selected from the group consisting of , Ta.
1. (4) The metal oxide film is made of TI, V, or Zr. The semiconductor device according to claim 1, which is an oxide film of one substance arbitrarily selected from the group consisting of Nb, Hf, and "ja". (5) The semiconductor device according to claim 1, wherein the wiring film is an MO film. Semiconductor device according to claim 2 (6) The semiconductor device according to claim 2, wherein the wiring film is WS. (7) The wiring film is made of Mo, W, Ta,
This is a silicide film of one substance arbitrarily selected from the group consisting of TI, V, Zl', Nb, Hr, and Cr. A semiconductor device according to claim 2. (8) The wiring film is made of Mo, W, Ta, TI
, V, Zr, Nb, Hf, and Cr. ? - The semiconductor device according to claim 2, which is a silicide film of a substance. (9) The wiring film is TIW, TIN, TaN.
, Au alloy. (10) The wiring film is an MO film, wm, Mo, W, Ta, TI, V, Zr, Nb, Hf. A silicide film of one substance arbitrarily selected from the group consisting of Cr, Mo, W, Ta, Ti, V, Zr, Nb, and Hf. A multilayer film of any combination of a silicide film of two substances arbitrarily selected from the group consisting of Cr, and a film of one substance arbitrarily selected from the group of TIW, TIN, TaN, and Al alloys. A semiconductor device according to claim 2.

Claims (10)

【特許請求の範囲】[Claims] （１）ＭＯＳ型電界効果トランジスタであって、半導体
シリコン基板と、 前記半導体シリコン基板上に形成され、ソース・ドレイ
ン領域となる不純物拡散層と、 前記半導体シリコン基板上に形成されるゲート絶縁膜と
、 前記ゲート絶縁膜上に形成され、多結晶シリコンからな
るゲート電極と、 前記ゲート電極の側部に該ゲート電極および前記不純物
拡散層に接触して形成され、該ゲート電極と該不純物拡
散層とを絶縁する絶縁膜と、前記不純物拡散層上および
前記ゲート電極上に形成される金属シリサイド膜と、 前記金属シリサイド膜上および前記絶縁膜上に形成され
る金属酸化膜と、 前記金属酸化膜上に形成される層間絶縁膜とを備えた半
導体装置。(1) A MOS field effect transistor, which includes a semiconductor silicon substrate, an impurity diffusion layer formed on the semiconductor silicon substrate and serving as a source/drain region, and a gate insulating film formed on the semiconductor silicon substrate. , a gate electrode formed on the gate insulating film and made of polycrystalline silicon; a gate electrode formed on a side of the gate electrode in contact with the gate electrode and the impurity diffusion layer; a metal silicide film formed on the impurity diffusion layer and the gate electrode; a metal oxide film formed on the metal silicide film and the insulation film; and a metal oxide film formed on the metal oxide film. A semiconductor device comprising: an interlayer insulating film formed in a semiconductor device; （２）前記層間絶縁膜および前記金属酸化膜を貫通する
コンタクト孔が設けられ、 前記コンタクト孔には前記金属シリサイド膜と電気的に
接続する配線用属膜が形成される特許請求の範囲第１項
記載の半導体装置。(2) A contact hole penetrating the interlayer insulating film and the metal oxide film is provided, and a wiring metal film electrically connected to the metal silicide film is formed in the contact hole. 1. Semiconductor device described in Section 1. （３）前記金属シリサイド膜は、Ｔｉ、Ｖ、Ｚｒ、Ｎｂ
、Ｈｆ、Ｔａからなる群から任意に選ばれた１物質のシ
リサイド膜である特許請求の範囲第１項記載の半導体装
置。(3) The metal silicide film is made of Ti, V, Zr, Nb
2. The semiconductor device according to claim 1, wherein the semiconductor device is a silicide film of one substance arbitrarily selected from the group consisting of , Hf, and Ta. （４）前記金属酸化膜は、Ｔｉ、Ｖ、Ｚｒ、Ｎｂ、Ｈｆ
、Ｔａからなる群から任意に選ばれた１物質の酸化膜で
ある特許請求の範囲第１項記載の半導体装置。(4) The metal oxide film is made of Ti, V, Zr, Nb, Hf
2. The semiconductor device according to claim 1, wherein the semiconductor device is an oxide film of one material arbitrarily selected from the group consisting of , Ta. （５）前記配線用膜は、Ｍｏ膜である特許請求の範囲第
２項記載の半導体装置。(5) The semiconductor device according to claim 2, wherein the wiring film is a Mo film. （６）前記配線用膜は、Ｗ膜である特許請求の範囲第２
項記載の半導体装置。(6) Claim 2, wherein the wiring film is a W film.
1. Semiconductor device described in Section 1. （７）前記配線用膜は、Ｍｏ、Ｗ、Ｔａ、Ｔｉ、Ｖ、Ｚ
ｒ、Ｎｂ、Ｈｆ、Ｃｒからなる群から任意に選ばれた１
物質のシリサイド膜である特許請求の範囲第２項記載の
半導体装置。(7) The wiring film is made of Mo, W, Ta, Ti, V, Z.
1 arbitrarily selected from the group consisting of r, Nb, Hf, and Cr
3. The semiconductor device according to claim 2, which is a silicide film of a substance. （８）前記配線用膜は、Ｍｏ、Ｗ、Ｔａ、Ｔｉ、Ｖ、Ｚ
ｒ、Ｎｂ、Ｈｆ、Ｃｒからなる群から任意に選ばれた３
物質のシリサイド膜である特許請求の範囲第２項記載の
半導体装置。(8) The wiring film is made of Mo, W, Ta, Ti, V, Z.
3 arbitrarily selected from the group consisting of r, Nb, Hf, and Cr
3. The semiconductor device according to claim 2, which is a silicide film of a substance. （９）前記配線用膜は、ＴｉＷ、ＴｉＮ、ＴａＮ、Ａｌ
合金の群から任意に選ばれた１物質の膜である特許請求
の範囲第２項記載の半導体装置。(9) The wiring film is made of TiW, TiN, TaN, Al
3. The semiconductor device according to claim 2, which is a film of one substance arbitrarily selected from the group of alloys. （１０）前記配線用膜は、 Ｍｏ膜、 Ｗ膜、 Ｍｏ、Ｗ、Ｔａ、Ｔｉ、Ｖ、Ｚｒ、Ｎｂ、Ｈｆ、Ｃｒか
らなる群から任意に選ばれた１物質のシリサイド膜、 Ｍｏ、Ｗ、Ｔａ、Ｔｉ、Ｖ、Ｚｒ、Ｎｂ、Ｈｆ、Ｃｒか
らなる群から任意に選ばれた３物質のシリサイド膜、お
よび ＴｉＷ、ＴｉＮ、ＴａＮ、Ａｌ合金の群から任意に選ば
れた１物質の膜、 の任意の組合わせの多層膜である特許請求の範囲第２項
記載の半導体装置。(10) The wiring film is a Mo film, a W film, a silicide film of one substance arbitrarily selected from the group consisting of Mo, W, Ta, Ti, V, Zr, Nb, Hf, and Cr, Mo, W , a silicide film of three substances arbitrarily selected from the group consisting of Ta, Ti, V, Zr, Nb, Hf, and Cr, and a film of one substance arbitrarily selected from the group of TiW, TiN, TaN, and Al alloys. 3. The semiconductor device according to claim 2, which is a multilayer film of any combination of .
JP60112606A 1985-05-25 1985-05-25 Semiconductor device Pending JPS61270870A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP60112606A JPS61270870A (en) 1985-05-25 1985-05-25 Semiconductor device
KR1019850008215A KR890004464B1 (en) 1985-05-25 1985-11-04 Semiconductor device
DE19863614793 DE3614793A1 (en) 1985-05-25 1986-05-02 Semiconductor component and its production

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60112606A JPS61270870A (en) 1985-05-25 1985-05-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61270870A true JPS61270870A (en) 1986-12-01

Family

ID=14590935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60112606A Pending JPS61270870A (en) 1985-05-25 1985-05-25 Semiconductor device

Country Status (3)

Country Link
JP (1) JPS61270870A (en)
KR (1) KR890004464B1 (en)
DE (1) DE3614793A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0594963A (en) * 1990-08-16 1993-04-16 Internatl Business Mach Corp <Ibm> Method for forming fire resisting metal silicide layers having various thicknesses for integrated circuit
US5341028A (en) * 1990-10-09 1994-08-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and a method of manufacturing thereof

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63221647A (en) * 1987-03-10 1988-09-14 Mitsubishi Electric Corp Manufacture of semiconductor device
KR930006128B1 (en) * 1991-01-31 1993-07-07 삼성전자 주식회사 Metal wiring method of semiconductor device
US5229325A (en) * 1991-01-31 1993-07-20 Samsung Electronics Co., Ltd. Method for forming metal wirings of semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4228212A (en) * 1979-06-11 1980-10-14 General Electric Company Composite conductive structures in integrated circuits
US4521952A (en) * 1982-12-02 1985-06-11 International Business Machines Corporation Method of making integrated circuits using metal silicide contacts
US4629635A (en) * 1984-03-16 1986-12-16 Genus, Inc. Process for depositing a low resistivity tungsten silicon composite film on a substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0594963A (en) * 1990-08-16 1993-04-16 Internatl Business Mach Corp <Ibm> Method for forming fire resisting metal silicide layers having various thicknesses for integrated circuit
US5341028A (en) * 1990-10-09 1994-08-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and a method of manufacturing thereof
US5444282A (en) * 1990-10-09 1995-08-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and a method of manufacturing thereof

Also Published As

Publication number Publication date
DE3614793A1 (en) 1986-11-27
KR890004464B1 (en) 1989-11-04
KR860009497A (en) 1986-12-23
DE3614793C2 (en) 1989-01-26

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