JPH01243460A - Manufacture of semiconductor storage device - Google Patents

Abstract

PURPOSE:To enable electrically positive connection by conducting silicidation extending from the surface of a source or a drain on the trench side of the source or the drain in a switching MISFET over the surface of the upper end of an electrode in the trench. CONSTITUTION:A trench 9 is cut to the main surface of a semiconductor substrate 1, electrodes 11, 13 are formed into the trench 9, a switching MISFET is shaped near the trench 9, and silicidation or selective CVD is performed extending over the surface of the upper end of the electrode 13 from the surface of a source or a drain on the trench side in the source or the drain (an n<-> type semiconductor region 6). Consequently, since the source or the drain 6 and the electrode 13 are connected, a silicide film or a silicon film can be shaped onto the surface of the electrode 13 and the surface of the source or drain 6 in the switching MISFET even when an silicon oxide film slightly remains on these surfaces. Accordingly, the laminated electrode and the source or the drain can be connected electrically and positively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a technique that is effective when applied to a dynamic RAM.

[Conventional technology]

Dynamic RAM memory cells are switching MI
It consists of an SFET and a capacitive element, and in order to miniaturize memory cells, a trench capacitor was developed as one of the capacitive elements.
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This trench capacitor has, for example, the following structure. That is, by digging a groove in the main surface of a semiconductor substrate,
A cylindrical plate electrode having a bottom and side walls and an open top is embedded in this groove. The plate electrode and the semiconductor substrate are insulated with a silicon oxide film. Then, a storage electrode is embedded in the plate electrode via a dielectric film. this? ?
The upper end of the f& electrode is connected to the side surface of the semiconductor substrate exposed by selectively removing the silicon oxide film on the side surface of the trench. An n-type semiconductor region is formed near a portion of the semiconductor substrate to which the storage electrode is connected;
By integrating this n° type semiconductor region with either the source or drain of the switching MISFET.

The storage electrode and the source or drain are connected. Further, since the word line extends above the storage electrode, an interlayer insulating film made of a silicon oxide film is provided.

Next, a method for forming the n-type semiconductor region for connecting the storage electrode with either the source or the drain will be explained.
P) is formed by diffusing through the connection portion between the storage electrode and the semiconductor substrate. next.

A silicon oxide film serving as an interlayer insulating film on the storage electrode is formed by thermally oxidizing the surface of the storage electrode.

[Problem to be solved by the invention]

The inventor of the present invention discovered the first problem as a result of studying the trench capacitor.

That is, in the trench capacitor described above, in order to connect the upper end of the storage electrode to the semiconductor substrate through the sidewalls of the trench, it was necessary to etch the silicon oxide film on the sidewalls of the trench. However, the etching of the silicon oxide film on the sidewalls of this trench is often incomplete, and the upper end of the storage electrode is sometimes not connected to the semiconductor substrate. In this way, if the storage electrode is not connected to the semiconductor substrate, the n-type semiconductor region formed by diffusion of impurities from the storage electrode will not be formed, and the trench capacitor will not be connected to the switching MISF.
There was a problem that it became impossible to connect to ET.

Furthermore, in order to form the interlayer insulating film on the storage electrode thickly so as to obtain sufficient dielectric breakdown voltage in all memory cells, the thermal oxidation time must be lengthened, and the A problem arises in that the diffusion of the n1 type semiconductor region formed by impurity diffusion becomes too large, and the separation distance between adjacent memory cells becomes small, resulting in incomplete element isolation. For this reason, the insulating film on the storage electrode cannot be formed sufficiently thick, and some memory cells have insufficient dielectric breakdown voltage of the insulating film between the storage electrode and the word line. There was also the problem.

An object of the present invention is to provide a technique that can reliably electrically connect a storage electrode and a source or drain of a memory cell.

Another object of the present invention is to provide a technique that can form an insulating film with sufficient dielectric breakdown voltage between a storage electrode of a memory cell and a word line.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a method of manufacturing a semiconductor memory device in which a memory cell includes a switching MISFET and a trench capacitor, a step of forming an electrode in the groove after digging a groove in the main surface of the semiconductor substrate; forming a switching MISFET near the groove on the main surface;
connecting the source or drain and the electrode by performing silicidation from the surface of the source or drain on the groove side of the source or train of the MISFET to the upper end surface of the electrode in the groove; It is prepared.

[Effect]

According to the above-mentioned method, even if a small amount of silicon oxide film remains on the surface of the storage electrode or the source or drain of the switching MISFET, silicide film or polysilicon film can be formed on the surface of the storage electrode or the source or drain of the switching MISFET. Therefore, the storage electrode and the source or drain can be reliably connected.

In addition, since an n'-type semiconductor region formed by diffusion of impurities from the storage electrode into the semiconductor substrate is not used to connect the storage electrode to the source or drain of the switching MISFET, the n'''-type semiconductor region is large. Since there is no limit to the thermal oxidation time of the upper surface of the storage electrode in order to prevent incomplete device isolation from the adjacent memory cell, the upper surface of the storage electrode can be thermally oxidized for a sufficiently long time. Therefore, an insulating film having sufficient dielectric breakdown voltage can be formed between the storage electrode and the word line.

These things can improve the electrical reliability of the semiconductor memory device.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view of a dynamic RAM memory cell formed by a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of the memory cell shown in FIG. 1 taken along the line ■--■.

In FIGS. 1 and 2, 1 is a semiconductor substrate made of p-single crystal silicon, and 2 is a field insulating film made of silicon oxide film. A P-type channel stopper region 3 is provided below the field insulating film 2. The memory cell consists of a switching MISFET and a trench capacitor, and the switching MISFET consists of a gate insulating film 4 made of a silicon oxide film and a two-layer structure in which a metal silicide film such as a tungsten silicide film is formed on a polycrystalline silicon film. It is composed of a gate electrode 5 made of a film, and n° type semiconductor regions 6 that serve as source and drain regions. The gate electrode 5 also serves as a word line. A silicon oxide film 7 is provided on the gate electrode 5, and a side wall 8 made of a silicon oxide film is provided on the side surface of the gate electrode 5. On the other hand, the trench capacitor is a switching MIS on the main surface of the semiconductor substrate 1.
A plate electrode 11 made of, for example, a polycrystalline silicon film, and a dielectric film 12 made of a two-layer film of, for example, a silicon nitride film and a silicon oxide film, which are provided in a groove 9 dug in the vicinity of the FET. For example, the storage electrode 13 is made of a polycrystalline silicon film.

Note that the lead line for indicating the groove 9 indicates the wall surface of the groove 9. The plate electrode 11 is connected to the semiconductor substrate 1 at the bottom of the groove 9, and an n'' semiconductor region 10 is provided around the connecting portion between the plate electrode 11 and the semiconductor substrate 1. This n゛゛ semiconductor region 10 connects the plate electrodes 11 of each trench capacitor, and has a voltage of 1/2 V c c at the peripheral part of the memory mat.
For example, it is connected to wiring that supplies 2.5V. Further, an insulating film 19 made of a silicon oxide film is provided on the side wall of the groove 9, and the plate electrode 11 and the semiconductor substrate 1 (P
It insulates between the ゛-type regions. The plate electrode 11 has a bottom plate and side walls, and has a cylinder-like shape with an open top end.

A storage electrode 13 is embedded in this cylinder-like plate electrode 11 with a dielectric film 12 interposed therebetween. 14 is an interlayer insulating film that insulates the storage electrode 13 and the gate electrode (word line) 5, and is made of a silicon oxide film.

The n-type semiconductor region 6 on the trench 9 side of the switching MISFET and the storage electrode 13 are connected by a titanium silicide (TiSi) film 15 formed on their surfaces. The titanium silicide film 15 is also formed on the surface of the n-type semiconductor region 6 on the side to which the data line 18 is connected. In FIG. 1, the portion where the titanium silicide film 15 is provided is shown with diagonal lines. The titanium silicide film 15 is provided on as much of the surface of the storage electrode 13 as possible, for example, about half, and is provided on the n-
On the surface of the type semiconductor region 6, it is formed over almost the entire area exposed from the sidewall 8 and the gate electrode 5. Since the resistance value of the titanium silicide film 15 is very small, the connection resistance between the storage electrode 13 and the n' semiconductor region 6 is small. Further, by providing a titanium silicide film 15 on the surface of each n-type semiconductor region 6 on both sides of the gate electrode 5, the switching MISFE
When T is conductive, for example, from the titanium silicide film 15 connected to the data line 18 to the underlying n-type semiconductor region 6. The resistance value from the channel region (inversion layer) to the n-type semiconductor region 6° on the trench 9 side to the titanium silicide film 15 thereon can be reduced. This allows switching MIS
The operating speed of the FET can be improved.

16 is silicon oxide film or phosphosilicate glass (PSG)
) film, and 17 is a switching MISF which connects the data line 18 via the titanium silicide film 15.
This is a connection hole for connecting to ET. The data line 18 is
For example, it is made of an aluminum film.

Next, a specific method of manufacturing the memory cell will be described.

3 to 6 are cross-sectional views of the same portion as FIG. 2 in the manufacturing process of the memory cell shown in FIGS. 1 and 2.

In the method for manufacturing the memory cell of this embodiment, first, as shown in FIG. 3, a field insulating film 2 and a p-type channel stopper region 3 are formed on a predetermined portion of the main surface of a semiconductor substrate 1. Next, a trench 9 is dug at a predetermined position in a portion of the main surface of the semiconductor substrate 1 exposed from the field insulating film 2, and then a groove 9 is formed, for example, by CVD.
A silicon oxide film 19 is formed in the groove 9 and on the semiconductor substrate 1.
form.

This was etched using anisotropic dry etching.

Silicon oxide film 19 is left only on the side walls of trench 9. next.

A polysilicon film 11 is formed in the groove 9 and on the semiconductor substrate 1, and phosphorus (P) is diffused into it to make it conductive.

At this time, phosphorus (P) flows from the bottom of the groove 9 into the semiconductor substrate 1.
is diffused to form an n-type semiconductor region 10. Next, a resist film is buried in the trench 9, and using this as a mask, the upper end portion of the trench 9 and the portion above the semiconductor substrate 1 of the polysilicon film 11 are etched. This etching completes the plate electrode 11. After etching, the resist film in the groove 9 is removed. Next, a dielectric film 12 is formed on the surface of the plate electrode 11 using, for example, a silicon nitride film formed by CVD. Next, a storage electrode 13 is formed by filling the trench 9 with a polysilicon film by, for example, CVD. For example, phosphorus (
P) is diffused to make it conductive.

Next, the polysilicon film forming the storage electrode 13 is thermally oxidized to form an interlayer insulating film 14 made of a silicon oxide film.

In this embodiment, when forming the interlayer insulating film 14, an n-type semiconductor region formed by diffusion of impurities from the storage electrode (polysilicon) 13 is used to connect the storage electrode 13 with the source or drain of the switching MI 5FET. Therefore, the time for thermal oxidation to form the interlayer insulating film 14 is not limited to prevent excessive diffusion of the n+ type semiconductor region, and therefore the storage electrode 13
is oxidized for a sufficiently long time to form a thick interlayer insulating film 14.
can be formed.

After forming the interlayer insulating film 14, the exposed portion of the main surface of the semiconductor substrate 1 is thermally oxidized to form the gate insulating film 4 made of a silicon oxide film. Next, as shown in Figure 4,
For example, by CVD, a polysilicon film and, for example, a tungsten silicide (WSi) film are laminated in order from the bottom, and then a silicon oxide film 7 is formed on top of this, and then these are patterned to form the gate electrode 5. Also, a silicon oxide film 7 having the same pattern as the gate electrode 5 is formed. next.

Using the gate electrode 5 and the silicon oxide film 7 as a mask, ions of, for example, phosphorus (P) are implanted to form a source.

An n-type semiconductor region 6 that will become a drain is formed. next,
For example, a silicon oxide film is formed on the entire surface of the semiconductor substrate 1 by CVD, and this is etched by anisotropic dry etching until the surface of the n-type semiconductor region 6 and the surface of the storage electrode 13 are exposed to form the sidewall 8. Form. Etching when forming the sidewall 8 can be performed accurately with the exposed surfaces of the storage electrode 13 and the n-type semiconductor region 6 as the etching end points, so that the silicon oxide film 19 is not etched. , storage electrode 1
3 and the semiconductor substrate 1 can be maintained in a good state. Next, a titanium (Ti) film is formed on the entire surface of the semiconductor substrate 1 by sputtering, for example, and then annealed (A r +
N, atmosphere, 600°C), as shown in Figure 6,
The titanium film and the storage electrode (polysilicon) 13 and n
A silicidation process is performed on each surface of the - type semiconductor region (single crystal silicon) 6. Due to this silicidation, a titanium silicide (TiSi2) film 15 is formed on the surfaces of the storage electrode 13 and the n-type semiconductor region 6. On the other hand, field insulating film 2. On the silicon oxide film 7° sidewall 8, the titanium film becomes a titanium nitride (TiN) film 15A. This titanium nitride film 15
A is etched using a mixed solution of H2O2, NH4OH, and H20, leaving only the titanium silicide film 15.

The titanium silicide film 15 covers the exposed storage electrode 13.
．． They are formed in self-alignment without alignment on each surface of the n-type semiconductor region 6. Additionally, metals generally have the effect of reducing silicon oxide films to silicon, and this is particularly noticeable with titanium, so a small amount of silicon oxide film may remain on the storage electrode 13 and the n° type semiconductor region 6. The titanium silicide film 15 can be formed even if In addition,
Instead of titanium.

So-called high melting point metals such as tungsten (W) and molybdenum (Mo) can be used.

After forming the titanium silicide film 15, the interlayer insulating film 16 shown in FIG. Connection hole 17. Each of the data lines 18 is formed.

Note that instead of connecting the storage electrode 13 and the n-type semiconductor region 6 with the titanium silicide film 15, a silicon film is grown from the surface of the storage electrode 13 to the surface of the n-type semiconductor region 6 by selective CVD. You can also connect using In selective CVD, the gas components are SiH, CR-H2-HCQ
, the gas pressure is 70 Torr, and PH3 gas is introduced to make the silicon film to be grown conductive.

Further, the etching for exposing the surfaces of the storage electrode 13 and the n-type semiconductor region 6 may be performed separately from the etching for forming the sidewall 8 using a resist film. In this way, over-etching can be avoided when forming the sidewall 8, so that a decrease in the film thickness of the field insulating film 2, that is, a decrease in dielectric breakdown voltage can be prevented.

As can be seen from the above description, 1. According to this embodiment, after trenches 9 are dug in the main surface of the semiconductor substrate 1, electrodes (plate electrodes 13) are formed in the trenches 9, and the semiconductor A switching MISFET is formed in the vicinity of the groove 9 on the main surface of the substrate 1, and the source or drain (n-type semiconductor region 6) of the MISFET is formed from the surface of the source or drain 6 on the groove side into the groove 9. By connecting the source or drain 6 and the electrode 13 by performing silicidation or selective CVD over the upper surface of the electrode 13, the silicidation can be performed on the surface of the electrode 13 or the source or drain of the switching MISFET. Even if a small amount of silicon oxide film remains on the surface of the electrode 13, a silicide film or a silicon film can be formed on the surface, so that the electrode 13 and the source or drain 6 can be electrically connected reliably. can do.

Furthermore, since an n° type semiconductor region formed by diffusion of impurities from the electrode 13 into the semiconductor substrate 1 is not used to connect the electrode 13 to the source or drain 6 of the switching MISFET, the upper surface of the electrode 13 is thermally oxidized. Therefore, the n+ type semiconductor region does not extend greatly and device isolation from adjacent memory cells becomes incomplete, and the upper surface of the electrode 13 can be thermally oxidized for a sufficiently long time to form a thick silicon oxide film 14. can. This makes it possible to improve the dielectric breakdown voltage between the electrode 13 and the word line (gate electrode 5) disposed thereon. These things can improve the electrical reliability of the semiconductor memory device.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, the storage electrode of the trench capacitor and the source or drain of the switching MI 5FET can be electrically connected reliably. Further, an insulating film with sufficient dielectric breakdown voltage can be formed between the storage electrode and the word line. These can improve the electrical reliability of the semiconductor memory device.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a dynamic RAM memory cell formed by a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross section of the memory cell shown in FIG. 1 taken along the n-H cutting line. 3 to 6 are cross-sectional views of the same portion as FIG. 2 in the manufacturing process of the memory cell shown in FIGS. 1 and 2. In the figure, 6... n-type semiconductor region, 7... silicon oxide film, 8... side wall, 11... plate electrode, 12... dielectric film, 13... storage electrode, 14・
...Interlayer insulating film, 15...Titanium silicide film. Figure 2 Figure 3 Figure 4 Figure 1 (P-) Figure 5 Figure 6

Claims (1)

[Claims] 1. In a method of manufacturing a semiconductor memory device in which a memory cell includes a switching MISFET and a trench capacitor, a step of forming an electrode in the groove after digging a groove in the main surface of the semiconductor substrate; forming a switching MISFET near the groove on the main surface;
A step of connecting the source or drain to the electrode by performing silicidation or selective CVD from the surface of the source or drain on the groove side to the upper end surface of the electrode in the groove of the SFET. A method for manufacturing a semiconductor memory device, comprising: