JPH01291450A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01291450A JPH01291450A JP12235788A JP12235788A JPH01291450A JP H01291450 A JPH01291450 A JP H01291450A JP 12235788 A JP12235788 A JP 12235788A JP 12235788 A JP12235788 A JP 12235788A JP H01291450 A JPH01291450 A JP H01291450A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- reaction barrier
- titanium
- semiconductor device
- titanium nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000006243 chemical reaction Methods 0.000 claims abstract description 21
- 230000004888 barrier function Effects 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000010936 titanium Substances 0.000 claims abstract description 16
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 16
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 12
- 230000008018 melting Effects 0.000 claims abstract description 12
- 238000002844 melting Methods 0.000 claims abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 12
- 150000003608 titanium Chemical class 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052760 oxygen Inorganic materials 0.000 abstract description 5
- 239000001301 oxygen Substances 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 3
- 238000010438 heat treatment Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000001603 reducing effect Effects 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関し、特に高温の熱処理に対し
て安定な耐熱性配線を有する半導体装置に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having heat-resistant wiring that is stable against high-temperature heat treatment.
従来、第２図に示す断面図のような高融点金属配線を有
する半導体装置が提案されている。これは、半導体基板
例えばシリコン基板１上に絶縁層２を熱酸化または化学
的気相成長法（以下ＣＶＯという）により設け、写真製
版及びエツチング処理によりコンタクトホール３を設け
る。そして、このコンタクトホール３上に反応障壁層例
えば窒化チタン層８を形成し、その表面に低抵抗の配線
層である高融点金属層７を設けている。ここで、窒化チ
タン層８は、配線層形成工程後の熱処理により、高融点
金属層７とシリコン基板１とが直接反応して劣化するこ
とを抑制する反応障壁層として作用する。従って、この
２層構造にすることにより、後工程で多くの熱処理を必
要とする三次元回路素子に使用する耐熱性配線として利
用することができる。なお、窒化チタン層８と高融点金
属層７は選択的にエツチングされ配線となる。2. Description of the Related Art Conventionally, a semiconductor device having a high melting point metal wiring as shown in a cross-sectional view in FIG. 2 has been proposed. In this method, an insulating layer 2 is provided on a semiconductor substrate, for example, a silicon substrate 1, by thermal oxidation or chemical vapor deposition (hereinafter referred to as CVO), and a contact hole 3 is provided by photolithography and etching. A reaction barrier layer, such as a titanium nitride layer 8, is formed on the contact hole 3, and a high melting point metal layer 7, which is a low resistance wiring layer, is provided on the surface thereof. Here, the titanium nitride layer 8 acts as a reaction barrier layer that prevents the high melting point metal layer 7 and the silicon substrate 1 from directly reacting and deteriorating due to heat treatment after the wiring layer forming step. Therefore, by forming this two-layer structure, it can be used as a heat-resistant wiring used in three-dimensional circuit elements that require a lot of heat treatment in subsequent steps. Note that the titanium nitride layer 8 and the high melting point metal layer 7 are selectively etched to form wiring.
従来の半導体装置は以上の様に構成されているので、窒
化チタン層８に含有する酸素が熱処理によってシリコン
基板１と反応し、コンタクトホール３におけるシリコン
基板１表面にシリコン酸化膜を形成することになり、配
線となる高融点金属層７及び窒化チタン層８とシリコン
基板１との良好な電気的接続が得られないという欠点が
あった。Since the conventional semiconductor device is configured as described above, the oxygen contained in the titanium nitride layer 8 reacts with the silicon substrate 1 through heat treatment, and a silicon oxide film is formed on the surface of the silicon substrate 1 in the contact hole 3. Therefore, there was a drawback that a good electrical connection between the silicon substrate 1 and the high melting point metal layer 7 and the titanium nitride layer 8, which serve as wiring, could not be obtained.
本発明は、上記のような欠点を解消するためになされた
もので、シリコン基板１上にシリコン酸化膜を形成しな
い良好な電気的接続（以下コンタクトという）を有する
半導体装置を得ることを目的とする。The present invention was made in order to eliminate the above-mentioned drawbacks, and an object of the present invention is to obtain a semiconductor device having good electrical connections (hereinafter referred to as contacts) without forming a silicon oxide film on a silicon substrate 1. do.
上記の欠点を解決するため本発明は、半導体基板の表面
に形成された絶縁膜と、この絶縁膜に設けられた前記半
導体基板が露出する開口部と、この開口部の表面に形成
された第１の反応障壁層と、この第１の反応障壁層の表
面ば形成されたチタン層と、このチタン層の表面に形成
された第２の反応障壁層と、この第２の反応障壁層の表
面に形成された高融点金属層とを備えている。In order to solve the above-mentioned drawbacks, the present invention provides an insulating film formed on the surface of a semiconductor substrate, an opening provided in this insulating film through which the semiconductor substrate is exposed, and an opening formed on the surface of this opening. a first reaction barrier layer, a titanium layer formed on the surface of this first reaction barrier layer, a second reaction barrier layer formed on the surface of this titanium layer, and a surface of this second reaction barrier layer. and a high melting point metal layer formed on.
反応障壁層と還元性の強いチタン層を設けているため、
熱処理を行なった場合、反応障壁層に含有する酸素はこ
のチタン層内に取り込まれ、半導体基板上のコンタクト
を劣化させない。Because it has a reaction barrier layer and a highly reducing titanium layer,
When heat treatment is performed, the oxygen contained in the reaction barrier layer is incorporated into this titanium layer and does not deteriorate the contacts on the semiconductor substrate.
以下、本発明の実施例を図について説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明に係る一実施例を示す半導体装置の断面
図である。図において、第２図と同一部分または相当部
分には同一符号を付しその説明を省略する。この実施例
ではコンタクトホール３上にまず第１の反応障壁層であ
る窒化チタン層４を形成し、その表面にチタン層５を形
成しである。そして、このチタン層５の表面に第２の反
応障壁である窒化チタン層６を形成しである。すなわち
、窒化チタン層４及び６の間にチタン層５がサンドイッ
チ状に挾まれた構造となっている。また、窒化チタン層
６０表面には低抵抗の配線となる高融点金属層７が形成
しである。FIG. 1 is a sectional view of a semiconductor device showing one embodiment of the present invention. In the figure, the same or corresponding parts as in FIG. 2 are given the same reference numerals, and the explanation thereof will be omitted. In this embodiment, a titanium nitride layer 4, which is a first reaction barrier layer, is first formed on the contact hole 3, and a titanium layer 5 is formed on the surface thereof. Then, a titanium nitride layer 6 as a second reaction barrier is formed on the surface of this titanium layer 5. That is, the structure is such that the titanium layer 5 is sandwiched between the titanium nitride layers 4 and 6. Furthermore, a high melting point metal layer 7 serving as a low resistance wiring is formed on the surface of the titanium nitride layer 60.
ここで、窒化チタン層４及び６に挾まれたチタン層５は
、還元性を有するため熱処理を行なうと窒化チタン層内
の酸素を取り込み、コンタクトを劣化させるコンタクト
ホール３におけるシリコン基板１上のシリコン酸化膜の
生成を抑制する。従って、シリコン基板１と高融点金属
層７とは常に良好なコンタクトを得ることができる。Here, since the titanium layer 5 sandwiched between the titanium nitride layers 4 and 6 has a reducing property, when heat treatment is performed, oxygen in the titanium nitride layer is taken in, and the silicon substrate 1 in the contact hole 3 deteriorates the contact. Suppresses the formation of oxide film. Therefore, good contact can always be obtained between the silicon substrate 1 and the high melting point metal layer 7.
なお、上記の実施例において反応障壁に窒化チタン層を
用いたが、高温の熱処理に対して劣化せず、各層間の反
応を抑制し原子の移動を防ぐ物質であれば窒化チタン層
以外の物質を用いてもよい。In the above example, a titanium nitride layer was used as a reaction barrier, but any material other than the titanium nitride layer may be used as long as it does not deteriorate under high-temperature heat treatment, suppresses reactions between layers, and prevents the movement of atoms. may also be used.
また、この半導体装置を後工程で多くの熱処理を必要と
する三次元回路素子の製造工程に用いる事により、良好
なコンタクト特性を実施することが可能となる。さらに
、高融点金属層としてタングステン、モリブデン、タン
タルまたはその珪化物、あるいはそれらの混合膜ないし
複合膜を用いてもよい。In addition, by using this semiconductor device in the manufacturing process of three-dimensional circuit elements that requires a lot of heat treatment in post-processes, it becomes possible to achieve good contact characteristics. Furthermore, tungsten, molybdenum, tantalum, a silicide thereof, or a mixed film or a composite film thereof may be used as the high melting point metal layer.
以上説明したように本発明は、第１及び第２の反応障壁
層の間にチタン層を挾むような構造となっているため、
熱処理によってこの反応障壁層に含有している酸素をチ
タン層内に取り込み、半導体基板上に酸化膜を形成しな
い良好な電気導通特性を有する半導体装置を提供するこ
とができる。As explained above, the present invention has a structure in which a titanium layer is sandwiched between the first and second reaction barrier layers.
Oxygen contained in the reaction barrier layer is incorporated into the titanium layer by heat treatment, making it possible to provide a semiconductor device having good electrical conductivity without forming an oxide film on the semiconductor substrate.
第１図は本発明に係る一実施例を示す半導体装置の断面
図、第２図は従来の半導体装置を示す断面図である。
１・・・・シリコン基板、２・・・・絶縁膜、３・・・
・コンタクトホール、４，６・・・・・窒化チタン層、
５・−・魯チタン層、７・拳・・高融点金属層。FIG. 1 is a sectional view of a semiconductor device showing one embodiment of the present invention, and FIG. 2 is a sectional view of a conventional semiconductor device. 1... Silicon substrate, 2... Insulating film, 3...
・Contact hole, 4, 6...Titanium nitride layer,
5.--Lu titanium layer, 7. Fist--high melting point metal layer.
Claims (1)
部と、 この開口部の表面に形成された第１の反応障壁層と、 この第１の反応障壁層の表面に形成されたチタン層と、 このチタン層の表面に形成された第２の反応障壁層と、 この第２の反応障壁層の表面に形成された高融点金属層
とを備えたことを特徴とする半導体装置。[Scope of Claims] An insulating film formed on a surface of a semiconductor substrate, an opening provided in this insulating film through which the semiconductor substrate is exposed, and a first reaction barrier layer formed on the surface of this opening. , a titanium layer formed on the surface of this first reaction barrier layer, a second reaction barrier layer formed on the surface of this titanium layer, and a titanium layer formed on the surface of this second reaction barrier layer. A semiconductor device comprising: a melting point metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12235788A JPH01291450A (en) | 1988-05-18 | 1988-05-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12235788A JPH01291450A (en) | 1988-05-18 | 1988-05-18 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01291450A true JPH01291450A (en) | 1989-11-24 |
Family
ID=14833900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12235788A Pending JPH01291450A (en) | 1988-05-18 | 1988-05-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01291450A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5550427A (en) * | 1991-11-19 | 1996-08-27 | Nec Corporation | Substrate contact electrode having refractory metal bump structure with reinforcement sidewall film |
| US5858868A (en) * | 1992-05-08 | 1999-01-12 | Yamaha Corporation | Method of manufacturing a laminated wiring structure preventing impurity diffusion therein from N+ and P+ regions in CMOS device with ohmic contact |
-
1988
- 1988-05-18 JP JP12235788A patent/JPH01291450A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5550427A (en) * | 1991-11-19 | 1996-08-27 | Nec Corporation | Substrate contact electrode having refractory metal bump structure with reinforcement sidewall film |
| US5858868A (en) * | 1992-05-08 | 1999-01-12 | Yamaha Corporation | Method of manufacturing a laminated wiring structure preventing impurity diffusion therein from N+ and P+ regions in CMOS device with ohmic contact |
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