JPS61269359A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase electrostatic breakdown withstand voltage between a gate electrode and source-drain by forming a region in low concentration just under an insulating film, at the center thereof the gate electrode is shaped, and to both side sections of the gate electrode and forming source-drain regions adjacent to the region. CONSTITUTION:A gate electrode 81 for a parasitic MOS element as a clamping element is shaped at approximately the central section of a comparatively thick field insulating film 42, and first semiconductor regions 52, 53 in low concentration are formed where corresponding to both side sections of the gate electrode just under the field insulating film before shaping the field insulating film. Second semiconductor regions 91, 92 as a source and a drain are formed adjacent to the first semiconductor regions 52, 53 in the side sections of the field insulating film. Since the gate electrode 81 is offset and shaped from the second semiconductor regions 91, 92, dielectric breakdown withstand voltage between both regions 91, 92 is increased, and gate electrode itself can also be utilized as an input protective resistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and more particularly to a parasitic MO8 element used as a clamp element in a lightning protection circuit.

[Background technology]

Various electrostatic breakdown protection circuits for semiconductor devices have been proposed in which a protective resistor such as a polysilicon resistor or a diffused layer resistor is combined with a clamp element such as an MO8 element in the form of a diode or a parasitic MO8 element. Generally, for polysilicon resistors, measures against field insulating film breakdown and thermal breakdown have been considered, and for diffused resistors, measures against latch-up and PN junction breakdown have been considered. On the other hand, instead of diodes and MO8 elements, parasitic MO8 elements are used to improve electrostatic breakdown voltage. This parasitic MO8 element includes a polysilicon parasitic MO8 element and A! Parasitic MO8 elements are known, and various measures have been taken for these as well from the viewpoint of improving electrostatic breakdown voltage. For example, the applicant's Japanese Patent Application Laid-Open No. 2003-110005 describes that the gate electrode of a parasitic MO8 element overlaps with the source and drain diffusion layers of the parasitic MO8 element, and that the insulating film between them is destroyed, and also describes how to solve the problem. The measures are disclosed.

By the way, L CD (Liquid Crysta)
Elements having a so-called high breakdown voltage MO8 element structure are known for directly driving devices such as 1Device). This high voltage MO8 element forms a low concentration semiconductor region under the field insulating film, which increases the PN junction reverse breakdown voltage and the channel breakdown voltage (BVD) of the MO8 element.
8)' so that a higher voltage can be applied to the drain and gate. The present inventors have discovered that the electrostatic breakdown voltage of a parasitic MOS element can be improved by utilizing this process for forming a low concentration semiconductor region.

[Purpose of the invention]

The purpose of the present invention is to reduce parasitic MO8 used in an electrostatic discharge protection circuit.
The present invention provides a semiconductor device in which the electrostatic breakdown voltage of the element is improved.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the gate electrode of the parasitic MO8 element as a clamp element is formed approximately at the center of a relatively thick field insulating film, and before the field insulating film is formed, a low-temperature electrode is formed at a position corresponding to both sides of the gate electrode directly under the field insulating film. forming a high concentration first semiconductor region; Thereafter, a second semiconductor region serving as a source and a drain is formed adjacent to the first semiconductor region on the side of the field insulating film.

Since the gate electrode is formed offset from the second semiconductor region, the dielectric breakdown voltage between the two is improved, and therefore the gate electrode itself can be used as an input protection resistor.

〔Example〕

FIG. 1 is a vertical cross-sectional structural view in which a P-channel MO8 element with a high breakdown voltage MO8 element structure and a parasitic MO8 element of the present invention are all formed on the same semiconductor substrate. In the figure, reference numeral 1 indicates a Nu silicon semiconductor substrate. A high breakdown voltage P-channel MO8 element 2 is formed on the right side of the figure, and a polysilicon gate parasitic MO8 element 3 is formed on the left side.

First, the structure of the high voltage P-channel MO8 element 2 will be explained. Code 4 is thick S10. Before forming the field insulating film 4, a lightly doped P-type semiconductor region 5 and an N-type semiconductor region 6 as a channel stopper are formed by ion implantation. A polysilicon gate electrode 8 is formed with a stow gate insulating film 7 interposed between the field insulating films 4.4 in which the P- producing conductor region 5 is formed over the entire lower part. Also, P
P type semiconductor regions 9 forming the source and drain of the channel MO8 element 2 are formed in contact with the P- type semiconductor regions 5 by ion implantation. In addition, code 1
0 (4 source and drain aluminum contact electrodes, numeral 11 is a glabella insulating film such as PSG, and numeral 1 is
2 is a badge page attack film. In the P-channel MO8 element 2 having such a configuration, the P-type semiconductor region 5 increases the PN junction reverse breakdown voltage between the substrate and the source and drain, and at the same time increases the P-type semiconductor region on both sides of the channel under the gate electrode 8. Increase the υMOS channel breakdown voltage. Therefore, a high voltage can be applied to the drain and gate, and it is used, for example, to drive an LCD or the like at a high voltage.

In the manufacturing process of such a high voltage MO8 element 2, P-
Although the step of forming a type semiconductor region tube is included, in the embodiment of the present invention, the P- type semiconductor region is utilized to improve the electrostatic breakdown voltage of the parasitic MO8 element. That is, the parasitic MO8 element 3Fi shown on the left side of the figure is formed as follows.

First, in order to form the parasitic MO8 element 3, 810° field insulating films 41, 42 and 43 are required.
Before forming the P-ffl semiconductor region 5, boron is implanted to form a low concentration P-ffl semiconductor region 5.
type semiconductor regions (first semiconductor regions) 51, 52, 53,
54 is formed directly under the field insulating films 41, 42, and 43. After this, a known oxide layer and a film (oxidation resistant film) that will serve as a mask during oxidation are formed on the entire surface, and the field insulating film 41 is selectively etched and thermally oxidized.
, 42.43. At this time, the P-type semiconductor region 51
, 52, 53, and 54 are diffused to a required depth.

Next, after depositing polysilicon on the entire surface, a gate electrode 81fi is formed by etching. This gate electrode 81 is formed approximately at the center of the field insulating film 42, and above the channel portion between the P-type semiconductor regions 52 and 53. Furthermore, P+ type semiconductor regions (second semiconductor regions) 91 and 92 which will become the source and drain of the damn MO8 element 30 are formed by ion implantation. This P
Each of the + type semiconductor regions 91 and 92 is a P− type semiconductor region 51.
Adjacent to 52, 53 and 54. Finally, high voltage M
In the same manner as described for O8 element 2, aluminum contact electrodes 101. Phosphosilicate glass (
The parasitic MO8 element 3 is completed by forming a glabella insulating film 111 and a badge page 1 film 121 made of PSG) or the like.

It can be seen that since the gate electrode 81 is formed almost in the center of the gold field insulating film 42 and separated from the source and drain P+ type semiconductor regions 91 and 92, the electrostatic breakdown voltage between them is improved.

Although the parasitic MO8 element 3 of this embodiment is a polysilicon gate, it is clear that this polysilicon layer can be used to selectively form the protective resistor of the electrostatic breakdown protection circuit. In addition, in the embodiment, the P-type semiconductor region 51,
52 and 53.54 were formed to surround P+ type semiconductor regions 91 and 92, respectively. However, P-
It is clear that the object of the present invention can be achieved even if the type semiconductor region exists only at least on the gate electrode side of the P+ type semiconductor region.

〔effect〕

A gate electrode is formed approximately at the center of a thick insulating film, a low concentration semiconductor region is formed directly under this insulating film and on both sides of the gate electrode, and a source and a drain are formed adjacent to this low concentration semiconductor region. This forms a semiconductor region. Therefore, the electrostatic breakdown voltage between the gate electrode and the source and drain is improved.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the embodiment, a parasitic MO8 element with a polysilicon gate has been described, but it is clear that the present invention can also be applied to a parasitic MO8 element with an aluminum gate. Also, the same embodiment tN-channel MO8F on the P-type semiconductor substrate or in the P-WELL region
It is also easy to implement with ET.

[Application field]

It can be applied as a clamp element in an electrostatic breakdown protection circuit, and is particularly suitable for application to CMO8-LSIs, LCD drivers, 4-bit microcomputers, etc. using high-voltage processes.

[Brief explanation of drawings]

FIG. 1 is a vertical cross-sectional structural view in which a P-channel MO8 element with a high breakdown voltage MO8 element structure and a parasitic MO8 element with a polysilicon gate, which is an embodiment of the present invention, are formed on the same semiconductor substrate. 1... Semiconductor substrate, 2... High voltage P-channel MO8
Element, 3... Parasitic MO8 element of polysilicon gate,
4.41,42,43...Field insulating film, 5...
・P-type semiconductor region, 51, 52, 53.54...P
- type semiconductor region (first semiconductor region), 6... Channel stopper, 7... Gate insulating film, 8, 81... Gate electrode, 9... P type semiconductor region, 91.92...
・P+ type semiconductor region (second semiconductor region), 10, 10
1... Aluminum electrode, 11,111... Interlayer insulating film, 12.121... Passivation film. Agent: Patent Attorney Masaru Ogawa -1, (,,

Claims (1)

[Claims] 1. A gate electrode formed approximately at the center of a relatively thick insulating film, a first semiconductor region formed directly below the insulating film and on both sides of the gate electrode, and the insulating film and a second semiconductor region formed adjacent to the first semiconductor region on both sides thereof and having a concentration higher than that of the first semiconductor region.