JPH08330581A - Semiconductor device - Google Patents

Abstract

PURPOSE: To increase the breakdown voltage and the never or integration of a complementary transistor, by dividing a second conductivity type semicon ductor substrate into a plurality of regions by using a second insulating film, forming high power elements in a first region where a first insulating film is not arranged, and forming logic elements in a second region where the first insulating film is arranged. CONSTITUTION: Lightly doped N-type Si semiconductor substrates 2a-2c are laminated on a P-type Si semiconductor substrate 1. A buried oxide film 3 is arranged in the position corresponding to the bottom part of the substrate 2a where logic elements are to be formed. In the oxide film 3, oxide film insulators 5a, 5b are formed to divide the region in the vertical direction. High breakdown voltage elements are formed in a direct junction region 100 where the oxide film is not present in the boundary between the divided P-type Si semiconductor substrate l and the N-type Si semiconductor substrates 2a-2c. Logic control elements are formed in an SOI region 200 where the oxide film 3 is present. Oxide films 4c, 4d are formed in a plurality of trenches, and oxide insulators 5c, 5d are formed in the oxide films.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to SOI (Silicon On In
The present invention relates to a semiconductor device that constitutes a high breakdown voltage element having a (sulator) structure, and particularly to a flat panel display, especially a display driver IC having a plurality of output stages at high voltage used for an electroluminescence (EL; Electro Luminescence) display, a plasma display and the like. The present invention relates to a semiconductor device that constitutes a high breakdown voltage element or a vehicle-mounted motor drive IC.

[0002]

2. Description of the Related Art Conventionally, as a technique for improving the breakdown voltage of a field effect transistor, for example, as shown in FIG. 2, a thick LOCOS (L
In some cases, an OCal Oxidation of Silicon (Oxidation of Silicon) oxide film 30 is formed to relax the electric field between the gate and the drain.

As this kind of electric field relaxation, for example, Japanese Patent Laid-Open No.
In Japanese Patent Laid-Open No. 103851, there is disclosed a technique related to a "high breakdown voltage semiconductor element" characterized in that an electric field relaxation layer having a low concentration (however, a concentration higher than that of an upper SOI layer) is provided in a lower layer of an SOI substrate. It is disclosed. Below, FIG.
The technique will be described with reference to.

In this technique, a p-type layer 58 serving as a channel region is formed in the central portion of the silicon layer 54, and the p-type layer 5 is formed.
N ⁺ -type layer 59a serving as a source region in the 8, b is formed, n ⁺ -type layer 59a of the p-type layer 58, b and the silicon layer 54
The gate electrode 57 is formed between the gate insulating film 56. The p ⁻ -type layers 60a and 60b are formed on the surface of the silicon layer 54 under the gate electrode 57 at a slight distance from the p-type layer 58, and the n ⁺ -type layers 61a and 61b to be drain regions are formed around the silicon layer 54. , 62a, 62b are formed. The n ⁺ -type layers 61a and b have the first electrodes 63a and 63b, which are drain electrodes, the p-type layer 58 and the n ⁺ -type layer 5, respectively.
A second electrode 64 serving as a source electrode is formed on 9a and 9b. An n ⁻ type layer 55 is formed in a region in contact with the oxide film 52 at the bottom of the high resistance silicon layer 54.

In such a structure, the first electrode 63
A drain voltage that is positive with respect to the second electrode 64 is applied to a and b to operate. In the off state where the gate voltage is zero or positive and no channel is formed in the p-type layer 58, the depletion layer extending from the p-type layer 58 easily reaches the p ⁻ -type layers 60a and 60b. Since the drain-source voltage is shared in the vertical direction and the horizontal direction by the depleted silicon layers 54, 60a, b and the n ⁻ type layer 55, high breakdown voltage characteristics can be obtained. That is,
In this technology, part of the reverse high voltage applied to the device is shared by the electric field relaxation layer, so that part of the voltage applied to the device is effectively shared by the buried oxide film, and high voltage is achieved. To be done.

[0006]

However, in the above-mentioned conventional technique, the high voltage is supported by the low-concentration electric field relaxation layer and the buried oxide film used in the lower portion of the SOI semiconductor substrate. When an IC for driving an EL display is to be constructed, heat is generated in the SOI region when a large current is output by the high breakdown voltage element. The buried oxide film in the SOI region has a thermal conductivity of Si.
Since it is 1/100 that of semiconductors, the heat generated is SO
It is easy to stay in the I region and the temperature of the IC rises. In order to prevent this temperature rise, a method of enlarging the high breakdown voltage element to reduce the electrical resistance of the high breakdown voltage element and reducing the heat generation determined by the product of the square of the current and the electrical resistance value may be considered.
In this method, the area of the IC is increased and the yield is increased, which is inconvenient in cost.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a high withstand voltage, which is excellent in high withstand voltage of complementary transistors and the like, measures against heat generation, noise interference and the like.
It is to realize a semiconductor device which can be highly integrated.

[0008]

In order to achieve the above object, a semiconductor device of the present invention comprises a first conductive type semiconductor substrate and an impurity concentration laminated on the first conductive type semiconductor substrate. Of 1 × 10 ¹⁴ cm ⁻³ or less, and a first conductive film which is partially disposed at a predetermined position on the laminated surface of the first and second conductive semiconductor substrates. An insulating film and a second insulating film provided in a predetermined groove provided in the second conductive type semiconductor substrate are provided, and the second conductive type semiconductor substrate is provided with the second insulating film. A high power element is formed in a first region of the second conductive semiconductor substrate in which the first insulating film is not provided,
The logic element is formed in the second region of the second conductive type semiconductor substrate on which the insulating film is provided.

[0009]

That is, a second conductive type semiconductor substrate having an impurity concentration of 1 × 10 ¹⁴ cm ⁻³ or less is laminated on the first conductive type semiconductor substrate, and the first insulating film is the first conductive film. And a second insulating film partially disposed at a predetermined position on the laminated surface of the second conductive type semiconductor substrate, and a second insulating film disposed in a predetermined groove provided on the second conductive type semiconductor substrate. The second conductive semiconductor substrate is divided into a plurality of regions by the second insulating film, and the first conductive film semiconductor substrate is not provided with the first insulating film. A high power element is formed on the second conductive semiconductor substrate, and a logic element is formed on the second region of the second conductive semiconductor substrate on which the first insulating film is provided. in this way,
Heat dissipation is improved by not disposing the first insulating film in the first region, and a low-concentration layer of the second conductive semiconductor substrate having an impurity concentration of 1 × 10 ¹⁴ cm ⁻³ or less is formed. An electric field is relaxed by incorporating a high breakdown voltage element. Furthermore, since the first region is divided into a plurality of parts by the second insulating film, a plurality of different high power elements can be installed side by side.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described below with reference to FIG. As shown in the figure,
On a P-type silicon (Si) semiconductor substrate 1, low-concentration N-type Si semiconductor substrates (hereinafter referred to as i-substrates) 2a to 2c having an impurity (donor) concentration of 1 × 10 ¹⁴ cm ⁻³ or less are approximately 10 μm thick. Are stacked in. A thickness of about 2 μm is formed in the region where the logic element is to be formed and at the position corresponding to the bottom of the i-substrate 2a.
A buried oxide film (SiO ₂ ) 3 of m is provided. Similarly, oxide films 4a and 4b having a thickness of 0.5 μm are separated in a direction perpendicular to the stacking direction of the elements on the groove and the side surface of the groove reaching the buried oxide film 3 from the surface of the i-substrate 2a. Form for the purpose.

In the oxide film 3, an oxide film insulator 5 is further provided.
a and 5b are provided to separate in the vertical direction. The P-type Si semiconductor substrate 1 and the i-substrate 2a thus separated
~ 2c direct bonding region 100 without the oxide film 3 at the boundary
A high breakdown voltage element is provided in the SOI region 20 where the oxide film 3 is present.
0 has a structure in which a logic control element is provided. Further, in the direct bonding region 100, a groove is provided to dispose a plurality of high breakdown voltage elements, and oxide films 4c and 4d are further provided in the groove, and an oxide film insulator 5c, 5d is provided.

Since the direct junction region 100 is divided into a plurality of parts as described above, an N channel type
It is possible to provide a field effect transistor (FET) of P-channel type or both types. In order to increase the breakdown voltage and the degree of integration of the device, it is necessary to relax the electric field between the source and drain of the field effect transistor provided in the direct junction region 100 without locally concentrating it. Board 2
By using b and 2c, the depletion layer can be easily expanded and the electric field can be relaxed. Furthermore, in order to make both the N channel and the P channel compatible with each other in the high breakdown voltage transistor, a substrate having a lower concentration than that of each drift region is required, but this is also possible by using the i substrate.

The actual manufacturing process of this semiconductor device will be described below. First, the P-type Si semiconductor substrate 1 and i
The substrates 2 are bonded together using a direct bonding technique. That is, the two substrates 1 and 2 are mirror-polished in advance, the polished surfaces are brought into close contact with each other in a clean atmosphere, and a predetermined heat treatment is applied to integrate them. At this time, the oxide film 3 is formed in a predetermined region of the i substrate 2. Next, the element isolation trenches are formed by photoetching, and the i-shaped substrates 2a to 2 are separated into islands.
An N-type Si semiconductor substrate 6, a P-type Si semiconductor substrate 7, and an N-type Si semiconductor substrate 8 are formed on the upper surface of c.

On the i-substrate 2a, a P-well region 9 is formed after a pattern to be a P-well region is formed by photoresist. Then, a P + type layer 10 and N + type layers 11 and 12 are diffused and formed on the P well layer 9 to form electrodes S1 and D
1 is formed to form an N-channel type transistor. Similarly, on the N-type Si semiconductor substrate 6, the P + type layers 13 and 14,
N + type layer 15 is formed by diffusion, electrodes S2 and D2 are formed,
A P-channel transistor is formed. Thus SOI
A logic control element is formed in the region 200.

On the other hand, on the i-substrate 2b, a pattern to be an N well region is formed by a photoresist, and then N
A well layer 16 is formed, and a P + type layer 17 and an N + type layer 18 serving as a source region are diffused and formed in the N well layer 16,
Type Si semiconductor substrate 7 on which a P + type layer 1 serving as a drain region is formed
9 is diffused to form electrodes S3, G3 and D3, respectively. In this way, a P-channel type transistor is formed on the i substrate 2b.

On the i-substrate 2c, a pattern to be a P-well region is formed by photoresist, and then a P-well layer 20 is formed. In the P-well layer 20, a P + -type layer 21, N serving as a source region is formed. The + type layer 22 is diffused to form N type Si.
An N + type layer 23 which will be a drain region is diffused and formed on the semiconductor substrate to form electrodes S4, G4 and D4. Thus
An N channel type transistor is formed on the i substrate 2c.

When the i substrate 2 is used for the SOI structure as described above, the heat generated in the high breakdown voltage element region is trapped due to the existence of the oxide film having a low thermal conductivity, and the temperature rises easily. By forming a high breakdown voltage element in the direct bonding region 100, heat dissipation can be improved. still,
The i-substrate 2 has a low electrical conductivity, but has a normal thermal conductivity of S.
It is on the order of the i substrate and is sufficiently higher than the oxide film.

As described above, in order to achieve high breakdown voltage and high integration of the semiconductor element, it is necessary to relax the electric field between the source and drain of the high breakdown voltage element without concentrating it locally. Then, by using the low-concentration semiconductor layer, the depletion layer between the source and the drain can be easily expanded, and the electric field can be relaxed.

Further, the low-concentration semiconductor layer (i substrate)
Has a low electrical conductivity, but the thermal conductivity in which lattice vibration is dominant is nearly 100 times that of an oxide film, so that it is possible to easily release the heat generated by the high breakdown voltage element. That is, the i-substrate plays an effective role in both electric field relaxation and heat dissipation.

In order to make both the N channel and the P channel compatible with each other as the high breakdown voltage field effect device, both the P type diffusion layer having a low concentration and the N type diffusion layer are required, but the concentration of the above low concentration is required. By using the semiconductor layer, it becomes easy to form both high breakdown voltage N-channel type and P-channel type FETs.

The semiconductor device of the present invention is not limited to the above-described embodiments, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the invention. For example, in the above-described embodiment, the N-type Si semiconductor substrate (i substrate) having the impurity concentration of 1 × 10 ¹⁴ cm ⁻³ or less is laminated on the P-type Si semiconductor substrate. A structure in which a P-type Si semiconductor substrate having an impurity concentration of 1 × 10 ¹⁴ cm ⁻³ or less is laminated thereon may be used.

[0022]

According to the present invention, it is possible to provide a semiconductor device which is excellent in heat dissipation and which can have high breakdown voltage and high integration.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a semiconductor device according to a conventional technique.

FIG. 3 is a diagram showing a configuration of a semiconductor device according to a conventional technique.

[Explanation of symbols]

 1, 7 ... P-type Si semiconductor substrate 2, 2a, 2b, 2c, 6, 8 ... N-type Si semiconductor substrate 3, 4a, 4b, 4c, 4d ... Oxide film 5a, 5b, 5c, 5d ... Oxide film insulator 9, 20 ... P well layer 16 ... N well layer 10, 13, 14, 17, 19, 21, ... P + layer 11, 12, 15, 18, 22, 23 ... N + layer 100 ... Direct junction region, 200 ... SOI area

Front page continuation (72) Inventor Toshiyuki Morishita 1-1, Showa-cho, Kariya city, Aichi Nihon Denso Co., Ltd.

Claims (1)

[Claims] 1. A first conductive semiconductor substrate and an impurity concentration of 1 × 10 stacked on the first conductive semiconductor substrate.
^A second conductive semiconductor substrate having a size of ¹⁴ cm ⁻³ or less, and a first insulating film partially disposed at a predetermined position on the laminated surface of the first and second conductive semiconductor substrates, A second insulating film provided in a predetermined groove provided in the second conductive type semiconductor substrate, wherein the second conductive type semiconductor substrate is divided into a plurality of regions by the second insulating film. A high power element is formed in the first region of the second conductive semiconductor substrate on which the first insulating film is not provided, and the first insulating film is provided. A semiconductor device, wherein a logic element is formed in a second region of the second conductive semiconductor substrate.