JP2012156520A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve flatness of a surface of a semiconductor substrate without causing the increase of a chip area due to the disposition of a dummy active region.SOLUTION: A gate insulator 7 of a high breakdown voltage MISFET having a thick film thickness is formed at an upper part of an n-type buried layer 3 serving as a dummy active region, and a resistance element IR of an internal circuit is formed at an upper part of the gate insulator 7. Disposing the thick gate insulator 7 between the n-type buried layer 3 and the resistance element IR reduces coupling capacitance formed between a substrate 1 (the n-type buried layer 3) and the resistance element IR.

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a semiconductor device in which a high breakdown voltage MISFET and a resistance element are formed on the same semiconductor substrate and a technique effective when applied to the manufacturing technique thereof.

  As an element isolation structure for electrically isolating adjacent semiconductor elements, an element isolation groove (STI: Shallow Trench Isolation) in which a groove is formed in an element isolation region of a semiconductor substrate and an insulating film is embedded therein is known. . In order to form the element isolation trench, the semiconductor substrate is first etched to form a trench, and then a silicon oxide film thicker than the depth of the trench is deposited on the semiconductor substrate. Next, when the silicon oxide film outside the groove is removed by a chemical mechanical polishing method, the silicon oxide film remains inside the groove and the surface thereof is flattened.

  By the way, since the dimensions of the semiconductor elements are optimized according to the application and function thereof, a plurality of types of semiconductor elements having different dimensions are mixed on an actual semiconductor substrate. For example, a MISFET that operates at a high power supply voltage (hereinafter referred to as a high voltage MISFET) has a larger size and a larger film thickness of a gate insulating film than a MISFET that operates at a low power voltage (hereinafter referred to as a low voltage MISFET). . Also, passive elements such as resistance elements and capacitive elements are generally larger in size than low breakdown voltage MISFETs. Furthermore, since the integrated circuit has different degrees of integration of semiconductor elements depending on its application and function, there are areas where semiconductor elements are densely arranged and areas where sparsely arranged semiconductor elements exist on an actual semiconductor substrate. .

  On the other hand, the dimension of the element isolation groove for separating the semiconductor elements is defined by the dimensions and density of the semiconductor elements. Therefore, in an actual semiconductor substrate, element isolation trenches having different dimensions are mixed, and there are a region where the element isolation trenches are densely arranged and a region where the element isolation trenches are sparsely arranged.

  However, in the step of forming element isolation grooves, after forming a plurality of grooves having different dimensions on a semiconductor substrate, a silicon oxide film is deposited and the surface is polished by a chemical mechanical polishing method. A phenomenon (called dishing) occurs in which the surface of the buried silicon oxide film is recessed and polished like a dish.

  When the above-mentioned dent is generated in the silicon oxide film in the element isolation trench, the flatness of the surface of the thin film is lowered above the element isolation trench when a thin film is deposited on the semiconductor substrate in a later process. . Therefore, when a photoresist film is next formed on the thin film and exposure processing is performed, the focus range of the exposure light is lowered above the element isolation groove, and the accuracy of the resist pattern is lowered.

  As a countermeasure, a large number of dummy active regions with small dimensions are laid in a matrix in a large-area element isolation region where dishing occurs significantly, and the effective area of the element isolation trenches in this region is reduced. A technique for suppressing dishing of a silicon oxide film has been proposed and applied to an actual semiconductor product.

  For example, Japanese Patent Laid-Open No. 2002-158278 (Patent Document 1) is known as a conventional technique for disposing a dummy active region in a large-area element isolation region. This Patent Document 1 improves the flatness of the surface of a silicon oxide film by disposing two types of dummy active regions having different dimensions in the element isolation region, and creates a dummy active region forming photomask. Discloses a technique for reducing the amount of data.

  Japanese Patent Laid-Open No. 2002-261244 (Patent Document 2) discloses that when a resistance element made of a polycrystalline silicon film is formed on an upper part of an element isolation groove, the center part of the element isolation groove is caused by dishing of the silicon oxide film. It points out the problem that the width, film thickness, and cross-sectional shape of the resistance element differ between the peripheral portions. In addition, in order to solve this problem, a technique is disclosed in which a dummy active region is disposed in the vicinity of a region where a resistance element is formed and the silicon oxide film is divided into a necessary range to suppress the occurrence of dishing. Yes.

JP 2002-158278 A JP 2002-261244 A

  According to the study of the present inventor, in the conventional technique in which the dummy active region is disposed in the element isolation region and the resistance element is formed thereon, a coupling capacitance is formed between the dummy active region and the resistance element. This causes a new problem that the characteristics of the resistance element fluctuate.

  In addition, the technique of improving the flatness of the chip surface by providing a dummy active region in a part of the semiconductor chip is not effective unless the proportion of the dummy active region in the semiconductor chip is increased to some extent. There is a problem of causing an increase in area.

  An object of the present invention is to provide a technique for improving the flatness of the surface of a semiconductor substrate without causing an increase in chip area accompanying an increase in dummy active regions.

  Another object of the present invention is to provide a technique for improving the reliability of a resistance element.

  Another object of the present invention is to provide a technique for improving ESD resistance of a resistance element for an electrostatic protection circuit.

  Another object of the present invention is to provide a technique for simplifying the manufacturing process of a semiconductor device in which a high voltage MISFET and a resistance element are formed on the same semiconductor substrate.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to the present invention includes a first MISFET having a first gate insulating film formed in a first region of a main surface of a semiconductor substrate and operating at a first power supply voltage, and a second gate of the main surface of the semiconductor substrate. A second MISFET formed in a region and having a second gate insulating film having a thickness larger than that of the first gate insulating film and operating at a second power supply voltage higher than the first power supply voltage; and the semiconductor substrate A resistive element made of a silicon film formed in a third region of the main surface of the semiconductor substrate, and an insulating film of the same layer as the second gate insulating film is formed in the third region of the main surface of the semiconductor substrate. The resistance element is formed on the insulating film.

  The semiconductor device of the present invention includes a first MISFET having a first gate insulating film formed in a first region of a main surface of a semiconductor substrate and operating at a first power supply voltage, and a second region of the main surface of the semiconductor substrate. A second MISFET having a thickness greater than that of the first gate insulating film and operating at a second power supply voltage higher than the first power supply voltage, and the semiconductor substrate. An internal circuit including a first resistance element made of a silicon film formed in a third region of the main surface and an electrostatic circuit including a second resistance element made of a silicon film formed in the fourth region of the main surface of the semiconductor substrate. A first insulating film in the same layer as the second gate insulating film is formed under each of the first and second resistance elements.

  The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

  Compared with the case where a dummy active region is arranged in the element isolation region and a resistive element is arranged above the element active region, the ratio of the dummy active region to the entire area of the semiconductor substrate is reduced, the surface of the semiconductor substrate is planarized and the chip size is reduced. It is possible to achieve both reduction.

It is the schematic which shows the circuit structure of the semiconductor device which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the semiconductor device which is one embodiment of this invention. FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 2; FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 4; FIG. 5 is a plan view of relevant parts of a semiconductor substrate, illustrating a method for manufacturing a semiconductor device following FIG. FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 5; FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 7; FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor device following FIG. 8; It is a top view which shows the resistance element formed in the resistance element formed in the internal circuit, and the electrostatic protection circuit. It is sectional drawing which shows another example of the resistive element formed in the internal circuit and the resistive element formed in the electrostatic protection circuit. It is a top view which shows another example of the resistance element formed in the resistance element formed in the internal circuit, and the electrostatic protection circuit. It is sectional drawing which shows another example of the resistive element formed in the internal circuit and the resistive element formed in the electrostatic protection circuit. It is sectional drawing which shows another example of the resistive element formed in the internal circuit and the resistive element formed in the electrostatic protection circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a schematic diagram showing a circuit configuration of an LCD driver according to the present embodiment. The LCD driver includes input / output terminals (bonding pads) 50, an internal circuit 51, an electrostatic protection (ESD) circuit 52, and the like formed on the main surface of the semiconductor chip 1A made of single crystal silicon.

  Although not shown in FIG. 1, the internal circuit 51 is configured by a complementary MISFET or the like that operates with three types of power supply voltages (for example, 25 V, 6 V, and 1.5 V). In addition, a resistance element IR is formed in a part of the internal circuit 51. In the following description, complementary MISFETs (n-channel MISFETs and p-channel MISFETs) that operate with a power supply voltage of 25V are referred to as high withstand voltage MISFETs, and complementary MISFETs that operate with a power supply voltage of 6V are referred to as medium withstand voltage MISFETs. A complementary MISFET that operates with a power supply voltage of 1.5 V is referred to as a low breakdown voltage MISFET.

The electrostatic protection circuit 52 is disposed between the input / output terminal 50 and the internal circuit 51 and has a function of preventing destruction of the internal circuit 51 due to high-voltage static electricity applied to the input / output terminal 50. The electrostatic protection circuit 52 includes protection diodes D ₁ and D ₂ and a resistance element ER. A power supply voltage of 6 V is applied to the resistance element ER of the electrostatic protection circuit 52 and the resistance element IR of the internal circuit 51 as in the case of the medium voltage MISFET.

  Next, the LCD driver manufacturing method according to the present embodiment will be described in the order of steps with reference to FIGS. In order to simplify the description of the manufacturing method, only a p-channel type MISFET is illustrated for a low withstand voltage MISFET that operates with a power supply voltage of 1.5 V and a medium withstand voltage MISFET that operates with a power supply voltage of 6 V, respectively. The illustration of the type MISFET is omitted.

  First, as shown in FIG. 2, an element isolation trench 2 is formed in a semiconductor substrate (hereinafter simply referred to as a substrate) 1 made of p-type single crystal silicon. In order to form the element isolation trench 2, for example, a trench is formed in the substrate 1 by dry etching using a silicon nitride film as a mask, and then a silicon oxide film is deposited on the substrate 1 by the CVD method, and then the outside of the trench is formed. The silicon oxide film is removed by a chemical mechanical polishing method.

  In the figure, a region A is a region for forming a high voltage n-channel MISFET that operates with a power supply voltage of 25V, and a region B is a region for forming a high voltage p-channel MISFET that operates with a power supply voltage of 25V. C is a region for forming a medium withstand voltage p-channel type MISFET that operates at a power supply voltage of 6V, region D is a region for forming a low withstand voltage p-channel type MISFET that operates at a power supply voltage of 1.5V, and region E is a static region. A region where the resistance element ER6V of the electrical protection circuit 52 is formed and a region F indicate a region where the resistance element IR of the internal circuit 51 is formed. As shown in the figure, in this embodiment, the element isolation groove 2 is formed on the entire surface of the substrate 1 in the region (E) where the resistance element ER of the electrostatic protection circuit 52 is to be formed. On the other hand, the element isolation groove 2 is not formed in the substrate 1 in the region (F) where the resistance element IR of the internal circuit 51 is formed.

  Next, as shown in FIG. 3, phosphorus (P) is ion-implanted into a part of the substrate 1 and boron (B) is ion-implanted into the other part, whereby an n-type buried layer 3 is formed in a deep region of the substrate 1. Then, the p-type buried layer 4 is formed. Further, phosphorus is ion-implanted into a part of the substrate 1 in the regions (A, B) for forming the high-breakdown-voltage MISFET and the region (C) for forming the medium-breakdown-voltage MISFET, and boron is ion-implanted in the other portions. A type well 5 and a p-type well 6 are formed.

  The n-type well 5 formed in the substrate 1 in the region (A) functions as the source and drain of the high breakdown voltage n-channel MISFET, and the p-type well 6 formed in the substrate 1 in the region (B) has a high breakdown voltage. It functions as part of the source and drain of the p-channel type MISFET.

  Next, as shown in FIG. 4, a gate insulating film 7 is formed on the surface of the substrate 1 in the regions (A, B, E, F). In order to form the gate insulating film 7, first, the substrate 1 is thermally oxidized to form a thin silicon oxide film having a thickness of 10 nm or less on the surface, and then a silicon oxide film is deposited on the silicon oxide film by a CVD method. To do. At this time, the total thickness of the silicon oxide film formed by thermal oxidation and the silicon oxide film deposited by the CVD method is 60 nm or more. Next, these silicon oxide films are patterned using the photoresist film as a mask, and are left on the surface of the substrate 1 in the regions (A, B, E, F). At this time, almost the entire surface of the substrate 1 in the region (E, F) is covered with the gate insulating film 7.

  Next, as shown in FIG. 5, a high breakdown voltage n-channel MISFET gate electrode 8 is formed on the gate insulating film 7 in the region (A), and a high breakdown voltage p-channel is formed on the gate insulating film 7 in the region (B). A gate electrode 8 of the type MISFET is formed. In order to form the gate electrode 8, an n-type polycrystalline silicon film is formed on the substrate 1 by the CVD method, and then a cap insulating film 9 is formed on the n-type polycrystalline silicon film. The cap insulating film 9 is made of, for example, a laminated film of a silicon oxide film and a silicon nitride film. Next, the cap insulating film 9 and the n-type polycrystalline silicon film are patterned by dry etching using the photoresist film as a mask.

  At this time, in this embodiment, by leaving the cap insulating film 9 and the n-type polycrystalline silicon film on the gate insulating film 7 in the region (E), the n-type multi-layer whose surface is covered with the cap insulating film 9 is left. A resistance element ER made of a crystalline silicon film is formed. In addition, by leaving the cap insulating film 9 and the n-type polycrystalline silicon film on the gate insulating film 7 in the region (F), the resistance element made of the n-type polycrystalline silicon film whose surface is covered with the cap insulating film 9 IR is formed.

  FIG. 6 is a plan view showing the resistance element ER formed in the region (E) and the resistance element IR formed in the region (F). As shown in FIGS. 5 and 6, the resistance element IR of the internal circuit 51 is formed above the n-type buried layer 3 which is an active region. However, in the present embodiment, since the insulating film (gate insulating film 7) having a thickness of 60 nm or more is interposed between the n-type buried layer 3 and the resistance element IR, the substrate 1 (n-type buried layer) The coupling capacitance formed between the layer 3) and the resistance element IR is reduced.

  That is, according to the present embodiment, it is possible to dispose the resistance element IR on the active region (n-type buried layer 3) with little consideration of the capacitance with the substrate 1. As a result, the ratio of the dummy active region to the entire area of the substrate 1 can be reduced as compared with the case where the dummy active region is formed in the element isolation trench 2 in which the silicon oxide film is embedded and the resistive element IR is disposed thereon. Therefore, it is possible to achieve both planarization of the surface of the substrate 1 and reduction of the chip size.

  In the present embodiment, since the insulating film interposed between the n-type buried layer 3 and the resistance element IR and the gate insulating film 7 of the high voltage MISFET are formed at the same time, the special film for forming the insulating film is used. An unnecessary process becomes unnecessary.

  On the other hand, when the resistance element ER of the electrostatic protection circuit 52 is arranged on the active region, the ESD resistance deteriorates at the edge portion of the polycrystalline silicon film constituting the resistance element ER when high-voltage static electricity is applied. The problem that it is easy to do arises. That is, since the resistance element ER is normally applied with a voltage higher than the voltage applied to the resistance element IR by an external electrostatic voltage, the ESD resistance is likely to deteriorate. However, in the present embodiment, since the resistance element ER is disposed above the element isolation groove 2, the ESD resistance can be prevented from being deteriorated and the reliability of the electrostatic protection circuit 52 can be ensured. In other words, since the film thickness of the insulating film under the resistance element ER is formed to be larger than the film thickness under the resistance element IR, the electrostatic withstand voltage of the resistance element ER is higher than the electrostatic withstand voltage of the resistance element IR. Has improved. Furthermore, in the present embodiment, since the insulating film (gate insulating film 7) having a thickness of 60 nm or more is interposed between the element isolation trench 2 and the resistance element ER, the deterioration of the ESD resistance is more reliably ensured. Can be prevented.

  Next, as shown in FIG. 7, an n-type semiconductor region 10 is formed by ion implantation of phosphorus into the n-type buried layer 3 in the region (D) where the low breakdown voltage p-channel MISFET is formed. Subsequently, a gate insulating film 11 made of a silicon oxide film having a film thickness of 12 nm is formed in a region (C) where a medium breakdown voltage p-channel type MISFET is formed, and a film thickness is formed in a region (D) where a low breakdown voltage p-channel type MISFET is formed. A gate insulating film 12 made of a 3 nm silicon oxide film is formed.

  In order to form two types of gate insulating films 11 and 12 having different film thicknesses, first, the substrate 1 is thermally oxidized to have a film thickness of about 9 nm on the surface of the substrate 1 in the region (A, B, C, D). A silicon oxide film is formed. Next, the surface of the substrate 1 in the region (C) is covered with a photoresist film, and the silicon oxide film formed on the surface of the substrate 1 in the other regions (A, B, D) is removed by wet etching. Next, after removing the photoresist film, the substrate 1 is thermally oxidized again to form a gate insulating film 12 made of a silicon oxide film having a thickness of 3 nm on the surface of the substrate 1 in the region (A, B, D). Form. At this time, a silicon oxide film having a thickness of about 9 nm remaining on the surface of the substrate 1 in the region (C) grows to become a gate insulating film 11 having a thickness of 12 nm.

  Next, as shown in FIG. 8, the gate electrode 13 of the medium breakdown voltage p-channel type MISFET is formed in the region (C), and the gate electrode 14 of the low breakdown voltage p-channel type MISFET is formed in the region (D). In order to form the gate insulating films 13 and 14, an n-type polycrystalline silicon film is formed on the substrate 1 by a CVD method, and then the n-type polycrystalline silicon film is patterned by dry etching using a photoresist film as a mask.

  Next, as shown in FIG. 9, sidewall spacers 16 are formed on the side walls of the gate electrodes 8, 13, and 14. The sidewall spacer 16 is formed by anisotropically etching a silicon oxide film deposited on the substrate 1 by the CVD method. Subsequently, phosphorus is ion-implanted into a part of the substrate 1 and boron is ion-implanted into the other part, thereby forming an n-type semiconductor region 17 on the surface of the n-type well 5 in the region (A). A p-type semiconductor region 18 is formed on the surface of each of the p-type well 6 in the region (B), the n-type well 5 in the region (C), and the n-type semiconductor region 10 in the region (D). The n-type semiconductor region 17 formed in the n-type well 5 in the region (A) functions as the source and drain of the high breakdown voltage n-channel MISFET, and the p-type semiconductor formed in the p-type well 6 in the region (B). The region 18 functions as the source and drain of the high breakdown voltage p-channel type MISFET. The p-type semiconductor region 18 formed in the n-type well 5 in the region (C) functions as the source and drain of the medium breakdown voltage p-channel MISFET and is formed in the n-type semiconductor region 10 in the region (D). The p-type semiconductor region 18 functions as the source and drain of the low breakdown voltage p-channel type MISFET.

Through the steps so far, the high breakdown voltage n-channel MISFET (Q _HN ) is formed on the substrate 1 in the region (A), and the high breakdown voltage p-channel MISFET (Q _HP ) is formed on the substrate 1 in the region (B). Is done. Further, a medium breakdown voltage p-channel type MISFET (Q _MN ) is formed on the substrate 1 in the region (C), and a low breakdown voltage p-channel type MISFET (Q _LP ) is formed on the substrate 1 in the region (D).

  Next, as shown in FIG. 10 and FIG. 11, after removing the cap insulating film 9 covering the both ends of the polycrystalline silicon film constituting the resistance elements ER and IR, that is, the wiring connection portion by etching, A silicide layer 20 for reducing electric resistance is formed on the exposed surfaces of the resistance elements ER and IR. The reason why the silicide layers 20 on the resistance elements ER and IR are separately formed is to control a desired resistance value as the resistance element. In other words, the resistance value of the resistance element can be controlled by controlling the areas of the relatively low resistance silicide layer 20 and the relatively high resistance polycrystalline silicon film.

Although not shown, a high breakdown voltage n-channel MISFET (Q _HN ), a high breakdown voltage p-channel MISFET (Q _HP ), a medium breakdown voltage p-channel MISFET (Q _MN ), and a low breakdown voltage p-channel MISFET (Q _LP ). Silicide layers 20 are also formed on the surfaces of the respective sources and drains. Thereafter, a plurality of layers of wirings are formed on the substrate 1 with an interlayer insulating film interposed therebetween, but illustration thereof is omitted. The silicide layers 20 are formed of, for example, a cobalt silicide layer (CoSi ₂ ), a titanium silicide layer (TiSi ₂ ), a nickel silicide layer (NiSi ₂ ), or the like.

  According to the present embodiment, the resistance element IR can be arranged on the active region (n-type buried layer 3), so that the ratio of the dummy active region to the entire area of the substrate 1 can be reduced. It is possible to achieve both planarization of the surface of the substrate 1 and reduction of the chip size.

  In addition, since the insulating film interposed between the active region and the resistance element IR is formed at the same time in the process of forming the gate insulating film 7 of the high voltage MISFET, the above-described effects can be obtained without adding a manufacturing process. Can do.

(Embodiment 2)
In the first embodiment, the resistance element ER of the electrostatic protection circuit 52 is disposed above the element isolation groove 2, whereas in the present embodiment, the resistance element ER is provided as shown in FIGS. Arranged on the active region (n-type buried layer 3). On the other hand, the resistance element IR of the internal circuit 51 is arranged on the active region (n-type buried layer 3) as in the first embodiment.

  However, as described above, when the resistance element ER is arranged on the active region, the ESD resistance tends to deteriorate at the edge portion of the polycrystalline silicon film constituting the resistance element ER. Therefore, in the present embodiment, the central portion of the resistance element ER is disposed on the active region, and only the edge portion is disposed on the upper portion of the element isolation groove 2, thereby preventing the deterioration of the ESD resistance. Furthermore, by interposing an insulating film (gate insulating film 7) having a thickness of 60 nm or more between the element isolation trench 2 and the resistance element ER, it is possible to more reliably prevent the deterioration of the ESD resistance. Thereby, the coupling capacitance between the resistance element ER and the substrate 1 can be reduced.

  According to the present embodiment, the two types of resistance elements ER and IR can be arranged on the active region without degrading the ESD resistance of the resistance element ER and hardly considering the capacitance with the substrate 1. it can. Accordingly, the ratio of the element isolation region to the entire area of the substrate 1 can be reduced as compared with the case where the resistance elements ER and IR are disposed above the element isolation trench 2 in which the silicon oxide film is embedded. It is possible to achieve both planarization of the surface and reduction of the chip size.

(Embodiment 3)
As shown in FIG. 14, in the present embodiment, the resistance element ER of the electrostatic protection circuit 52 and the resistance element IR of the internal circuit 51 are respectively arranged above the element isolation groove 2. A plurality of dummy active regions 21 are formed in an island shape, a lattice shape, or a matrix shape in the element isolation trench 2 below each of the resistance elements ER and IR. As a result, the surface of the substrate 1 can be flattened as compared with the case where the resistance elements ER and IR are disposed above the element isolation trench 2 in which the silicon oxide film is embedded.

  In this case, in order to reduce the coupling capacitance between the dummy active region 21 and the resistance elements ER and IR, an insulating film (gate insulating film 7) having a large thickness is formed below each of the resistance elements ER and IR. Intervene. Further, in order to prevent the ESD resistance of the resistance element ER from deteriorating, the dummy active region 21 is not disposed below the edge portion of the resistance element ER.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the first embodiment, the resistance elements ER and IR are formed using the first-layer polycrystalline silicon film (the n-type polycrystalline silicon film used for the gate electrode 8 of the high voltage MISFET). The resistive elements ER and IR can be formed using the polycrystalline silicon film (the n-type polycrystalline silicon film used for the gate electrode 13 of the medium breakdown voltage p-channel type MISFET and the gate electrode 14 of the low breakdown voltage p-channel type MISFET). . Alternatively, one of the two types of resistance elements ER and IR can be formed of a first-layer polycrystalline silicon film, and the other can be formed of a second-layer polycrystalline silicon film.

  Although the case where the present invention is applied to an LCD driver has been described in the above embodiment, the present invention is not limited to this, and a high voltage MISFET having a thick gate insulating film and a resistance element made of a silicon film are formed on the same semiconductor substrate. It can be widely applied to various semiconductor devices to be formed.

  The present invention is used in a semiconductor device in which a high voltage MISFET and a resistance element are formed on the same semiconductor substrate.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1A Semiconductor chip 2 Element isolation groove 3 N type buried layer 4 P type buried layer 5 N type well 6 P type well 7 Gate insulating film 8 Gate electrode 9 Cap insulating film 10 N type semiconductor region 11, 12 Gate insulating film 13, 14 Gate electrode 16 Side wall spacer 17 n-type semiconductor region 18 p-type semiconductor region 20 silicide layer 21 dummy active region 50 I / O terminal (bonding pad)
51 Internal circuit 52 Electrostatic protection circuit D ₁ , D ₂ Protection diode ER Resistance element IR Resistance element Q _HN High breakdown voltage n-channel MISFET
Q _HP high breakdown voltage p-channel MISFET
Q _MP medium breakdown voltage p-channel MISFET
Q _LP low breakdown voltage p-channel MISFET

Claims (21)

A semiconductor substrate;
An element isolation groove formed on the semiconductor substrate;
A first insulating film embedded in the element isolation trench;
A plurality of dummy active regions defined by the element isolation grooves;
A second insulating film formed on the first insulating film and the plurality of dummy active regions;
A resistance element formed on the second insulating film,
No semiconductor element is formed in the plurality of dummy active regions,
The plurality of dummy active regions are formed under a resistive element,
An edge portion of the resistive element overlaps the first insulating film in a planar manner. The semiconductor device according to claim 1,
The semiconductor device, wherein the second insulating film is composed mainly of a silicon oxide film formed by a CVD method. The semiconductor device according to claim 1,
The resistance element is formed of a silicon film. The semiconductor device according to claim 1,
The plurality of dummy active regions are formed in an island shape, a lattice shape, or a matrix shape. The semiconductor device according to claim 1,
An edge portion of the resistance element is not formed on the dummy active region. The semiconductor device according to claim 1,
The resistance element is used as a part of an electrostatic protection circuit. The semiconductor device according to claim 6.
The semiconductor device is applied to an LCD driver. The semiconductor device according to claim 1,
A first MISFET is formed on the semiconductor substrate,
The first MISFET is
A first gate insulating film formed on the semiconductor substrate;
A first gate electrode formed on the first gate insulating film,
The semiconductor device, wherein the first insulating film and the first gate insulating film are formed of the same insulating film. The semiconductor device according to claim 8,
A second MISFET is formed on the semiconductor substrate,
The second MISFET is
A second gate insulating film formed on the semiconductor substrate;
A second gate electrode formed on the second gate insulating film,
The first MISFET is a MISFET that operates at a higher power supply voltage than the second MISFET,
The semiconductor device according to claim 1, wherein the film thickness of the first gate insulating film is larger than the film thickness of the second gate insulating film. The semiconductor device according to claim 9.
The semiconductor device, wherein the resistance element, the first gate electrode, and the second gate electrode are formed of the same silicon film. (A) forming an element isolation groove in the semiconductor substrate;
(B) burying a first insulating film in the element isolation trench;
(C) removing the first silicon film outside the element isolation trench by a chemical mechanical polishing method;
(D) after the step (c), a step of forming a second insulating film on the semiconductor substrate;
(E) forming a resistance element on the second insulating film,
Under the resistor element, a plurality of dummy active regions defined by the element isolation trench are formed,
No semiconductor element is formed in the plurality of dummy active regions,
A method of manufacturing a semiconductor device, wherein an edge portion of the resistive element overlaps the first insulating film embedded in the element isolation trench in a planar manner. In the manufacturing method of the semiconductor device according to claim 11,
The method of manufacturing a semiconductor device, wherein the second insulating film includes a silicon oxide film formed by a CVD method as a main component. In the manufacturing method of the semiconductor device according to claim 12,
The method of manufacturing a semiconductor device, wherein the second insulating film includes a silicon oxide film formed by a CVD method and a silicon oxide film formed by a thermal oxidation method. In the manufacturing method of the semiconductor device according to claim 11,
The method of manufacturing a semiconductor device, wherein the resistance element is formed of a silicon film. In the manufacturing method of the semiconductor device according to claim 11,
The method for manufacturing a semiconductor device, wherein the plurality of dummy active regions are formed in an island shape, a lattice shape, or a matrix shape. In the manufacturing method of the semiconductor device according to claim 11,
The semiconductor device manufacturing method, wherein an edge portion of the resistance element is not formed on the dummy active region. In the manufacturing method of the semiconductor device according to claim 11,
The method of manufacturing a semiconductor device, wherein the resistance element is used as a part of an electrostatic protection circuit. In the manufacturing method of the semiconductor device according to claim 17,
A method of manufacturing a semiconductor device, wherein the semiconductor device is applied to an LCD driver. In the manufacturing method of the semiconductor device according to claim 11,
The semiconductor device includes a first MISFET having a first gate insulating film formed on the semiconductor substrate and a first gate electrode formed on the first gate insulating film,
In the step (d), the first gate insulating film is formed,
The method of manufacturing a semiconductor device, wherein the first gate electrode is formed in the step (e). In the manufacturing method of the semiconductor device according to claim 19,
The semiconductor device includes a second MISFET having a second gate insulating film formed on the semiconductor substrate and a second gate electrode formed on the second gate insulating film,
In the step after the step (d) and before the step (e), the second gate insulating film is formed,
In the step (e), the second gate electrode is formed,
The first MISFET is a MISFET that operates at a higher power supply voltage than the second MISFET,
A method of manufacturing a semiconductor device, wherein the film thickness of the first gate insulating film is larger than the film thickness of the second gate insulating film. In the manufacturing method of the semiconductor device according to claim 20,
The method of manufacturing a semiconductor device, wherein the second gate insulating film is formed by a thermal oxidation method.

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