JPS61214576A - Semiconductor device - Google Patents

Abstract

PURPOSE:To protect internal circuits from electrostatic breakdown by a method wherein a source region and a drain region of a parasitic MIS element are composed of respective high density semiconductor regions and respective low density regions surrounding them and the high density regions are offset against a gate electrode. CONSTITUTION:A field insulation film 2 is formed on a surface of a P-type semiconductor substrate 1 and a gate electrode 15 is formed on the film 2. A source region and a drain region of a parasitic MIS element are constituted by N<+> type regions 18 and 19 formed at the same time with a source region and a drain region of an N-type MOSFET using the field insulation film 2 as a mask and N<-> type semiconductor regions 16 and 17 formed below the N<+> type regions 18 and 19 surrounding them respectively. The regions 16 and 17 are so formed as to overlap with the end parts of the electrode 15. As the electrode 15 is formed on the thick insulation film 2 only, this parasitic MOSFET has a high dielectric strength and electrical breakdown of the gate insulation film 2 is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a technique for preventing electrostatic damage in a semiconductor device including a MIS element.

[Background Art] In a semiconductor device having an MI or S element, especially a MOSFET, in its internal circuit, an input protection circuit is generally used to prevent the active MO8FET in the internal circuit from being damaged by electrostatic discharge.

Conventionally, this input protection circuit consists of a resistor and a clamp MO8FE.
An example of an input protection circuit using a clamp MO8FET is disclosed in Japanese Patent Application No. 59-174947 filed by the present applicant.

As a clamp MO3FET, active MO8FE
There are two methods: one using T surface breakdown and the other using parasitic MO8FET conduction using a field insulating film as a gate insulating film.

The surface breakdown voltage of the former active MO8FET is about 12 to 15V when the gate oxide film thickness is 250 angstroms, whereas the dielectric breakdown voltage of the active MO8FET of the internal circuit is about 25V.

Since the margin between the two is thus small, there is a problem in that it is difficult to use in terms of circuit design. Furthermore, since the charge is released using avalanche due to surface breakdown, the substrate potential rises and acts as a transistor, resulting in the problem that the protection element itself is destroyed.

On the other hand, in the case of a device using a parasitic MOSFET, in the case of a silicon gate process, an A
An I2 parasitic parasitic 8FET and a polysilicon parasitic MO3FET using polysilicon as a gate electrode are known.

The former Al parasitic MO8FET uses a field insulating film and a glabella insulating film as the gate insulating film, so the threshold voltage is as high as 15 to 20V, whereas the latter polysilicon parasitic MO8FET uses a field insulating film as the gate insulating film. Since only the insulating film is used, the threshold voltage is 10
~12v, which is set lower than the AQ parasitic MO8FET. Considering that the dielectric breakdown voltage of the active MO5FET in the internal circuit is about 25V, it can be seen that the polysilicon parasitic MO5FET has a margin and is easier to use.

By the way, according to studies conducted by the present inventors, it has been found that the polysilicon parasitic MO8FET has the following difficulties in its manufacturing process. In other words, due to the mask alignment margin between the edge of the field insulating film and the polysilicon gate, the polysilicon gate is
It is formed extending over the thin gate insulating film of the FET. This is because the source and drain regions and the polysilicon gate overlap each other through the thickness of the gate oxide film.

Although the thick gate oxide film of the parasitic MO3FET is essentially not destroyed, there is a problem in that dielectric breakdown occurs in the thin gate insulating film connected thereto.

[Object of the Invention] An object of the present invention is to provide a protection circuit element that prevents an active MOSFET in an internal circuit from being damaged by electrostatic discharge.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

That is, a gate electrode is formed on a field insulating film forming a parasitic MIS element. Therefore, no gate electrode is interposed on the thin gate insulating film, thereby preventing dielectric breakdown of the gate insulating film. Furthermore, parasitic MI
The source and drain regions of the S element are each formed of a highly doped semiconductor region and a surrounding lightly doped semiconductor region, with the highly doped region offset with respect to the gate electrode. Therefore, reduction in the junction breakdown voltage of the parasitic MIS element can be prevented.

[Example] An example in which the semiconductor device of the present invention is applied to an MO8 element will be described below with reference to FIGS. 1 to 3.

FIG. 2 shows a cross-sectional view of a CMO8 type semiconductor device having an active MO8FET in its internal circuit.

In the figure, active elements, namely an N-type MOSFET (on the left side of the figure) and a P-type MO8FET (on the right side of the figure), are formed on the surface of a P-type semiconductor substrate 1, separated by a field insulating film 2 of approximately 6000 angstroms. . For example, a gate insulating film 3 of 250 angstroms is formed in the N-type MO8FET region, and further,
A gate electrode 4 made of polysilicon is formed on this gate insulating film 3. On both sides of the gate electrode 4, a source region 5 and a drain region 6, which are high concentration N medium semiconductor regions, are formed by ion implantation using the gate electrode 4 and the field insulating film 2 as a blank. Furthermore, the gate electrode 4 and the source and drain regions 5,
6, a thin oxide film 11 is formed.

An N-type well 7 is formed in the P-type MO8FET region, and a gate insulating film 3 and a gate electrode 8 are formed on the surface of the well 7 in the same manner as in the N-type MOSFET. Source area 10. Drain region 9 is constituted by a P4 type semiconductor region formed by ion implantation using gate electrode 8 and field insulating film 2 as a mask. Further, a thin oxide film 11 is formed on the gate electrode 8 and the source and drain regions 9 and 10, similarly to the N-type MO8FET. Reference numeral 12 denotes a glabellar insulating film formed on the thin oxide film 11 and the field insulating film 2, and a phosphosilicate glass (PSG) film is used. code 1
Reference numeral 3 denotes an aluminum wiring, which is used for ohmic contact with the source and drain regions and for mutual wiring between the drain region 6 of the N-type MO8FET and the drain region 9 of the P-type MO5FET.

Furthermore, a passivation film 1 is placed on the aluminum wiring.
4 is formed.

FIG. 1 shows a cross-sectional view of a parasitic MO8FET according to an embodiment of the present invention.
Portions having the same functions as FETs are indicated by the same reference numerals.

A field insulating film 2 is formed on the surface of the P-type semiconductor substrate 1, and a gate electrode 15 is formed on this field insulating film 2.
is formed. The gate electrode 15 is made of polysilicon and is formed in the same process as the gate electrodes 4 and 8 of the active MO8FET. The source and drain regions of the parasitic MO8FET are located below and surrounding the N-type semiconductor regions 18 and 19, which were formed simultaneously with the source and drain regions of the N-type MO5FET using the field insulating film as a mask, and further below the N-type region. As low concentration of N″″
It is constituted by semiconductor regions 16 and 17 of the N- type, and the N- type regions 16 and 17 are formed at the ends of the gate electrode 15 so as to overlap therewith. The N-type regions 16 and 17 are formed in the same process as the well 7 of the active P-type MO8FET.

In the parasitic MO8FET of the present invention, since the gate electrode 15 is formed only on the thick field insulating film 2, its dielectric breakdown voltage is high and the gate insulating film is not destroyed.

In addition, the source and drain regions are highly doped N0-type regions 18 and 19 and a lightly doped N''''-type region 16 surrounding them.
．． 17, and.

While the N- type regions 16 and 17 are arranged to overlap at the end of the gate electrode 15, the N+ type region 181
Since the gate electrode 9 has a so-called offset structure formed apart from the gate electrode 15, the junction breakdown voltage is increased.

Therefore, when high voltage static electricity or air is applied to the input, the parasitic MO8FET immediately becomes conductive, which prevents the gate insulating film of the active MO8FET in the internal circuit from being destroyed, and also prevents the parasitic MO8FET from being destroyed. Since breakdown at the junction can also be prevented, it is possible to realize a highly reliable semiconductor device.

FIG. 3 specifically shows an example in which the parasitic MO8FET shown in FIG. 1 is used as an input protection circuit by comparing the circuits. Reference numeral 22 is the parasitic MO8 explained in FIG.
FET, and point A is the polysilicon gate electrode 15. B
The dots correspond to the drain electrodes 21, which are wired to each other and connected to the input pad. Further, six points correspond to the source electrode 20 and are grounded to the substrate potential. Point D corresponds to the gate electrode 4.8 of the active MO8FET in the internal circuit. Reference numeral 23 is a resistor inserted between points B and D. The input protection circuit using the parasitic MO5FET of the present invention is not limited to the one shown in FIG. It goes without saying that a circuit method can be applied.

[Effects] (1) The gate electrode of the input protection circuit is formed only on the thick field insulating film. Therefore, no gate electrode is interposed on the thin gate insulating film, and dielectric breakdown of the thin insulating film can be prevented.

(2) In the drain region, the N-type region forms an offset structure with the gate electrode, and the gate end has a low concentration of N-
Since the type region is formed to surround the N-type region, the junction breakdown voltage of the parasitic mosFEr will not be lowered.

(3) Form the gate electrode of the parasitic MO8FET and the gate electrode of the active MO8FET in the internal circuit.

Active MO5FET4 source and drain regions
Since the Q source, drain region, and well of the P-type MO8FET can be formed in the same process, there is no additional process.

(4) Since the gate electrode of the parasitic MO8FET is formed in the same process as the gate electrode of the active MO8FET of the internal circuit, the threshold voltage can be set with good control, and the protection function against electrostatic damage can be performed with sufficient margin.

Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited to the above-mentioned examples, and various changes can be made without departing from the gist thereof. For example, in the embodiment, polysilicon is used as the gate electrode, but it goes without saying that metal or metal-silicide can also be used.

[Field of Application] The present invention can be applied to a semiconductor device using a parasitic MIS element in an input protection circuit, and is particularly suitable for application to MO8LSI.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a cross-sectional structure of a parasitic MO8FET of a semiconductor device of the present invention, and FIG. 2 is a diagram showing a C
Figure 3 is a diagram showing the cross-sectional structure of an MO8 type semiconductor device.
FIG. 2 is a diagram illustrating the relationship between the parasitic MO8FET shown in the figure and a specific input protection circuit. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Field insulating film, 3...
...Gate insulating film, 4,8.15...Gate electrode, 7
．． 16, 17...N-type semiconductor region, 5.6, 18,
19...N skewer type semiconductor region, 9.10...P medium size semiconductor region, 11...Light oxide film, 12...Interlayer insulating film, 13, 20, 21... Aluminum wiring, 14
...passivation film, 22...parasitic MO8FE
T, 23...Resistance. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. A protection circuit for protecting internal circuits from electrostatic discharge damage includes at least a parasitic MIS element, and this parasitic MIS element has a gate electrode formed on a field insulating film and a gate electrode formed on the field insulating film. A semiconductor device comprising source and drain regions extending downward and overlapping a gate electrode. 2. The source and drain regions each include a first semiconductor region with a high concentration and a second semiconductor region with a low concentration surrounding the first semiconductor region, and the first semiconductor region is offset with respect to the gate electrode. A semiconductor device according to claim 1, characterized in that: