JPS6126700B2 - - Google Patents

Info

Publication number
JPS6126700B2
JPS6126700B2 JP56028452A JP2845281A JPS6126700B2 JP S6126700 B2 JPS6126700 B2 JP S6126700B2 JP 56028452 A JP56028452 A JP 56028452A JP 2845281 A JP2845281 A JP 2845281A JP S6126700 B2 JPS6126700 B2 JP S6126700B2
Authority
JP
Japan
Prior art keywords
data
memory
series
register
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56028452A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57143654A (en
Inventor
Shigeru Komatsu
Shigeru Hirahata
Tsuguji Tateuchi
Takuo Koyama
Kunihiko Nagai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56028452A priority Critical patent/JPS57143654A/ja
Publication of JPS57143654A publication Critical patent/JPS57143654A/ja
Publication of JPS6126700B2 publication Critical patent/JPS6126700B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
JP56028452A 1981-03-02 1981-03-02 Memory sequence extending circuit Granted JPS57143654A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56028452A JPS57143654A (en) 1981-03-02 1981-03-02 Memory sequence extending circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56028452A JPS57143654A (en) 1981-03-02 1981-03-02 Memory sequence extending circuit

Publications (2)

Publication Number Publication Date
JPS57143654A JPS57143654A (en) 1982-09-04
JPS6126700B2 true JPS6126700B2 (fr) 1986-06-21

Family

ID=12249051

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56028452A Granted JPS57143654A (en) 1981-03-02 1981-03-02 Memory sequence extending circuit

Country Status (1)

Country Link
JP (1) JPS57143654A (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0179981B1 (fr) * 1984-10-26 1992-08-26 International Business Machines Corporation Appareil de traitement de données à espace d'adressage fixe et à mémoire variable
JPS61160162A (ja) * 1985-01-07 1986-07-19 Meidensha Electric Mfg Co Ltd メモリのペ−ジ方式
JPS61211750A (ja) * 1985-03-15 1986-09-19 Nec Corp メモリバンク切替え確認方式

Also Published As

Publication number Publication date
JPS57143654A (en) 1982-09-04

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