JPS61264877A - Picture display device - Google Patents

Abstract

PURPOSE:To make a signal peak-to-peak value smaller and to constitute as one IC by segmenting a picture display in a vertical direction, generating an electron beam at every section, deflecting it in the vertical direction and making a distance from a horizontal focusing electrode to a high voltage electrode longer. CONSTITUTION:A primary color signal 101 is converted to digital dataan A/D conversion circuit 102 and they are inputted to a 1H memory 103 and are writ ten in time sequential by a latch start pulse 104 and are transferred to the next stage of 1H memory 106 in a horizontal period. the output of a PWM conversion part 107 is introduced to the conductive plat of a beam current control electrode through an output part 108. At such a stage, the 1H memories 103 and 106 and the PWM conversion part 107 are assembled to a small signal logic part IC 110 and each of an output part 108 is assembled to an output part IC 111 and each of the IC 110 and the IC 111 is assembled to a driving IC 112 as one IC constitution. This invention makes a driving IC superior by changing the design of an electrode and brings about cost down by forming it as one IC constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention generates an electron beam for each division when a screen on a screen is vertically divided into a plurality of divisions, and generates an electron beam for each division. The present invention relates to an apparatus for displaying a plurality of lines by vertically deflecting a beam to display a television image as a whole.

Conventional technology Traditionally, cathode ray tubes have been mainly used as display elements for displaying color television images, but conventional cathode ray tubes have a very long depth compared to the screen size, making it difficult to use in thin television receivers. It was impossible to create. In addition, although EL display elements, plasma display devices, liquid crystal display elements, etc. have recently been developed as flat display elements, all of them are insufficient in terms of performance such as brightness, contrast, and color display, and have not been put into practical use. I haven't reached Runibayashi yet.

Therefore, the present applicant proposed a new display device in Japanese Patent Application No. 56-20618 (Japanese Unexamined Patent Publication No. 57-135590) to achieve a flat display device using electron beams.

This method generates an electron beam for each section when the screen is vertically divided into multiple sections, and displays multiple lines by deflecting each electron beam vertically for each section. However, it displays a television image as a whole.

First, a basic configuration of the image display element used here will be explained with reference to FIG. This display element consists of, in order from the back to the front, a back electrode (1), a line cathode (2) as a beam source, vertical focusing electrodes (3) (3'), a vertical deflection electrode (4), and a beam flow control electrode. (5), horizontal focusing electrode (6
), a horizontal deflection electrode (7), a beam acceleration electrode (8), and a screen (9) are arranged, and these are housed in the evacuated interior of a fan-shaped glass bulb (not shown). There is. A line cathode (2) serving as a beam source is stretched horizontally so as to generate an electron beam distributed linearly in the horizontal direction, and a plurality of line cathodes (2) are arranged vertically at appropriate intervals. Books ((2a) to (2) in the figure)
d) only four are shown). In this example, it is assumed that 15 are provided. them (2a)
~(20). These line cathodes (2) are for example 1
An oxide cathode material for thermionic emission is coated on the surface of a tanned and Gesten wire of 0 to 20 μφ. and.

These line cathodes (2a) to (2o) are heated so as to generate a thermionic electron beam by passing an electric current through them, and as described later, the line cathodes (2a) are heated to generate electrons for a certain period of time. controlled to emit a beam. The back electrode (1) suppresses the generation of electron beams from other line cathodes other than the line cathode that is controlled to emit electron beams for a certain period of time, and directs the generated electron beams only in the forward direction. It has the effect of pushing out. This back electrode (1) may be formed by a coating of electrically conductive material applied to the inner surface of the rear wall of the glass bulb. Further, a one-plane electron beam emitting cathode may be used instead of the back electrode (1) and the line cathode (2).

The vertical focusing electrode (3) is a conductive plate (11) having a horizontally long slit (10) facing each of the line cathodes (2a) to (2o), and collects the electron beam emitted from the line cathode (2). taken out through the slit (10),
and vertically focused. 1 horizontal line (3
In Figure 6, the electron beam for 60 picture elements is taken out at the same time.
Of these, only one section in the horizontal direction is shown.

The slits (10) may be provided with crosspieces at appropriate intervals in the middle, or may be a row of through holes provided in large number at small intervals in the horizontal direction (intervals that are almost touching). So are the six vertical focusing electrodes (3'), which may be configured substantially as slits.

A plurality of vertical deflection electrodes (4) are arranged horizontally at intermediate positions between the slits (10),
Conductors (
13) (13') is provided. Then, a vertical deflection voltage is applied between the opposing conductors (13) (13'') to deflect the electron beam in the vertical direction. In this example, the pair of conductors (13) (13'')
), the electron beam from one line cathode (2) is deflected vertically to a position corresponding to 16 lines.

The 16 vertical deflection electrodes (4) constitute 15 conductor pairs corresponding to each of the 15 line cathodes (2), so that 240 horizontal lines are drawn on the screen (9). Deflect the electron beam to

Next, the control electrodes (5) are composed of conductive plates (15) each having a long slit (14) in the vertical direction, and a plurality of control electrodes (5) are arranged in parallel in the horizontal direction at a predetermined interval.

In this example, 180 control electrode conductive plates (15-1)
~(15-n) are provided. (Only 9 lines are shown in the figure). Each of the control electrodes (5) separates and extracts the electron beam into two picture elements in the horizontal direction, and controls the amount of electron beam passing therethrough in accordance with a video signal for displaying each picture element. Therefore, the conductive plate for the control electrode (5) (
If 180 lines of 15-1) to (15-n) are provided, 360 picture elements can be displayed per horizontal line. Also,
In order to display images in color, each picture element is displayed using phosphors of three colors R, G, and B, and each control electrode (5) has R and G for two picture elements.

Each video signal of B is added sequentially. In addition, 180 pairs of video signals for one line (2 pixels per pair) are simultaneously applied to each of the 180 conductive plates (15-1) to (15-n) for control electrodes (5). One line of video is displayed at one time.

The horizontal focusing electrode (6) is connected to the slit (14) of the control electrode (5).
) is composed of a conductive plate (17) having a plurality of vertically long slits (16) facing each other, and the electron beam for each pixel divided horizontally is transmitted horizontally. Focus into a narrow beam of electrons.

The horizontal deflection electrode (7) is composed of a plurality of conductive plates (18) (18') arranged vertically on both sides of the slit (16), and each electrode (1g) ( 18') is applied with six levels of horizontal deflection voltage to deflect the electron beam of each picture element in the horizontal direction, so that two sets of R and G are displayed on the screen (9).

Each phosphor of B is sequentially irradiated to emit light. In this embodiment, the deflection range is two picture elements wide for each electron beam.

The accelerating electrode (8) is composed of a plurality of conductive plates (19) installed horizontally in the same position as the vertical deflection electrode (4), and it directs the electron beam to the screen (9) with sufficient energy. Accelerate to cause a collision.

The screen (9) is constructed by applying a phosphor (20) that emits light when irradiated with an electron beam to the back surface of a glass plate (21), and adding a metal back layer (not shown). The phosphor (20) has two phosphors of three colors R2O and B for one slit (14) of the control electrode (5), that is, for each one electron beam divided in the horizontal direction. They are provided in pairs and are applied in vertical stripes. In FIG. 3, the broken lines drawn on the screen (9) indicate the divisions in the vertical direction that are displayed corresponding to the plurality of line cathodes (2), and the two-dot chain lines indicate the divisions in the vertical direction that are displayed corresponding to the plurality of line cathodes (2). ) shows the horizontal divisions displayed corresponding to each of them. As shown in the enlarged view in Figure 4, one section partitioned by these two has R, G, and B phosphors (20) for 2i elements in the horizontal direction, and 16 lines in the vertical direction. It has a width of The size of one section is, for example, 1 m in the horizontal direction.

The vertical direction is 9+na+.

Note that in FIG. 3, the length in the horizontal direction is greatly expanded relative to the length in the vertical direction for clarity.

In addition, in this example, two R, G, and B phosphors (20) are used for one control electrode (5), that is, one electron beam.
Although only one pair of picture elements is provided, of course, one picture element or three or more picture elements may be provided, and in that case, the control electrode (5) has one picture element or three or more picture elements. R, G, and B video signals are sequentially applied for the purpose, and horizontal deflection is performed in synchronization with the R, G, and B video signals.

Next, the basic configuration and waveforms of each part of a drive circuit for displaying television images on this display element will be explained with reference to FIG. First, a driving portion for irradiating the screen (9) with an electron beam to emit raster light will be described.

The power supply circuit (22) is a circuit for applying a predetermined bias voltage (operating voltage) to each electrode of the display element.

The back electrode (1) has a -V vertical focusing electrode (3) (3'
) has v3. A DC voltage of V3' is applied to the horizontal focusing electrode (6), V is applied to the acceleration electrode (8), and V is applied to the screen (9).

Next, a composite video signal of a television signal is applied to the input terminal (23), and a vertical synchronization signal V and a horizontal synchronization signal H are separated and extracted in a synchronization separation circuit (24).

The vertical deflection drive circuit (40) includes a vertical deflection counter (2
5), a memory for vertical deflection signal storage (27), and a digital-to-analog converter (39) (hereinafter referred to as a DA converter). As input pulses to the vertical deflection drive circuit (4o), a vertical synchronizing signal V and a horizontal synchronizing signal H shown in FIG. 6 are used. Vertical deflection counter (25) (
8 bits) are reset by the vertical synchronizing signal V and counting the horizontal synchronizing signal H.

This vertical deflection counter (25) counts the effective scanning period (in this case, a period of 240H) excluding the vertical blanking period of the vertical period, and this count output is supplied to the address of the memory (27). be done. The memory (27) outputs vertical deflection signal data (here, 8 bits) corresponding to each address, and the D-A converter (39) outputs the data of the sixth vertical deflection signal.
It is converted into vertical deflection signals of υ and υ'' shown in the figure (Fig. 5 (b) D). In this circuit, there is a memory address for storing vertical deflection signals corresponding to each line of 240H, and 16H of vertical deflection signals are stored. By storing regular data in the memory, 16 levels of vertical deflection signals can be obtained.

On the other hand, the line cathode drive circuit (26) uses the vertical synchronization signal V and the output of the vertical deflection counter (25) to create line cathode drive pulses a to 0. FIG. 7(a) shows the vertical synchronizing signal V,
The relationship between the horizontal synchronizing signal H and the lower 5 bits of the vertical deflection counter (25) is shown. FIG. 7(b) shows a method of creating line cathode drive pulses a' to 0' every 16H using these signals. In FIG. 7, LSB indicates the lowest bit, and (LSB+1) means the bit one higher than the LSB.

The first line cathode drive pulse a' is generated using the vertical synchronizing signal V and the output (LSB+4) of the vertical deflection counter (25).
The line cathode drive pulses b' to o' can be generated using a -S flip-flop, etc., and the line cathode drive pulses b' to o' are generated by inverting the line cathode drive pulse a' of the output (LSB+3) of the vertical deflection counter (25) using a shift register. It can be obtained by using something as a clock and transferring it. This drive pulse a'~
0' is inverted and converted into a line cathode drive pulse a''o which is made low potential only during each pulse period and made high potential of about 20 volts during other periods (Fig. 5(b) E).
, are added to each line cathode (2a) to (20).

Each line cathode (2a) to (2o) has its driving pulse a'=
A current is applied to heat it during the high potential period of drive pulses a to 0, and the heated state is maintained so that electrons can be emitted during the low potential period of drive pulses a to 0. As a result, 15 wire cathodes (
Electrons are emitted from 2a) to (20) only during the 16H period when low potential drive pulses a to 0 are applied to each of them. During periods when a high potential is applied, the potential at the line cathode (2a) is lower than the potential at the position of the line cathode (2) determined by the bias voltage applied to the back electrode (1) and the vertical focusing electrode (3). Since the high potential applied to ~(2o) is more positive, no electrons are emitted from the line cathodes (2a) to (20). Thus, in the line cathode (2), during the effective vertical scanning period, the upper line cathode (2a)
Electrons are sequentially emitted from the line toward the line cathode (2o) for each 16H period. The emitted electrons are pushed forward by the back electrode (1), pass through the opposing slits (10) of the vertical focusing electrode (3), and are focused in the vertical direction to form a flat electron beam. .

Next, the line cathode drive pulse a ”o and the vertical deflection signal υ,
The relationship with υ'' will be explained using Fig. 8.
Figure (a) is a waveform diagram of a line cathode drive pulse, (b) is a waveform diagram of a vertical deflection signal, and (c) is a waveform diagram of a horizontal deflection signal. Vertical deflection signal υ in FIG. 8(b).

υ' changes by IH in 16 steps during the 16H period of each line cathode pulse a to 0 in FIG. 8(a).

Both vertical deflection signals υ and υ' have a center voltage of v4, and υ increases sequentially and υ' decreases sequentially.
They are designed to change in opposite directions. These vertical deflection signals υ and υ' are applied to the electrodes (13) and (13'') of the vertical deflection electrode (4), respectively, resulting in an electron beam generated from the respective line cathodes (2a) to (20). is vertically deflected in 16 steps, and as mentioned earlier, on the screen (9), one electron beam is deflected so that a raster of 16 lines is drawn sequentially one line at a time from the top.

As a result of the above, electron beams are emitted sequentially from the top of the 15 line cathodes (2a) to (2o) for a period of 16H, and each electron beam is sequentially emitted in one line from top to bottom within 15 sections in the vertical direction. On the screen (9), from the first line at the top to the 24th line at the bottom.
The electron beam is vertically deflected one line at a time up to the 0th line, and a total of 240 raster lines are drawn.

The vertically deflected electron beam is sent to the control electrode (5).
It is divided into 180 sections in the horizontal direction by a horizontal focusing electrode (6) and taken out. In Figure 4, one of them
The classification is shown. The amount of electron beam passing through each section is controlled by a control electrode (5), and is focused in the horizontal direction by a horizontal focusing electrode (6) to form a single C narrow electron beam.

The light is deflected in six steps in the horizontal direction by the horizontal deflection means described below, and is sequentially irradiated onto the R2O, B capacitive light body (20) for two picture elements on the screen (9). FIG. 4 shows the vertical and horizontal divisions. The phosphors corresponding to (15-1) to (15-n) of the control electrode (5) are R, G, and B for two picture elements, but for convenience of explanation, one picture element is R1,
G1. Let B1 and the other be R, , G, , B2.

Next, the horizontal deflection drive circuit (41) is composed of a horizontal deflection counter (28) (11 bits), a memory (29) that stores horizontal deflection signals, and a DA converter (38). . As shown in FIG. 9, the input pulses of the horizontal deflection drive circuit (41) are synchronized with the vertical synchronizing signal V and the horizontal synchronizing signal H, and a pulse 6H having a repetition frequency six times that of the horizontal synchronizing signal H is used. The horizontal deflection counter (28) is reset by the vertical synchronizing signal V and receives the horizontal six times the pulse 6H.
count. This horizontal deflection counter (28) is
6 times during H, 240Hx 6/H= 1 during 1v
It counts 440 times, and this count output is stored in the memory (29
) is supplied to the address.

The memory (29) outputs horizontal deflection signal data (8 bits in this case) according to the address, and the D-A converter (38) converts it as shown in Figure 9 (Figure 5 (b) C). ,h'
is converted into a horizontal deflection signal such as In this circuit, 5
There is a memory address for storing horizontal deflection signals corresponding to each of can be obtained.

As shown in FIG. 9, these horizontal deflection signals are a pair of horizontal deflection signals ri and h' that change in six steps, both of which have a center voltage of v7, and h decreases sequentially.

h' changes in opposite directions so as to increase sequentially. These horizontal deflection signals h' are applied to electrodes (18) and (1g') of the horizontal deflection electrode (7), respectively. As a result, each horizontally segmented electron beam is applied to the R, G of the screen (9) during each horizontal period.

B, R, G, B (R,, G,, B□= Rz−Gz−
It is horizontally deflected so that the phosphor of Bz) is sequentially irradiated for H/6 periods. Thus, in each line raster, the electron beam is R□2 for each of the 180 sections in the horizontal direction.
Each phosphor (20) of G□, B□, R,, G,, B2
are irradiated sequentially.

Therefore, the electron beam is set to R1, G for each horizontal section of each line.
,,B1. By modulating with R, , G, , B video signals, a color television image can be displayed on the screen (9).

Next, the modulation control portion of the electron beam will be explained. First, the composite video signal applied to the television signal input terminal (23) is applied to the color demodulation circuit (30), where the R-Y and B-Y color difference signals are demodulated and the G-Y color difference signal is demodulated. The signals are matrix-synthesized, and further, they are combined with the luminance signal Y to form each primary color signal C of R2O, B and below R,
G, B video signals) are output. Those R,G
, B. Each video signal is processed by 180 sample and hold circuits (3
1-1) to (31-n). Each sample-and-hold circuit (31-1) to (31-n) has six sample-and-hold circuits for R, G1, B1, R2, G2, and B2. These sample and hold outputs are stored in the holding memories (32-1) to (32-1), respectively.
−n).

On the other hand, the reference clock oscillator (33) is composed of a PLL (phase-locked loop) circuit, etc., and in this example, the reference clock 6fsc is six times the color subcarrier fsc.
and a double reference clock 2fsc is generated. The reference clock is controlled to always have a constant phase with respect to the horizontal synchronizing signal H.

The reference clock 2fsc is a deflection pulse generation circuit (42)
signals 6H and H/6, which are six times the horizontal synchronization signal H.
Signal switching pulse rxt gx+ b□* f'z
A pulse of rgzs I)z (FIG. 5(b) B) is obtained. On the other hand, the reference clock 6fsc is applied to the sampling pulse generation circuit (34), where it is delayed by one clock cycle by a shift register, etc.
108θ sampling pulses R, 1, G, 1 . B.1. R12,G...
B1□tR219G2L9Bitz* G22%
B22~Rnxt Gn,, Bn,, Rn,.

On, , Bn, (FIG. 5(b) A) are generated in sequence, and then one transfer pulse t is generated. These sampling pulses R11 to Bn correspond to each picture element when one line of the video to be displayed is divided into 360 picture elements in the horizontal direction, and their positions are always constant with respect to the horizontal synchronizing signal H. controlled as follows.

These 1080 sampling pulses R, ~Bn, each form 180 sets of sample hold circuits (31-1).
-(31-n), and as a result, each sample-hold circuit (31-1) to (31-n) has an R1 value of 2 pixels for each of 180 pixels divided into 1 line. , Gyu, B1. R,,G2. Each video signal of B is individually sampled and held. The sample-held 180 pairs of R1, G□, B1.
R.

G2. The video signal of B is stored in 180 sets of memories (32-1) to (32-n) after completing the sample hold for one line.
) are transferred all at once by a transfer pulse t, and held here for the next horizontal period. This retained R-work.

G., B1. R2, G2. The signal B is applied to switching circuits (35-1) to (35-n). The switching circuits (35-1) to (35-n) each have R□, G1. It is composed of a tri-state or analog gate having individual input terminals for B1°R, , G, , B and a common output terminal for sequentially switching and outputting them.

The output of each switching circuit (35-1) to (35-n) is 180 sets of pulse width modulation (PWM) circuit (37-1)
(37-n), and here, the reference pulse signal is pulse width modulated according to the magnitude of the sampled and held Rz-Gx-Bt and Rz-Gz-Bz video signals and is output. It is desirable that the repetition period of the reference pulse signal is sufficiently smaller than the pulse width of the signal switching pulses r□zgtvb□, r2゜gztbz,
For example, a ratio of about 1:10 to 1:100 is used.

The outputs of the pulse width modulation circuits (37-1) to (37-n) are used as control signals for modulating the electron beam to the 180 conductive plates (15-1) to the control electrodes (5) of the display element.
(15-n) respectively. The switching circuits (35-1) to (35-n) are simultaneously controlled by switching pulses rxy giy' bl, rzt gzt bz applied from the switching pulse generating circuit (36). The switching pulse generation circuit (36) generates a signal switching pulse from the deflection pulse generation circuit (42) described above.rye gzt blt rye
gzt bz, each horizontal period is divided into 6 and the switching circuit (35-1) is divided into H/6.
~(35-n), R1, G1 . B□、R、、
Switching signals r+g1gb are used to time-divide and sequentially output the G, , B video signals and supply them to the pulse width modulation circuits (37-1) to (37-n).

Generate rz+gz+bx.

What should be noted here is that the switching circuit (35-1
) to (35-n) R 1+ Gx* Bt, R
2FG2. Switching the supply of video signals of B and electron beam R processing using the horizontal deflection drive circuit (41)
tR,.

G2. B, the horizontal deflection of the irradiation switching to the phosphor.

They are synchronously controlled to completely match both timing and order. As a result, when the electron beam is irradiating the R0 phosphor, the irradiation amount of the electron beam is controlled by the R1 video signal, and the G,
, B, , R, , G, , B are controlled in the same way, and the light emission of each phosphor of each picture element R,, G, B1° R,, G,, B2 , G.

Each picture element is controlled by Bi, R, , G, and B video signals, and each picture element is displayed by emitting light according to the input video signal. This control is for one line.
This is done simultaneously for 80 sets (2 picture elements each), and an image of 360 picture elements per line is displayed.

Furthermore, the processing is performed sequentially for 240H lines starting from the upper line, and one image is displayed on the screen (9).

and one or more such operations are performed on one or more of the input television signals.
This is repeated for each field, and as a result, a moving television image is displayed on the screen (9) in the same way as a normal television receiver.

Problems to be Solved by the Invention The signal driving section of the above image display device is divided into a small signal logic section and an output section (pulse amplifier section). This is because the peak value of the pulse waveform of the output section output that actually drives the electrodes is very high at 30 to 35 V, and is quite different from the 5 V of the small signal logic section. This is because it cannot be formed. Furthermore, the number of input/output connections is extremely large, making implementation extremely complicated. As described above, there are two major problems when implementing ICs: (a) increased cost due to not being able to be integrated into the same chip; and (b) increased cost due to extremely complicated wiring.

The present invention solves this problem by driving the output section by reducing the peak value of 30 to 35 V to around 15 V, so that the output section and the small signal lodge section are integrated into the same chip. An object of the present invention is to provide an image display device in which the image display device is incorporated.

Means for Solving the Problem In order to solve this problem, the present invention configures the distance from the horizontal focusing electrode to the beam acceleration electrode, which is a high voltage electrode, and the screen surface to be longer than the conventional distance, and the beam flow control electrode The device is configured to be driven by reducing the peak value of the applied signal.

In other words, the drive voltage of the beam current control current electrode (5) (this electrode is mainly modulated in response to video signals and is also called a signal modulation electrode) is very dependent on the horizontal focus diameter between the screen and the horizontal focus diameter. Under the typical driving conditions of the image display device proposed earlier (driving voltage value of signal modulation electrode = 32V), the horizontal focus diameter φH color is 100μ
It is m. In addition, the distance L□ between the horizontal focusing electrode (6) and the beam accelerating electrode (8), which is a high voltage electrode, and the distance L2 between the beam accelerating electrode (8) and the surface of the screen (9) are as follows. This is determined by the proposed invention (Japanese Patent Application No. 57-80437), and the actual distance is 9 m for Li"'4°2WR and L2 color, as shown in FIG. 2(B).

this is.

Basically, it is determined based on the condition that the vertical amplitude width is sufficient, and it does not directly affect the horizontal focus. Practically speaking, if the absolute value of these distances L□ becomes smaller, the horizontal focus diameter φ) also becomes smaller, and the overall thickness of the image display device becomes thinner.6 However, the present invention has the advantage that this L□ Take a large size, L engineering'M 8
By designing around mm-L 2 colors 9 nu, it is possible to lower the applied voltage value of the signal modulation electrode to about 15V, and the conventional small signal logic section and output section can be created on the same C-MOS chip. It has an IIC configuration.

Effect: With this configuration, the L1 value can be increased, for example, 8III11
By doing so, the signal modulation drive circuit is integrated into one chip, and the I
This reduces costs when converting to C, and also reduces costs in terms of implementation by eliminating the complexity of input/output connections, which is a great advantage for commercializing conventional image display devices.

In addition, this invention actually has the disadvantage that φR deteriorates to around 150 μm by increasing L□ to 81ff11, but when considering the size of the pixel when considering ignition development, the horizontal It seems that the focus diameter is sufficiently accurate, so this is not a major drawback.

EXAMPLE An example of the present invention will be described below based on the drawings. 1st
The figure shows an IC block diagram of the drive circuit.

In Figure 1, (101) is the input primary color signal,
This primary color signal is input to an A-D converter circuit (102) and converted into digital data, this data is input to an IH memory (103), and this input signal is sequentially converted in time by a latch start pulse (104). written,
It is configured to be transferred to the next stage IH memory (106) in a horizontal period by a data transfer pulse (105) during horizontal blanking, and the same processing as the drive circuit block proposed in Fig. 3 is performed. Ru. And PWM converter (
The output of 107) is led to the conductive plate of the beam flow control electrode through the output part (108). Here, LH memory (10
3) (106), the pwM conversion section (107) is incorporated into the small signal logic section IC (110), and the output section (10
8) are respectively incorporated in the output section IC (111), and the respective ICs (110) and (111) drive the drive IC (1
12) as an IIC configuration. This drive I
Since the number of outputs of C (112) is 23, in reality, in a 10 inch size image display device with 184 outputs, this drive IC (1
12) will be used in 8 pieces.

Effects of the Invention The present invention can improve the drive IC by changing the design of the electrodes, reduce costs by adopting an IIC configuration, and reduce input between conventional ICs (small signal block and output section). There are significant effects such as cost reduction in terms of mounting by eliminating the complexity of output wiring, and the IIC configuration reduces the mounting area, saving space and cost of the drive circuit block.

[Brief explanation of the drawing]

FIG. 1 is a drive circuit block II showing an embodiment of the present invention.
C configuration diagram, FIGS. 2A and 2B are diagrams illustrating changes in electrode design between the present invention and the conventional example, and FIG. 3 is a diagram showing the basic electrode configuration of an image display device to which the present invention is applied. Fig. 4 is a diagram showing the minimum unit configuration of this image display device on the screen, Fig. 5 is a block diagram of the drive circuit and waveform diagrams of each part in the device, and Fig. 6 is a diagram showing the vertical deflection voltage and horizontal synchronizing signal. Correlation diagram. Fig. 7 is a diagram showing various timing charts, Fig. 8 is a diagram showing the relationship between cathode drive pulses, vertical deflection signals, and horizontal deflection signals;
FIG. 9 is a correlation diagram between the horizontal deflection voltage and the horizontal synchronization signal. (2) (2a) to (2o)... line cathode, (3)...
・Vertical focusing electrode, (4)...Vertical deflection electrode, (5)・
... Beam flow control electrode, (6) ... Horizontal focusing electrode, (
7)...Horizontal deflection electrode, (8)...Beam acceleration electrode, (9)...Screen, (20)...phosphor, (
110)...Small signal logic section IC, (111)
...Output part IC, (112)...Drive IC Agent Yoshihiro Morimoto Figure 1tto-, HA9a5-'vriuIC l〃・8. Firepower #IC1 ff2-11 Lee 117Ic Fig. 2 tA) (β) Fig. 4 Nagate Riko/11 Hisuke Fig. 7 (a) (Me' Fig. q)

Claims (1)

[Claims] 1. A screen coated with a phosphor that emits light when irradiated with an electron beam; an electron beam source that generates an electron beam for each vertical section of the screen divided into a plurality of vertical sections; separation means for dividing the electron beam generated by the electron beam source into a plurality of horizontal sections and irradiating the separated beam onto the screen; A beam flow that controls the amount of light emitted from each pixel on the screen by controlling the amount of the electron beam irradiated onto the screen with a deflection electrode that deflects in a plurality of steps in the horizontal direction, and the electron beam separated for each horizontal section. A control electrode, a focusing electrode that controls the size of light emitted by the electron beam on the phosphor surface in each pixel, a back electrode that controls the amount of electron beam from the electron beam source, and a focusing electrode that controls the electron beam up to the screen. It is equipped with a beam accelerating electrode for accelerated irradiation, and the distance from the horizontal focusing electrode to the beam accelerating electrode, which is a high voltage electrode, and the screen surface is configured to be longer than the conventional distance, and the peak value of the signal applied to the beam flow control electrode is reduced. An image display device configured to be driven.