JPS6238086A - Picture display device - Google Patents

Abstract

PURPOSE:To always obtain the display output which is not noisy and stable by applying the switch group to the sample holding circuit and changing over the switch group according to the case whether the picture display device input is a television signal or a component signal such as a personal computer (PC). CONSTITUTION:A switch group 50 is composed of, for example, an analog gate 51. For a control terminal 52, at the time of the television signal input, an L level is added, and at the time of the component signal input such as a personal computer (PC), an H level is added. When PC is connected, sampling pulses R11 and R12 impressed to the R latch of a sample holding circuit 31-1 are impressed to other G and B latches of the sample holding circuit 31-1 by the analog gate 51 of the switch group 50.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention generates an electron beam for each division when a screen on a screen is vertically divided into a plurality of divisions, and generates an electron beam for each division. The present invention relates to an apparatus for displaying a plurality of lines by vertically deflecting a beam to display a television image as a whole.

Conventional technology Traditionally, cathode ray tubes have been mainly used as display elements for displaying color television images, but conventional cathode ray tubes have a very long depth compared to the screen size, making it difficult to use in thin television receivers. It was impossible to create. In addition, although EL display elements, plasma display devices, liquid crystal display elements, etc. have recently been developed as flat display elements, all of them are insufficient in terms of performance such as brightness, contrast, and color display, and have not been put into practical use. It has not yet been reached.

Therefore, the present applicant proposed a new display device in Japanese Patent Application No. 56-20618 (Japanese Unexamined Patent Publication No. 57-135590) to achieve a flat display device using electron beams.

This method generates an electron beam for each section when the screen is vertically divided into multiple sections, and displays multiple lines by deflecting each electron beam vertically for each section. death.

It displays a television image as a whole.

First, a basic configuration of the image display element used here will be explained with reference to FIG. 4. This display element consists of, in order from the back to the front, a back electrode (1), a line cathode (2) as a beam source, vertical focusing electrodes (3) (3'), a vertical deflection electrode (4), and a beam flow control Electrode (5), horizontal focusing electrode (
6) It consists of a horizontal deflection electrode (7), a beam acceleration type Vi (8), and a screen (9), which are housed inside a flat glass bulb (not shown) that is evacuated. has been done. Line cathode (2
) is stretched horizontally so as to generate an electron beam distributed linearly in the horizontal direction, and a plurality of such linear cathodes (2) are vertically spaced at appropriate intervals ((2a) to (2a) in the figure).
(Only the four shown in (2d)) are provided. In this example, it is assumed that there are 15 set numbers. Those(
2a) to (20). These wire cathodes (2) are constructed by coating the surface of a tungsten wire with a diameter of 10 to 20 μΦ with an oxide cathode material for thermionic emission. These line cathodes (2a) to (2o) are heated so as to generate a thermionic beam by passing an electric current through them, and as described later, the line cathodes (2a) to (2o) are heated sequentially for a certain period of time. It is controlled to emit an electron beam at a time. The back electrode (1) suppresses the generation of electron beams from other line cathodes other than the line cathode that is controlled to emit electron beams for a certain period of time, and directs the generated electron beams only in the forward direction. It has the effect of pushing out. This back electrode (
1) may be formed by a coating of electrically conductive material applied to the inner surface of the rear wall of the glass bulb. Furthermore, a one-plane electron beam emitting cathode may be used instead of the back electrode (1) and the line cathode (2).

The vertical focusing electrode (3) is a conductive plate (11) having a horizontally long slit (10) facing each of the line cathodes (2a) to (2o), and collects the electron beam emitted from the line cathode (2). taken out through the slit (10),
and vertically focused. 1 horizontal line (3
60 pixels worth of electron beams are taken out at the same time. In the diagram,
Of these, only one section in the horizontal direction is shown.

The slits (10) may be provided with crosspieces at appropriate intervals in the middle, or may be a row of through holes provided in large number at small intervals in the horizontal direction (intervals that are almost touching). It may be configured substantially as a slit. The vertical focusing electrode (3') is also similar.

A plurality of vertical deflection electrodes (4) are arranged horizontally at intermediate positions between the slits (10),
Conductors (
i3) (1,3') is provided. And opposing conductors (13) (13')
A vertical deflection voltage is applied between them to deflect the electron beam in the vertical direction. In this example, a pair of conductors (13) (
13') deflects the electron beam from one line cathode (2) vertically to positions corresponding to 16 lines.

The 16 vertical deflection electrodes (4) constitute 15 conductor pairs corresponding to each of the 15 line cathodes (2), so that 240 horizontal lines are drawn on the screen (9). Deflect the electron beam to

Next, the control electrodes (5) are composed of conductive plates (15) each having a vertically long line (14), and a plurality of control electrodes (5) are arranged in parallel in the horizontal direction at a predetermined interval. In this example, 180 control electrode conductive plates (15-1
) to (15-port) are provided. (Only 9 lines are shown in the figure). Each of the control electrodes (5) separates and extracts the electron beam into two picture elements in the horizontal direction, and controls the amount of electron beam passing therethrough in accordance with a video signal for displaying each picture element. Therefore, if 180 conductive plates (15-1) to (15-n) for control electrodes (5) are provided, one horizontal
360 picture elements can be displayed per line. In addition, in order to display images in color, each picture element is R, G, B
Each control electrode (5)
has two picture elements of R and G.

Each video signal of B is added sequentially. In addition, 180 pairs of video signals for one line (2 pixels per pair) are simultaneously applied to each of the 180 conductive plates (15-1) to (15-n) for control electrodes (5). One line of video is displayed at one time.

The horizontal focusing electrode (6) is connected to the slit (14) of the control electrode (5).
) is composed of a conductive plate (17) having a plurality of vertically long slits (16) facing each other, and the electron beam for each pixel divided horizontally is transmitted horizontally. Focus into a narrow beam of electrons.

The horizontal deflection electrode (7) is composed of a plurality of conductive plates (18) (18') arranged vertically on both sides of the slit (16), and each electrode (18) ( 18') is applied with six levels of horizontal deflection voltage to deflect the electron beam of each picture element in the horizontal direction, so that two sets of R and G are displayed on the screen (9).

Each phosphor of B is sequentially irradiated to emit light. In this embodiment, the deflection range is two picture elements wide for each electron beam.

The accelerating electrode (8) is composed of a plurality of conductive plates (19) installed horizontally in the same position as the vertical deflection electrode (4), and it directs the electron beam to the screen (9) with sufficient energy. Accelerate to cause a collision.

The screen (9) is constructed by applying a phosphor (20) that emits light when irradiated with an electron beam to the back surface of a glass plate (2), and adding a metal back layer (not shown). The phosphor (20) has two phosphors of three colors R2O and B for one slit (14) of the control electrode (5), that is, for each one electron beam divided in the horizontal direction. They are provided in pairs.

It is applied in vertical stripes. In Figure 4, the broken lines drawn on the screen (9) indicate multiple J! A vertical division is shown corresponding to each of the line cathodes 2), and a two-dot chain line is a horizontal division displayed corresponding to each of a plurality of control electrodes (5). As shown in the enlarged view in Figure 5, one section partitioned by these two has R, G, and B phosphors (20) for two picture elements in the horizontal direction, and 16 lines in the vertical direction. It has a width of 30 minutes. The size of one section is, for example, Im in the horizontal direction and 9 mm in the vertical direction.

Note that in FIG. 4, the length in the horizontal direction is greatly expanded relative to the length in the vertical direction for clarity.

In addition, in this example, two R, G, and B phosphors (20) are used for one control electrode (5), that is, one electron beam.
Although only one pair of picture elements is provided, of course, one picture element or three or more picture elements may be provided, and in that case, the control electrode (5) has one picture element or three or more picture elements. R, G, and B video signals are sequentially applied for the purpose, and horizontal deflection is performed in synchronization with the R, G, and B video signals.

Next, the basic configuration and waveforms of each part of a drive circuit for displaying television images on this display element will be explained with reference to FIG. First, a driving portion for irradiating the screen (9) with an electron beam to emit raster light will be explained.

The power supply circuit (22) is a circuit for applying a predetermined bias voltage (operating voltage) to each electrode of the display element.

The back electrode (1) has −■□, the vertical focusing electrode (3) (3
) for V, y, p, horizontal focusing electrode (6) for V,
, V8 for the accelerating electrode (8), V for the screen (9),
Apply a DC voltage of

Next, a composite video signal of a television signal is applied to the input terminal (23), and a vertical synchronization signal V and a horizontal synchronization signal H are separated and extracted in a synchronization separation circuit (24).

The vertical deflection drive circuit (40) includes a vertical deflection counter (2
5), a memory for vertical deflection signal storage (27), and a digital-to-analog converter (39) (hereinafter referred to as a DA converter). As input pulses to the vertical deflection drive circuit (40), a vertical synchronizing signal V and a horizontal synchronizing signal H shown in FIG. 7 are used. Vertical deflection counter (25) (
8 bits) are reset by the vertical synchronizing signal V and counting the horizontal synchronizing signal H.

This vertical deflection counter (25) counts the effective scanning period (in this case, a period of 240H) excluding the vertical blanking period of the vertical period, and this count output is supplied to the address of the memory (27). be done. The memory (27) outputs vertical deflection signal data (here, 8 bits) corresponding to each address, and the D-A converter (39) outputs the data of the vertical deflection signal corresponding to each address.
It is converted into vertical deflection signals of υ and υ' as shown in the figure (Fig. 6(b) D > By storing regular data in the memory, 16 levels of vertical deflection signals can be obtained.

On the other hand, the line cathode drive circuit (26) uses the vertical synchronization signal V and the output of the vertical deflection counter (25) to create a line cathode drive pulse a'=o. FIG. 8(a) shows the vertical synchronizing signal V, the horizontal synchronizing signal H, and the vertical deflection counter (25
) shows the relationship between the lower 5 bits. FIG. 8(b) shows line cathode drive pulses a' to 0 every 16H using these signals.
We will show you how to make ′. In FIG. 8, LSB indicates the lowest bit, and (LSB+1) means the bit one higher than the LSB.

The first line cathode drive pulse a'' can be created by an R-S flip-flop using the vertical synchronization signal V and the output (LSB+4) of the vertical deflection counter (25), and the line cathode drive pulse b'~0 ′ uses a shift register,
This can be obtained by transferring the line cathode drive pulse a' using the inverted version of the output (LSB+3) of the vertical deflection counter (25) as a clock. This drive pulse a'
~0' is inverted and converted into a line cathode drive pulse a~0 which is set to a low potential only during each pulse period and set to a high potential of approximately 20 volts during other periods (Fig. 6(b)E). , are added to each line cathode (2a) to (2o).

Each line cathode (2a) to (2o) is heated by passing a current during the high potential period of the drive pulses a to 0, and is heated so that it can emit electrons during the low potential period of the drive pulse ao. State is preserved. As a result, 15 wire cathodes (2a)
From ~(2o), low potential drive pulses a~0 are respectively applied.
Electrons are emitted only during the 16H period when . During periods when a high potential is applied, the line cathode (2a ) to (20) is more positive, so no electrons are emitted from the line cathodes (2a) to (2o). Thus, in the line cathode (2), electrons are sequentially emitted from the upper line cathode (2a) to the lower line cathode (2o) for each 16H period during the effective vertical scanning period. The emitted electrons are pushed forward by the back electrode (1), pass through the opposing slits (10) of the vertical focusing electrode (3), and are focused in the vertical direction to form a flat electron beam. .

Next, line cathode drive pulses a~0 and vertical deflection signals υ, υ′
The relationship will be explained using FIG. 9. Figure 9 (
6. The vertical deflection signal υ in FIG. 9(b) is a waveform diagram of the linear cathode drive pulse, (b) a waveform diagram of the vertical deflection signal, and (c) a waveform diagram of the horizontal deflection signal.

υ' changes by IH in 16 steps during the 16H period of each line cathode pulse a-o in FIG. 9(,).

Both vertical deflection signals υ and υ' have a center voltage of v4, and υ increases sequentially and υ' decreases sequentially.
They are designed to change in opposite directions. These vertical deflection signals υ and υ' are applied to the electrodes (13) and (13') of the vertical deflection electrode (4), respectively, resulting in the electron beams generated from the respective line cathodes (2a) to (20). is vertically deflected in 16 steps, and as mentioned earlier, on the screen (9), one electron beam is deflected so that a raster of 16 lines is drawn sequentially one line at a time from the top.

As a result of the above, electron beams are emitted from the 15 line cathodes (2a) to (20) sequentially for a period of 16H starting from the top, and each electron beam is sequentially emitted one line from top to bottom within 15 sections in the vertical direction. On the screen (9), from the first line at the top to the 24th line at the bottom.
The electron beam is vertically deflected one line at a time up to the 0th line, and a total of 240 raster lines are drawn.

The vertically deflected electron beam is sent to the control electrode (5).
It is divided into 180 sections in the horizontal direction by a horizontal focusing electrode (6) and taken out. In Figure 5, one of them
The classification is shown. The amount of this electron beam passing through each section is controlled by a control electrode (5), and is focused horizontally by a horizontal focusing electrode (6) into a single narrow electron beam. The light is deflected in six steps in the direction and sequentially irradiates each R2G and B phosphor (20) of two picture elements on the screen (9). FIG. 5 shows the vertical and horizontal divisions. The phosphors corresponding to (15-1) to (15-n) of the control electrode (5) are R, G, and B for two picture elements, but for convenience of explanation, one picture element is R□, G□. , B, and the other R2, G2 .
B.

shall be.

Next, the horizontal deflection drive circuit (41) is composed of a horizontal deflection counter (28) (11 bits), a memory (29) that stores horizontal deflection signals, and a DA converter (38). . The input pulses of the horizontal deflection drive circuit (41) are a vertical synchronizing signal V and a horizontal synchronizing signal H as shown in FIG.
A pulse 6H with a repetition frequency six times that of the horizontal synchronizing signal H is used. The horizontal deflection counter (28) is reset by the vertical synchronizing signal V and receives the horizontal six times the pulse 6.
Count H. This horizontal deflection counter (28) is applied 6 times during IH and 240Hx 6/H= during 1V.
It counts 1440 times, and this count output is stored in the memory (2
9) is supplied to the address.

The memory (29) outputs horizontal deflection signal data (8 bits in this case) according to the address, and the D-A converter (38) converts it as shown in Figure 10 (Figure 6(b)C). ,
It is converted into a horizontal deflection signal such as h'. This circuit has memory addresses for storing horizontal deflection signals corresponding to each of 6 x 240 lines.

By storing six pieces of regular data in the memory for each line, a six-step wave horizontal deflection signal can be obtained during the IH period.

As shown in Fig. 10, this horizontal deflection signal is a pair of horizontal deflection signals ri and h' that change in 6 steps, both of which have a center voltage of v7, where h decreases sequentially and h' increases sequentially. They change in opposite directions as they move forward. These horizontal deflection signals, h' are the electrodes (
18) and (18'). As a result, each horizontally segmented electron beam is applied to the R, G of the screen (9) during each horizontal period.

B, R, G, B (R4, G1. B1. R,, a,, B
The light is horizontally deflected so that the phosphor of 2) is sequentially irradiated for H/6 periods. Thus, in each line raster, the electron beam is R1' for each of the 180 horizontal sections.
G1. B engineering, R2, G2. Each phosphor (20) of B2 is sequentially irradiated.

Therefore, the electron beams are set to R, , G for each horizontal section of each line.
1. B Eng., R., G2. By modulating with the B2 video signal, a color television image can be displayed on the screen (9).

Next, the modulation control portion of the electron beam will be explained. First, the composite video signal applied to the television signal input terminal (23) is applied to the color demodulation circuit (30), where the R-Y and B-Y color difference signals are demodulated and the G-Y color difference signal is demodulated. The signals are matrix-synthesized, and further, they are combined with the luminance signal Y to form each primary color signal of R2O and B (hereinafter R,
G, B video signals) are output. Those R,G
, B. Each video signal is processed by 180 sample and hold circuits (3
1-1) to (31-n). Each sample hold circuit (31-1) to (31-n) is for R1, G, B1, and R2, respectively.

It has six sample and hold circuits for G2 and B2. These sample and hold outputs are respectively applied to holding memories (32-1) to (32-n).

On the other hand, the reference clock oscillator (33) is composed of a PLL (phase-locked loop) circuit, etc., and in this example, the reference clock 6fsc is six times the color subcarrier fsc.
and a double reference clock 2fsc is generated. The reference clock is controlled to always have a constant phase with respect to the horizontal synchronizing signal H.

The reference clock 2%sc is the deflection pulse generation circuit (42)
signals 6H and H/6, which are six times the horizontal synchronization signal H.
Signal switching pulse r□* gi+ b1+ rz+
Pulses of gz and bz (Fig. 6(b)B) are obtained. On the other hand, the reference clock 6fsc is applied to the sampling pulse generation circuit (34), where it is delayed by one clock period by a shift register, so that the horizontal period (63
, 5μ5ec) of the effective horizontal scanning period (approximately 50μ5ec).
ec), 1080 sampling pulses R11,
G11. B11. RL2. G1□, B1□, R21
,G,.

B, 1. R, 2, G2□, B,, -Rn,, Gn
l, Bnl, Rn2゜On,, 13n2 (Fig. 6 (
b) A) are generated sequentially, followed by one transfer pulse t
is generated. This sampling pulse R1, ~Bn2
corresponds to each picture element when one line of the video to be displayed is divided into 360 picture elements in the horizontal direction, and its position is controlled to always be constant with respect to the horizontal synchronizing signal H.

These 1080 sampling pulses R1□ to Bn2 are connected to 180 sets of sample hold circuits (31, -1
) to (31-n), and thereby each sample-hold circuit (31-1) to (31-n)
When one line is divided into 180 parts, each 2
Picture element R□, G1. B1. R2, G2. Each B2 video signal is individually sampled and held. The 180 sample-held sets of R, G, B, and R
2°G2. The video signal of B is stored in 180 sets of memories (32-1) to (32
-n), are transferred all at once by a transfer pulse t, and are held here for the next horizontal period. This retained R-work.

G□, B engineering, R2, G2. The signal B is applied to switching circuits (35-1) to (35-n). Switching circuits (35-1) to (35-n) each have R1
It is constituted by a tri-state or analog gate having individual input terminals for PG1+B1rR, , G, , B and a common output terminal for sequentially switching and outputting them.

The output of each switching circuit (35-1) to (35-n) is 180 sets of pulse width modulation (PWM) circuit (37-1)
~(37-n), where the sample-held R1. G,, B engineering, R2,, G2. B2
The reference pulse signal is pulse width modulated according to the magnitude of the video signal and output. The repetition period of the reference pulse signal is the above signal switching pulse rx+ g, r b, r2
It is desirable that the pulse width is sufficiently smaller than the pulse width of ゜gz+bz, for example, 1:10 to 1:100.
The output of the pulse width modulation circuits (37-1) to (37-n) is used as a control signal for modulating the electron beam to the 180 conductive plates of the control electrode (5) of the display element. (15-])~
(15-n) respectively. The switching circuits (35-1) to (35-n) are simultaneously controlled by switching pulses rty glt blv rze gz+b2 applied from the switching pulse generating circuit (36). The switching pulse generation circuit (36) generates signal switching pulses rze gx, blv rze from the aforementioned deflection pulse generation circuit (42).
It is controlled by gz + bz, and each horizontal period is divided into 6, and the switching circuit (35-1) ~
Switch (35-n), R1, G work, B work t R2*
The switching signals rtpg and b are used to time-divide and sequentially output the respective video signals of Gzt B2 and supply them to the pulse width modulation circuits (37-1) to (37-n).

Generate rze g2* bz.

What should be noted here is that the switching circuit (35-
1) R1, G, B1. in ~(35-n).
The switching of the supply of video signals of R2°G, , B, and the horizontal deflection of the irradiation of the electron beams R1, Gi, B, R2°G, , B2 to the phosphors by the horizontal deflection drive circuit (41) are performed by: They are synchronously controlled to completely match both timing and order. This results in
When the electron beam is irradiating the R0 phosphor, the irradiation amount of the electron beam is controlled by the R1 video signal,
G□HB 1 p Rz p G21 B Z is similarly controlled, and R1, G1 . B1゜R2t G! , B The light emission of the two capacitive light bodies is controlled by the video signals of the picture element R, G1゜B□, R, , G, , B2, and each picture element emits light according to the input video signal. It will be displayed. Such control is 1
This is performed simultaneously for 180 lines (2 pixels each) to display an image of 360 pixels per line, and then sequentially for 240H lines starting from the upper line, displaying 1 line on the screen (9). Two images will be displayed.

The above operations are performed on one input television signal.
This is repeated for each field, and as a result, a moving television image is displayed on the screen (9) in the same way as a normal television receiver.

Figure 2 shows the sampling and hold circuit (314) in Figure 6.
This shows how sampling pulses R□ and -B-process 2 are sequentially applied. Here, GK indicates an original oscillation clock that generates sampling pulses input to the R latch group of the sample and hold circuits (31-1) to (31-n) at a frequency of 2 fsc.

Problems to be Solved by the Invention However, in the above configuration, the R, G, and B outputs of a personal computer (hereinafter abbreviated as PC), etc.
When a component signal is input to the image display device, the sampling pulse for latching the component signal has sampling pulse phases 11G+, 2 for G and B, and
, 2 are the sampling pulses R□1. The sampling points are located at points obtained by dividing the phase of the original oscillation clock GK, which generates R1, by 120 degrees, and the sampling points exist in time order.

For this reason, there was no problem when the R, G, and B data were used as image outputs (outputs obtained by demodulating composite video signals), but when R, G, and B data are used as component signals, such as in PCs,
, B are in phase, 1dle! ! If the sampling pulses for latching this data are input sequentially in time as described above, for example, in the example shown in Figure 3, the timing for latching data B is Since it is very close to the transition time of the B data, the latched value is not stable at H or L and becomes unstable. Therefore, the signal output corresponding to the latch data becomes unstable, resulting in a very noisy display. The present invention solves the above problem, and when the signal input of the image display device is a component signal such as a PC, the sampling pulse phase for R, G, and B is adjusted to the phase of the input. It is an object of the present invention to provide an image display device that can latch accurate and stable data and obtain a stable and noise-free display on a single image display surface.

Means for Solving the Problems In order to solve the above problems, the present invention provides a method in which, when a television (video) signal or a component signal such as a PC signal is input, in response to this, The sampling pulse applied to the sample hold circuit is
A group of switches is used to switch between sequential sampling pulses when the television signal is input as in the past, or simultaneous phase using one of the sampling pulses applied to the sample and hold circuit as the overall sampling pulse. It is something.

According to the above-described structure, the switch group is switched depending on whether the input to the image display device is a television signal or a component signal from a PC, etc., so that the phase of the input data and the sampling pulse always correspond correctly. Stable, noise-free data is latched into the sample-and-hold circuit, and a signal corresponding to this data becomes a stable output on the display screen.

Example An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of main parts showing one embodiment of the present invention. In FIG. 1, 34 is a sampling pulse generation circuit, and (31-1) to (31-n) are sample and hold circuits, which are the same as those in FIG.

(50) is a switch group, for example an analog gate (51)
It consists of (52) is a control terminal to which an L level is applied when a television signal is input, and an H level is applied when a component signal such as a PC is input. Any method may be used for this purpose, as long as it can provide L and H levels corresponding to the above example. In this example, once the PC is connected.

The sampling pulses R1i and R□2 applied to the R latch of the sampling and holding circuit (31-1) are applied to the other G and B of the sample and holding circuit (31-1) by the analog gate (51) of the switch group (50). The voltage is applied to the latch.

Figure 3 G-work 1. In B2□, the pulse indicated by the broken line indicates the sampling pulse when the PC is connected as described above. As a result, R,G.

It can be seen that the B component signal is stably sampled and latched.

In this way, in this example, the instability of the B data is completely eliminated, and a stable display output without noise can be obtained on the display screen.

Effects of the Invention According to the present invention, by simply adding a switch group to the sample and hold circuit and switching the switch group depending on whether the input to the image display device is a television signal or a component signal from a PC or the like, No matter what the image display device input is, a sampling pulse that is in phase with the input data can be applied to the sampling and hold circuit, and stable and noise-free data can always be latched. A stable display output without noise can always be obtained on the screen.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the sequentiality of sampling pulses, FIG. 3 is a diagram explaining the phase relationship between sampling pulses and input data, and FIG. 5 is a diagram showing the basic electrode configuration of an image display device to which the present invention is applied, FIG. 5 is a diagram showing the minimum unit configuration of the image display device on a screen, and FIG. 6 is a block diagram of a drive circuit in the device. and waveform diagrams, Figure 7 shows the correlation between vertical deflection voltage and horizontal synchronizing signal, Figure 8 shows various timing charts, and Figure 9 shows the relationship between cathode drive pulse, vertical deflection signal, and horizontal deflection signal. 10 are diagrams showing the correlation between the horizontal deflection voltage and the horizontal synchronization signal. (2) (2a) to (20)... line cathode, (3) (
3) '... Vertical focusing electrode, (4)... Vertical deflection electrode, (5)... Beam flow control electrode, (7)... Horizontal deflection electrode, (9)... Screen, (2o) ...phosphor, (34) ... sampling pulse generation circuit, (31
-1) to (31-n)...Sample and hold circuit group,
(50)... Switch group, (51)... Analog gate agent Yoshihiro Morimoto Figure 1 Figure 2 k -B/2 = ! = `` Suehira force direction qlQ minute Fig. 4 (let) Cp Fig. 7 me-11 1, 1 Fig. 1 ta) ζ no e'

Claims (1)

[Claims] 1. An electron beam generation source, a screen having a phosphor that emits light when irradiated with the electron beam, a focusing electrode that focuses the electron beam generated by the electron beam generation source, and a screen that focuses the electron beam on the screen. The screen is equipped with an electrostatic deflection electrode that deflects the electron beam between the screen and a control electrode that controls the emission intensity by controlling the amount of the electron beam irradiated onto the screen, and corresponds to one pixel in the horizontal direction. Each primary color signal demodulated in color is sampled sequentially in time and applied to the control electrode.
An image display device provided with means for switching to a simultaneous sampling pulse when a component signal of the component signal is inputted.