JPS6190593A - Picture display device - Google Patents

Abstract

PURPOSE:To execute a dot matrix system picture display in which a pulse signal with minimum unit width completely corresponds to one picture element on the screen by sampling rectangular pulse-shaped chrominance components outputted from a computer, etc., with a sampling pulse which synchronizes with the chrominance components in a phase manner. CONSTITUTION:In addition to a conventional video signal input terminal 23, R, G and B component signal input terminals 43a-43c, an input terminal 44 of an oscillating clock signal CK generating a component signal of a computer, etc., and input terminals 45 and 46 of horizontal and vertical synchronizing signals H' and V' used for a computer, etc., are installed. R, G and B component signals are directly inputted to sample and hold circuits 31-1-31-n by a change- over switch 47. On the other hand, an oscillating clock signal CK is inputted so as to change over a conventional fsc to a reference clock oscillating device 33 of a picture display device. Thus, a sampling pulse generated at a sampling pulse generating circuit 34 locks with the R, G and B component signals in a phase manner.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention generates an electron beam for each division when a screen on a screen is vertically divided into a plurality of divisions, and generates an electron beam for each division. The present invention relates to an apparatus for displaying a plurality of lines by vertically deflecting a beam to display a television image as a whole.

Conventional configurations and their problems Traditionally, cathode ray tubes have been mainly used as display elements for displaying color television images, but conventional cathode ray tubes are extremely long and thin compared to the screen size. It was impossible to create a television receiver for Furthermore, as flat display elements, EL display elements, plasma display devices, liquid crystal display elements, etc. have recently been developed.

All of them are insufficient in terms of performance such as brightness, contrast, and color display, and have not yet been put into practical use.

Therefore, we aimed to achieve a flat display device using electron beams, and when the screen on the screen is vertically divided into multiple sections, an electron beam is generated for each section. It was invented to display a plurality of lines by vertically deflecting each electron beam to display a television image as a whole.

First, a basic configuration of the image display element used here will be explained with reference to FIG. This display element includes, in order from the back to the front, a back electrode (1).

Line cathode (2) as beam source, vertical focusing electrode (3) (
3'), vertical deflection electrode (4), beam flow control electrode (5)
.

It consists of a horizontal focusing electrode (6), a horizontal deflection electrode (7), a beam accelerating electrode (8), and a screen (9), which are placed in the vacuum of a flat glass bulb (not shown). It is stored inside. A line cathode (2) serving as a beam source is stretched horizontally so as to generate an electron beam distributed linearly in the horizontal direction, and a plurality of line cathodes (2) are arranged vertically at appropriate intervals. Books (only four books (2a) to (2d) are shown in the figure) are provided. In this example, it is assumed that 15 are provided.

Let them be (2a) to (20). These line cathodes (
2) is constructed by coating the surface of a tungsten wire with a diameter of 10 to 20 .mu.φ with an oxide cathode material for thermionic emission. These line cathodes (2a) to (20) are heated so as to generate a thermionic beam when a current is passed through them, and as described later, the line cathodes (20)
The electron beams are controlled to be emitted sequentially from 2a) for a fixed period of time. The back electrode (1) suppresses the generation of electron beams from other line cathodes other than the line cathode that is controlled to emit electron beams for a certain period of time, and directs the generated electron beams only in the forward direction. It has the effect of pushing out. This back electrode (1) may be formed by a coating of electrically conductive material adhered to the inner surface of the rear wall of the glass bulb, and instead of these back electrode (1) and line cathode (2),
A planar electron beam emitting cathode may also be used.

The vertical focusing electrode (3) is a conductive plate (11) having a horizontally long slit (10) facing each of the line cathodes (2a) to (20), and collects the electron beam emitted from the line cathode (2). is taken out through the slit (lO),
and vertically focused. 1 horizontal line (3
60 pixels worth of electron beams are taken out at the same time. In the diagram,
Of these, only one section in the horizontal direction is shown.

The slit (10)' may be provided with crosspieces at appropriate intervals in the middle, or a row of through holes provided in large numbers at small intervals in the horizontal direction (intervals that are almost touching). The same applies to the vertical focusing electrode (3'), which may be configured substantially as a slit.

A plurality of vertical deflection electrodes (4) are arranged horizontally at intermediate positions between the slits (io),
Conductors (
13) (13') is provided. Then, a vertical deflection voltage is applied between the opposing conductors (13) (i3') to deflect the electron beam in the vertical direction. In this example, a pair of conductors (13) (
13') deflects the electron beam from one line cathode (2) vertically to positions corresponding to 16 lines. And 15 line cathodes (
Fifteen conductor pairs corresponding to each of 2) are constructed, and the electron beam is ultimately deflected to draw 240 horizontal lines on the screen (9).

Next, the control electrodes (5) are composed of conductive plates (15) each having a long slit (14) in the vertical direction, and a plurality of control electrodes (5) are arranged in parallel in the horizontal direction at a predetermined interval.

In this example, 180 control electrode conductive plates (15-1
) to (15-n) are provided. (Only nine electrodes are shown in the figure.) Each of these control electrodes (5) divides the electron beam into two picture elements in the horizontal direction and extracts it, and displays the amount of electron beam passing through each picture element. control according to the video signal. Therefore, if 18080 conductive plates (15-1) to (15-n) for control electrodes (5) are installed, one horizontal
360 picture elements can be displayed per line. In addition, in order to display images in color, each picture element is R, G, B
Each control electrode (5)
RlG and B video signals for two picture elements are sequentially added to the . In addition, 180 control electrodes (5) conductive plates (15-
1) Each of ~(15-n) has 18 for one line.
0 sets (2 picture elements per set) of video signals are applied at the same time, and one line of video is displayed at one time.

The horizontal focusing electrode (6) is connected to the slit (14) of the control electrode (5).
) is composed of a conductive plate (17) having a plurality of vertically long slits (16) facing each other, and the electron beam for each pixel divided horizontally is transmitted horizontally. Focus into a narrow beam of electrons.

The horizontal deflection electrode (7) is composed of a plurality of conductive plates (18) (18') arranged vertically on both sides of the slit (16), each of which has nine electrodes (18'). ) Six levels of horizontal deflection voltage are applied to (18') to deflect the electron beam for each picture element in the horizontal direction, so that two sets of R and G are displayed on the screen (9).

Each phosphor of B is sequentially irradiated to emit light. In this example, the deflection range is two picture elements wide for each electron beam.

The accelerating electrode (8) is composed of a plurality of conductive plates (19) installed horizontally in the same position as the vertical deflection electrode (4), and it directs the electron beam to the screen (9) with sufficient energy. Accelerate to cause a collision.

The screen (9) is constructed by applying a phosphor (20) that emits light when irradiated with an electron beam to the back surface of a glass plate (21), and adding a metal back layer (not shown). The phosphor (20) has two phosphors of three colors R2O and B for one slit (14) of the control electrode (5), that is, for each one electron beam divided in the horizontal direction. They are provided in pairs.

It is applied in vertical stripes. In Figure 1, the broken lines drawn on the screen (9) represent multiple wire cathodes (2
), and the two-dot chain line indicates a horizontal division displayed corresponding to each of the plurality of control electrodes (5). As shown in the enlarged view in Figure 2, one section partitioned by these two has R, G, and B phosphors for two picture elements in the horizontal direction (
20), and has a width of 16 lines in the vertical direction. The size of one section is, for example,
The horizontal direction is 1 m, and the vertical direction is 10+ nm.

Note that in FIG. 1, the length in the horizontal direction is greatly enlarged relative to the length in the vertical direction for clarity.

In addition, in this example, two R, G, and B phosphors (20) are used for one control electrode (5), that is, one electron beam.
Although only one pair of picture elements is provided, of course, one picture element or three or more picture elements may be provided, and in that case, the control electrode (5) has one picture element or three or more picture elements. R, G, and B video signals are sequentially applied for the purpose, and horizontal deflection is performed in synchronization with the R, G, and B video signals.

Next, the basic configuration and waveforms of each part of a drive circuit for displaying television images on this display element will be explained with reference to FIG. First, a driving portion for irradiating the screen (9) with an electron beam to emit raster light will be described.

The power supply circuit (22) is a circuit for applying a predetermined bias voltage (operating voltage) to each electrode of the display element.
1) -v1. Vertical focusing electrode (3) (3″) has V
A DC voltage of B2 V3', VG is applied to the horizontal focusing electrode (6), V6 is applied to the acceleration electrode (8), and V is applied to the screen (9).

Next, a composite video signal of a television signal is applied to the input terminal (23), and a vertical synchronization signal V and a horizontal synchronization signal H are separated and extracted in a synchronization separation circuit (24).

The vertical deflection drive circuit (40) includes a vertical deflection counter (2
5), a memory for vertical deflection signal storage (27), and a digital-to-analog converter (39) (hereinafter referred to as a DA converter). As input pulses to the vertical deflection drive circuit (40), a vertical synchronizing signal V and a horizontal synchronizing signal H shown in FIG. 4 are used. Vertical deflection counter (25) (
8 bits) are reset by the vertical synchronizing signal V and counting the horizontal synchronizing signal H.

This vertical deflection counter (25) counts the effective scanning period (in this case, a period of 240H) excluding the vertical blanking period of the vertical period, and this count output is supplied to the address of the memory (27). be done. The memory (27) outputs vertical deflection signal data (here, 8 bits) corresponding to each address, and the D-A converter (39) outputs the data of the vertical deflection signal corresponding to each address.
It is converted into vertical deflection signals of υ and υ' shown in the figure (Fig. 3(b) D). This circuit has a memory address for storing vertical deflection signals corresponding to each line for 240H, and by storing regular data in the memory every 16H, a 16-step basic deflection signal is obtained. be able to.

On the other hand, the line cathode drive circuit (26) uses the vertical synchronization signal V and the output of the vertical deflection counter (25) to create line cathode drive pulses a to 0. FIG. 5(a) shows the vertical synchronization signal V,
FIG. 5(b), which shows the relationship between the horizontal synchronizing signal H and the lower 5 bits of the vertical deflection counter (25), shows a method of creating line cathode drive pulses a' to 0' every 16H using these signals. In FIG. 5, LSB indicates the lowest bit, and (LSB+1) means the bit one higher than the LSB.

The first line cathode drive pulse a' can be created by an R-S flip-flop using the vertical synchronization signal V and the output (LSB+4) of the vertical deflection counter (25), and the line cathode drive pulse b'~0 ′ uses a shift register,
This can be obtained by transferring the line cathode drive pulse a' using the inverted version of the output (LSB+3) of the vertical deflection counter (25) as a clock. This drive pulse a'
~oI is inverted and converted into a line cathode driving pulse a-o which is set to a low potential only during each pulse period and set to a high potential of about 20 volts during other periods (Fig. 3(b)E), It is added to each line cathode (2a) to (2o).

Each line cathode (2a) to (2o) is heated by passing a current during the high potential period of the drive pulse a-o, and is heated so that it can emit electrons during the low potential period of the drive pulse a''o. state is maintained.This allows 15 line cathodes (2
From a) to (2o), a low potential drive pulse a is applied to each of a) to (2o).
'= Electrons are emitted only during the 16H period when o is added. During the period when a high potential is applied, the back electrode (1
) and the vertical focusing electrode (3) at the position of the line cathode (2) determined by the bias voltage applied to the line cathode (2a) to (2o). To make it positive, connect the wire to the cathode (2
No electrons are emitted from a) to (20), thus
In the line cathode (2), electrons are sequentially emitted from the upper line cathode (2a) to the lower line cathode (2o) for each 16H period during the effective honest scanning period. The emitted electrons are pushed forward by the back electrode (1), pass through the opposing slits (lO) of the vertical focusing electrode (3), and are focused in the vertical direction to form a flat electron beam. .

Next, the line cathode drive pulse a-o and the vertical deflection signals υ, υ′
The relationship between the two will be explained using FIG. Figure 6 (
, ) is a waveform diagram of a line cathode driving pulse, -(b) is a waveform diagram of a vertical deflection signal, and (e) is a waveform diagram of a horizontal deflection signal.

Vertical deflection signal υ in FIG. 6(b).

υ' changes by IH in 16 steps during the 16H period of each line cathode pulse a to 0 in FIG. 6(a).

Both vertical deflection signals υ and υ' have a center voltage of v4, and υ increases sequentially and υ' decreases sequentially.
They are designed to change in opposite directions. These vertical deflection signals υ and υ' are applied to electrodes (13) and (13'') of the vertical deflection electrode (4), respectively.

As a result, the electron beams generated from each of the line cathodes (2a) to (20) are vertically deflected in 16 steps.
As mentioned above, one electron beam is deflected on the screen (9) so that a raster of 16 lines is drawn one line at a time from the top.

As a result of the above, electron beams are emitted sequentially from the top of the 15 line cathodes (2a) to (2o) for a period of 16H, and each electron beam is sequentially emitted in one line from top to bottom within 15 sections in the vertical direction. On the screen (9), from the first line at the top to the 24th line at the bottom.
The electron beam is vertically deflected one line at a time up to the 0th line, and a total of 240 raster lines are drawn.

The vertically deflected electron beam is connected to the control electrode (5).
It is divided into 180 sections in the horizontal direction by a horizontal focusing electrode (6) and taken out. In Figure 1, one of them
The classification is shown. The amount of electron beam passing through each section is controlled by a control electrode (5), and horizontally focused by a horizontal focusing electrode (6) to form a single narrow electron beam. The light is deflected in six steps and sequentially illuminates each of the R9G and B light bodies (20) corresponding to two picture elements on the screen (9). FIG. 2 shows the vertical and horizontal divisions. The phosphors corresponding to (15-1) to (15-n) of the control electrode (5) are R, G, and B for two picture elements, but for convenience of explanation, one picture element is R1, G, and B. B□ and the other one is R2, G2. B
Set it to 2.

Next, the horizontal deflection drive circuit (41) is composed of a horizontal deflection counter (28) (ll bits), a memory (29) that stores horizontal deflection signals, and a DA converter (38). . As shown in FIG. 7, the input pulses of the horizontal deflection drive circuit (41) are synchronized with the vertical synchronizing signal (2) and the horizontal synchronizing signal H, and a pulse 6H having a repetition frequency six times that of the horizontal synchronizing signal H is used. The horizontal deflection counter (28) is reset by the vertical synchronizing signal V and receives the horizontal six times the pulse 6H.
count. This horizontal deflection counter (28) is
6 times during H, 240H during 1v 6/H = 1
It counts 440 times, and this count output is stored in the memory (29
) is supplied to the address.

The memory (29) outputs horizontal deflection signal data (here, 8 bits) according to the address, and the data is sent to the D-A converter (38) as shown in Fig. 7 (Fig. 3 (b) C:). the law of nature,
It is converted into a horizontal deflection signal such as h'. This circuit has memory addresses for storing horizontal deflection signals corresponding to each of 6 x 240 lines, and by storing 6 pieces of regular data for each line in the memory, 6-step horizontal waves are generated during the IH period. A deflection signal can be obtained.

As shown in Figure 7, this horizontal deflection signal is a pair of horizontal deflection signals ri and h' that change in six steps, both of which have a center voltage of v7, with h decreasing sequentially and h' increasing sequentially. They change in opposite directions as they move forward. These horizontal deflection signals, h' are the electrodes (
18) and (18'). As a result, each horizontally segmented electron beam is applied to the R, G of the screen (9) during each horizontal period.

B, R, G, B (R,, G1.B,, R,, G2.B
, ) are horizontally deflected so that the phosphors are sequentially irradiated for H/6 periods. Thus, in each line raster, one electronic beam is generated for each of the 180 horizontal segments.
M is R engineering, G□, B1. Each phosphor (20) of R2, G, B2 is sequentially irradiated.

Therefore, for each horizontal section of each line, the electron beam is
□, B□+ R2, G2. By modulating with the B2 video signal, a color television image can be displayed on the screen (9).

Next, the modulation control portion of the electron beam will be explained. First, the composite video signal applied to the television signal input terminal (23) is applied to the color demodulation circuit (30), where the R-Y and B-Y color difference signals are demodulated and the G-Y color difference signal is demodulated. The signals are matrix-synthesized, and further, they are combined with the luminance signal Y to form each primary color signal R2O, H (hereinafter R,
G, B video signals) are output. Those R,G
,,B Each video signal is processed by 180 sample and hold circuits (
31-1) to (31-n). Each sample hold circuit (31-1) to (31-n) is R1
It has six sample and hold circuits: 1, G1, B, R2, G2, and B2. Those sample and hold outputs are stored in the holding memories (32-1) to (32-1), respectively.
2-n).

On the other hand, the reference clock oscillator (33) is composed of a PLL (phase-locked loop) circuit, etc., and in this embodiment, the reference clock 6f is six times as large as the color subcarrier fsc.
A reference clock 2fsc, which is double the reference clock 2fsc, is generated. The reference clock is controlled to always have a constant phase with respect to the horizontal synchronizing signal H. The reference clock 2fsc is added to the deflection pulse generation circuit (42), and a signal 6H which is six times the horizontal synchronizing signal H and a signal switching pulse r every H/6 are added to the deflection pulse generation circuit (42).
1p g engineering, bo.

A pulse of rz+gztt)z (Figure 3(b)B) is obtained.

On the other hand, the reference clock 6fsc is applied to the sampling pulse generation circuit (34), where the shift register
The horizontal period (6
The effective horizontal scanning period (approximately 50 μ
1080 sampling pulses R11 during 5ec)
, G engineering, + B 11 HR engineering 2. G1□, B12. R
,1,G2□1B211Rzze Gzzt B 22
~Rn1. Gn,, B nt+ Rn, l Gn
, +Bn2 (Figure 3(b) A) are generated sequentially,
After that, one transfer pulse t is generated. These sampling pulses R11 to Bn2 correspond to each picture element when one line of the video to be displayed is divided into 360 picture elements in the horizontal direction, and their positions are always constant with respect to the horizontal synchronizing signal H. controlled by.

These 1080 sampling pulses R11 to Bn each form 180 sets of sample hold circuits (31-1).
-(31-n), and as a result, each sample-hold circuit (31-1) to (31-n) has an R1 value of 2 pixels for each of 180 pixels divided into 1 line. , G1. B1. R2, G2. Each video signal of B is individually sampled and held. The sample held 180 pairs of R1, G□, B□,
R2°G2. The video signal of B2 is stored in 180 sets of memories (32-1) to (3
2-n), they are transferred all at once by a transfer pulse t, and are held here for the next horizontal period. This retained R1
゜G□, B1. R2, G2. The B2 signal is applied to switching circuits (35-1) to (35-n).

The switching circuits (35-1) to (35-n) are R, G, B, respectively.

It is composed of a tri-state or analog gate having individual input terminals for R, , G, , B and a common output terminal for sequentially switching and outputting them.

The output of each switching circuit (35-1) to (35-n) is 180 sets of pulse width modulation (pwM) circuit (37-1)
~(37-n), where the sample-held R, , G1 . B□, R, , G, , B, the reference pulse signal is pulse width modulated according to the magnitude of the video signal and output. The repetition period of the reference pulse signal is the above signal switching pulse rx+ git bzv rztgzm
It is desirable that the pulse width be sufficiently smaller than the pulse width of bz, and for example, a pulse width of about 1:10 to 1:100 is used.

The outputs of the pulse width modulation circuits (37-1) to (37-n) are used as control signals for modulating the electron beam to the 180 conductive plates (15-1) to the control electrodes (5) of the display element.
(15-n) respectively. The switching circuits (35-1) to (35-n) are simultaneously controlled by switching pulses rx*gttblerztgzebz applied from the switching pulse generating circuit (36). The switching pulse generation circuit (36) generates a signal switching pulse rz+gtt from the deflection pulse generation circuit (42) described above.
It is controlled by ble raw gze bz, and each horizontal period is divided into 6, and the switching circuits (35-1) to (35-n) are switched by H/6.

Each video signal of Rx=G1-Bu, Rat Gzv Ba is time-divided and output sequentially, and the pulse width modulation circuit (37
-1) to (37-n), the switching signal r□2
gyu, b□.

Generate raw gay bz.

What should be noted here is that the switching circuit (35-1
) to (35-n), G1. B□,
R.

G2. B2 video signal supply switching and electron beams R1, Gi, Bi, R by the horizontal deflection drive circuit (41)
,.

The horizontal deflection of the irradiation switching to the phosphors G, , and B is synchronously controlled so that they completely match both in timing and order. As a result, when the electron beam is irradiating the R phosphor, the irradiation amount of the electron beam is controlled by the R1 video signal.
B1. R,,G,,B are similarly controlled,
R,, G□, B, of each picture element.

R,,G,,B, the emission of each phosphor corresponds to the R□,G of that picture element.
1°B1. Each picture element is controlled by the R2, G, B2 video signals, and each picture element is displayed by emitting light according to the input video signal. Such control is performed simultaneously for 180 sets (2 picture elements each) for one line, and an image of 360 picture elements for one line is capped.

Further, 240H of lines are sequentially performed starting from the upper line, and one image is displayed on the screen (9)6.
This is repeated for each field, and as a result, a moving television image is displayed on the screen (9) in the same way as a normal television receiver.

In such an image display device, rectangular pulses of R and G are output from a computer or the like in order to display a dot matrix image.

The B component signal (which takes only two levels, HIGH or LOW) is directly input to the sample and hold circuits (31-1) to (31-n). However, since the sampling pulse generated by the sampling pulse generation circuit (34) and the R, G, B component signals, which vary depending on the model of computer, are asynchronous in phase, the repetition period of the sampling pulse and
Depending on the relationship between the pulse widths of the R, G, and B component signals, normal sampling may not be performed.

For example, as shown in FIG. 8(a), the pulse width T1 of the component signal is the repetition synchronization T of the sampling pulse.
If it is smaller than 2, if sampling is performed at the rising edge of the sampling pulse, the pulse portion of the component signal may not be sampled due to the phase shift, resulting in missing pixels on the screen. Furthermore, as shown in FIG. 8(b), if the pulse width T□ of the component signal is larger than the repetition period T2 of the sampling pulse, even though the component signal has a pulse width corresponding to one pixel on one screen. First, it is sampled as if it were a component signal with a pulse width that displays two or more pixels. As a result, the characters and figures displayed on one screen cannot accurately convey the original information.

OBJECTS OF THE INVENTION The present invention is intended to eliminate the conventional drawbacks such as l-, and to apply a complete dot matrix method to rectangular pulse-shaped R, G, and B component signals output from computers, etc. An object of the present invention is to provide an image display device that is capable of displaying images.

Structure of the Invention The present invention includes a plurality of line cathode electron beam generation sources, a screen having a phosphor that emits light when irradiated with the electron beams, and a focusing device that focuses the electron beams generated by the electron beam generation sources. A display including an electrode, an electrostatic deflection electrode that deflects the electron beam up to the screen, and a control electrode that controls the intensity of light emission by controlling the amount of the electron beam irradiated onto the screen. When displaying an image using a rectangular pulse-shaped color signal (for example, R2O, B component signal) output from a computer or the like, the display element is driven by the color subcarrier of the video signal. , a reference clock oscillator that generates a clock signal for sampling a video signal is driven by an oscillation clock signal that generates a color signal, and a clock signal for color signal sampling generated from this reference clock oscillator is driven by a clock signal for sampling the color signal of the relevant color. The signal is configured to be phase-synchronized with the color signal, and as a result, the pulse signal with the minimum unit width of the color signal can be displayed on the screen as a single pulse signal without missing or overlapping pixels.
It is displayed to correspond to a pixel, and enables complete dot matrix image display.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 9 is a block diagram showing the basic configuration around the video signal input section in the present invention.

In addition to the conventional video signal input terminal (23), R, G.

B component signal input terminals (43a) to (43c)
, an input terminal (44) for an oscillation clock signal CK that generates component signals for computers, etc., and horizontal and vehicle synchronization signals Hl used in computers and the like.

V' input terminals (45) and (46) are provided. R
,G.

The B component signal is directly input to the sample and hold circuits (31-1) to (31-n') by the changeover switch (47) without passing through the conventional color demodulation circuit (30).

On the other hand, the oscillation clock signal CK that generates R, G, and B component signals on the side of devices such as computers is switched to the reference clock oscillator (33) of the image display device using a conventional fsc and changeover switch (48). is input. As a result, the sampling pulse generation circuit (34)
The sampling pulses generated are phase-synchronized with the R, G, and B component signals. In addition, (4
9) is a changeover switch for switching between the horizontal and honest synchronous signals H and V generated by the synchronous separation circuit (24) and the horizontal and honest synchronous signals H' and V' input from the input terminals (45) and (46). It is.

- For example, as shown in Fig. 10, if the repetition period T2 of the sampling pulse is equal to the pulse width T1 of the minimum unit of the R, G, and B component signals and they are phase synchronized, then the rising edge of the pulse Since component signals are sampled at the edges, a pulse signal with a minimum unit width corresponds completely to one pixel on the screen, making it possible to display images equivalent to the dot matrix method over the entire screen.

Effects of the Invention As described above, according to the present invention, a rectangular pulse-shaped color signal output from a computer or the like can be sampled with a sampling pulse that is phase-synchronized with the color signal. It is possible to perform dot matrix image display in which a pulse signal having a unit width completely corresponds to one pixel on the screen.

[Brief explanation of the drawing]

Figure 1 is an exploded perspective view of an example of an image display element used in a conventional image display device, Figure 2 is an enlarged view of the fluorescent screen of the image display element, and Figure 3 is the basics of the drive circuit of the image display element. A block diagram showing the configuration and waveform diagrams of each part, FIG. 4 is a waveform diagram for explaining the operation of the vertical deflection drive circuit, FIG. 5 is a waveform diagram for explaining the operation of the line cathode drive circuit, and FIG. 6 is a waveform diagram for explaining the operation of the vertical deflection drive circuit. A waveform diagram of the drive signal. Figure 7 is a waveform diagram to explain the operation of the horizontal deflection drive circuit. Figure 8 shows the relationship between R, G, and B component signals and sampling pulses to explain the problems in the conventional example. FIG. 9 is an image in the present invention,
FIG. 10 is a block diagram showing one embodiment of the basic configuration around the signal input section, and is a diagram showing the relationship between R, G, and B component signals and sampling pulses in the present invention. (1)... Back electrode, (2) (2a) to (2c)
... Line cathode, (3) (3') ... Vertical focusing electrode, (4
) Vertical deflection electrode, (5) Beam flow control electrode, (6) Horizontal focusing electrode, (7) Horizontal deflection electrode, (9) Screen, (20) ...fluorescent substance. (23)...Input terminal, (24)...Synchronization separation circuit, (25)...Vertical deflection counter, (26)...
... Line cathode drive circuit, (27) ... Memory, (28)
...Horizontal deflection counter, (29)...Memory,
(30)...color demodulation circuit, (31-1) ~(31-
n)-sample hold circuit, (32-1) to (32-
n)...Memory, (33)...Reference clock oscillator, (34)...Sampling pulse generation circuit, (35
-1) to (35-n)...Switching circuit, (36
)... Switching pulse generation circuit, (37-1) ~
(37-n) -PWM circuit, (38) (39
)・D/A converter, (40)...Vertical deflection drive circuit, (41)...Horizontal deflection drive circuit, (42)...
・Deflection pulse generator/main circuit, (43a) to (43c)・
...R, G, B component signal input terminal, (44)
...Oscillation clock signal input terminal, (47)...R
2O, B component signal selection switch, (48)・
...Oscillation clock signal changeover switch, (49)...Horizontal and vertical synchronization signal changeover switch representative Yoshihiro Morimoto 4 Figure 3 (b) B D Figure 4-]l Figure 7 Section 8 t Figure 10 Tz rf=T2

Claims (1)

[Claims] 1. a plurality of line cathode electron beam generation sources, a screen having a phosphor that emits light when irradiated with the electron beam, a focusing electrode that focuses the electron beam generated by the electron beam generation source, and the electron beam generation source; The display element includes an electrostatic deflection electrode that deflects the beam up to the screen, and a control electrode that controls the emission intensity by controlling the amount of the electron beam irradiated onto the screen. When displaying an image using a rectangular pulse-shaped color signal output from a computer or the like on a display element, a reference clock oscillator that is driven by the color subcarrier of the video signal and generates a clock signal for sampling the video signal is required. An image display device is driven by an oscillation clock signal that generates a color signal, and a clock signal for color signal sampling generated from the reference clock oscillator is configured to be a signal synchronized in phase with the component signal.