JPH0339436B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention generates an electron beam for each division when a screen on a screen is vertically divided into a plurality of divisions, and generates an electron beam for each division. The present invention relates to an apparatus for displaying a plurality of lines by vertically deflecting a beam to display a television image as a whole.

Conventional configurations and their problems Traditionally, cathode ray tubes have been mainly used as display elements for displaying color television images, but conventional cathode ray tubes are extremely long and thin compared to the screen size. It would have been impossible to create a television receiver. In addition, EL display elements, plasma display devices, liquid crystal display elements, etc. have recently been developed as flat display elements.
All of them are insufficient in terms of performance such as brightness, contrast, and color display, and have not yet been put into practical use.

Therefore, in order to achieve a flat display device using electron beams, the present applicant filed a patent application in 1983-
No. 20618 (Japanese Unexamined Patent Publication No. 135590/1983) proposed a new display device.

This method generates an electron beam for each section when the screen is vertically divided into multiple sections, and displays multiple lines by deflecting each electron beam vertically for each section. However, it displays the television image as a whole.

First, a basic configuration of the image display element used here will be explained with reference to FIG. This display element includes, in order from the back to the front, a back electrode 1,
Line cathode 2 as a beam source, vertical focusing electrode 3,
3', a vertical deflection electrode 4, a beam flow control electrode 5, a horizontal focusing electrode 6, a horizontal deflection electrode 7, a beam acceleration electrode 8, and a screen 9. ) A line cathode 2 as a beam source is housed in a vacuumed interior and is stretched horizontally so as to generate an electron beam distributed linearly in the horizontal direction. A plurality of (only four 2a to 2b are shown in the figure) are provided in the vertical direction at appropriate intervals. In this example, it is assumed that 15 are provided. Let them be 2a to 2o. These wire cathodes 2 are constructed by coating the surface of a tungsten wire with a diameter of 10 to 20 μΦ with an oxide cathode material for thermionic emission. These line cathodes 2a to 2o are heated so as to generate a thermionic electron beam by passing an electric current through them, and as described later, emit electron beams sequentially for a certain period of time starting from the line cathode 2a. controlled as follows. The back electrode 1 suppresses generation of electron beams from line cathodes other than the line cathode controlled to emit electron beams for a certain period of time, and pushes out the generated electron beams only in the forward direction. act. The back electrode 1 may be formed by a coating of a conductive material applied to the inner surface of the rear wall of the glass bulb. Further, instead of the back electrode 1 and the linear cathode 2, a planar electron beam emitting cathode may be used.

The vertical focusing electrode 3 is a conductive plate 11 having a horizontally long slit 10 facing each of the line cathodes 2a to 2o. Focus. An electron beam for one horizontal line (360 pixels) is extracted at the same time. In the figure, only one section in the horizontal direction is shown. The slit 10 may be provided with crosspieces at appropriate intervals in the middle, or may be substantially formed by a row of through holes arranged horizontally at small intervals (nearly touching). may be configured. The vertical focusing electrode 3' is also similar.

A plurality of vertical deflection electrodes 4 are arranged horizontally in the middle of each of the slits 10, and are each composed of conductors 13 and 13' provided on the upper and lower surfaces of an insulating substrate 12. has been done. And the opposing conductors 13, 13'
A vertical deflection voltage is applied between them to deflect the electron beam in the vertical direction. In this embodiment, the electron beam from one line cathode 2 is vertically deflected to positions corresponding to 16 lines by a pair of conductors 13, 13'. The 16 vertical deflection electrodes 4 constitute 15 pairs of conductors corresponding to each of the 15 line cathodes 2, and in the end, the electron beams are emitted so as to draw 240 horizontal lines on the screen 9. deflect.

Next, the control electrodes 5 are composed of conductive plates 15 each having a vertically long slit 14, and a plurality of control electrodes 5 are arranged in parallel in the horizontal direction at a predetermined interval. In this example, 180 control electrode conductive plates 1
5-1 to 15-n are provided. (9 in the figure)
(only books shown). Each of the control electrodes 5 extracts the electron beam by dividing it into two picture elements in the horizontal direction, and controls the amount of electron beam passing therethrough in accordance with a video signal for displaying each picture element. Therefore, the conductive plates 15-1 to 15-n for the control electrode 5 are
If 180 lines are provided, 360 pixels can be displayed per horizontal line. In addition, in order to display images in color, each picture element is displayed with phosphors of three colors R, G, and B, and each control electrode 5 has each of R, G, and B for two picture elements. Video signals are added sequentially. In addition, 180 conductive plates 15-1 to 15 for control electrodes 5
-n, 180 sets of video signals for one line (two picture elements per set) are simultaneously applied, and the video for one line is displayed at one time.

The horizontal focusing electrode 6 is composed of a conductive plate 17 having a plurality of vertically long slits 16 (180 slits 16) facing the slits 14 of the control electrode 5, and collects electrons for each picture element divided in the horizontal direction. Each beam is focused horizontally into a narrow electron beam.

The horizontal deflection electrode 7 is made up of a plurality of conductive plates 18, 18' arranged vertically on both sides of the slit 16, and each electrode 18, 18' has six levels of horizontal deflection. A voltage is applied to horizontally deflect the electron beam for each pixel, and on the screen 9 two sets of R,
The G and B phosphors are sequentially irradiated to emit light. In this embodiment, the deflection range is two picture elements wide for each electron beam.

The accelerating electrode 8 is composed of a plurality of conductive plates 19 provided horizontally at the same position as the vertical deflection electrode 4, and accelerates the electron beam so that it collides with the screen 9 with sufficient energy.

The screen 9 is constructed by coating the back surface of a glass plate 21 with a phosphor 20 that emits light when irradiated with an electron beam, and adding a metal back layer (not shown). The phosphor 20 has R,
Two pairs of three-color phosphors, G and B, are provided and are applied in stripes in the vertical direction.
In FIG. 1, the broken lines drawn on the screen 9 indicate divisions in the vertical direction that are displayed corresponding to each of the plurality of line cathodes 2, and the two-dot chain lines correspond to each of the plurality of control electrodes 5. Indicates the horizontal division displayed. As shown in the enlarged view of FIG. 2, in one section partitioned by these two, there are R, G, and B phosphors 20 for two picture elements in the horizontal direction.
It has a width of 16 lines in the vertical direction. The size of one section is, for example, 1 mm in the horizontal direction,
The vertical direction is 9 mm.

Note that in FIG. 1, the length in the horizontal direction is greatly enlarged relative to the length in the vertical direction for clarity.

Further, in this example, one control electrode 5, that is, one
For the electron beam of the book, R, G, B phosphor 2
Only one pair of 0's for two picture elements is provided, but of course, one picture element or three or more picture elements may be provided, and in that case, the control electrode 5 has one picture element or three or more picture elements. R, G, and B video signals are sequentially added to the image signal, and horizontal deflection is performed in synchronization with the R, G, and B video signals.

Next, the basic configuration and waveforms of each part of a drive circuit for displaying television images on this display element will be explained with reference to FIG. First, a driving portion for irradiating the screen 9 with an electron beam to emit raster light will be described.

The power supply circuit 22 is a circuit for applying a predetermined bias voltage (operating voltage) to each electrode of the display element,
-V ₁ to the back electrode 1, and -V 1 to the vertical focusing electrodes 3 and 3'.
DC voltages of V ₃ , V ₃ ', V ₆ to the horizontal focusing electrode 6, V ₈ to the accelerating electrode 8, and V ₉ to the screen 9 are applied.

Next, a composite video signal of a television signal is applied to the input terminal 23, and a synchronization separation circuit 24 separates and extracts a vertical synchronization signal V and a horizontal synchronization signal H.

The vertical deflection drive circuit 40 includes a vertical deflection counter 25, a memory 27 for storing vertical deflection signals, and a digital-to-analog converter 39 (hereinafter referred to as a DA converter). Vertical deflection drive circuit 4
As the zero input pulse, the vertical synchronizing signal V and horizontal synchronizing signal H shown in FIG. 4 are used. The vertical deflection counter 25 (8 bits) is reset by the vertical synchronizing signal V and counts the horizontal synchronizing signal H. This vertical deflection counter 25 counts the effective scanning period (here, a period of 240H) excluding the vertical retrace period of the vertical period, and this count output is supplied to the address of the memory 27. The memory 27 outputs vertical deflection signal data (here, 8 bits) corresponding to each address, and the D-A converter 39 outputs the vertical deflection signal data (8 bits in this case) as shown in FIG.
It is converted into vertical deflection signals of ν and ν′ shown in . In the kneading circuit, there is a memory address that stores the vertical deflection signal corresponding to each line for 240H.
By storing regular data in the memory every 16 hours, a 16-step vertical deflection signal can be obtained.

On the other hand, the line cathode drive circuit 26 uses the vertical synchronization signal V and the output of the vertical deflection counter 25 to create line cathode drive pulses a to o. FIG. 5a shows the relationship between the vertical synchronizing signal V, the horizontal synchronizing signal H, and the lower five bits of the vertical deflection counter 25. FIG. 5b shows a method of creating line cathode drive pulses a' to o' every 16H using these signals. In FIG. 5, LSB indicates the lowest bit, and (LSB+1) means the bit one higher than the LSB.

The first line cathode drive pulse a' can be created by an R-S flip-flop using the vertical synchronization signal V and the output (LSB+4) of the vertical deflection counter 25, and the line cathode drive pulses b' to o' are shifted. This can be obtained by using a register to transfer the line cathode drive pulse a' using the inverted version of the output (LSB+3) of the vertical deflection counter 25 as a clock. These drive pulses a' to o' are inverted so that the potential is low only during each pulse period, and the line cathode drive pulse a is set at a high potential of about 20 volts during other periods.
~o (Fig. 3b, E), each line cathode 2a
~2o added.

Each line cathode 2a to 2o is heated by a prolonged current during the high potential period of the drive pulses a to o, and the heated state is maintained so that electrons can be emitted during the low potential period of the drive pulses a to o. Ru. As a result, electrons are emitted from the 15 linear cathodes 2a to 2o only during the 16H period when low potential drive pulses a to o are applied to each of them. During the period when a high potential is applied, the potential applied to the line cathodes 2a to 2o is higher than the potential at the position of the line cathode 2 determined by the bias voltage applied to the back electrode 1 and the vertical focusing electrode 3. Since the higher potential is positive, no electrons are emitted from the line cathodes 2a to 2o. Thus, in the line cathode 2, electrons are sequentially emitted from the upper line cathode 2a toward the lower line cathode 2o for each 16H period during the effective vertical scanning period. The emitted electrons are pushed forward by the back electrode 1, and the emitted electrons are pushed forward by the back electrode 1, and the slits 1 facing each other in the vertical focusing electrode 3
0 and is focused in the vertical direction to form a flat electron beam.

Next, the relationship between the line cathode drive pulses a to o and the vertical deflection signals ν, ν' will be explained using FIG. 6. FIG. 6a is a waveform diagram of a line cathode drive pulse, b is a waveform diagram of a vertical deflection signal, and FIG. 6c is a waveform diagram of a horizontal deflection signal. The vertical deflection signals ν, ν′ in FIG.
During the 16H period of each line cathode pulse a to o in figure a
Changes in 16-step increments of 1 hour. The vertical deflection signals ν and ν′ both have a center voltage of V ₄ , and ν
are made to change in opposite directions so that ν' increases sequentially and ν' decreases sequentially. These vertical deflection signals ν and ν′ are applied to the vertical deflection electrode 4, respectively.
As a result, the electron beams generated from the respective line cathodes 2a to 2o are vertically deflected in 16 steps, and as mentioned above, one electron beam is formed on the screen 9. At the source, the raster is deflected to draw 16 lines of raster one line at a time, starting from the top.

As a result of the above, electron beams are emitted from the 15 line cathodes 2a to 2o for a period of 16 hours in order from those above them.
In addition, each electron beam is deflected one line at a time from the top to the bottom within the 15 vertical divisions, so that on the screen 9, one line is deflected from the 1st line at the top to the 240th line at the bottom. The electron beam is vertically deflected minute by minute, creating a raster of 240 lines in total.

The electron beam thus vertically deflected is horizontally deflected by 180 degrees by the control electrode 5 and the horizontal focusing electrode 6.
It is divided into sections and taken out. Figure 1 shows one of these categories. The amount of electron beam passing through each section is controlled by a control electrode 5, and horizontally focused by a horizontal focusing electrode 6 into a single narrow electron beam, which is then controlled by horizontal deflection means described below. The light is then deflected in six steps in the horizontal direction, and is sequentially irradiated onto each of the R, G, and B phosphors 20 for two picture elements on the screen 9. FIG. 2 shows the vertical and horizontal divisions. The phosphors corresponding to 15-1 to 15-n of the control electrode 5 are R, G, and B for two picture elements, but for convenience of explanation, one picture element is R ₁ , G ₁ , and B _{1 and the other is R 1 , G 1 , and B 1} . Let R ₂ , G ₂ , and B ₂ .

Next, the horizontal deflection drive circuit 41 is composed of a horizontal deflection counter 28 (11 bits), a memory 29 storing horizontal deflection signals, and a DA converter 38. The input pulse to the horizontal deflection drive circuit 41 is synchronized with the vertical synchronizing signal V and the horizontal synchronizing signal H, as shown in FIG. 7, and uses a pulse 6H having a repetition frequency six times that of the horizontal synchronizing signal H. The horizontal deflection counter 28 is reset by the vertical synchronizing signal V and counts horizontal six times the pulse 6H. This horizontal deflection counter 28 counts 6 times during 1H and 240×6/H=1440 times during 1V, and this count output is supplied to the address of the memory 29. The memory 29 outputs horizontal deflection signal data (here, 8 bits) according to the address, and the D-A
A converter 38 converts the signal into horizontal deflection signals such as h and h' shown in FIG. 7 (FIGS. 3B and 3C). This circuit has memory addresses that store horizontal deflection signals corresponding to each of 6 x 240 lines.
By storing six pieces of regular data in the memory for each line, a horizontal deflection signal with six step waves can be obtained in a 1H period.

This horizontal deflection signal is a pair of horizontal deflection signals h and h' that change in 6 steps as shown in FIG. 7, both have a center voltage of V ₇ , and h gradually decreases.
h' increases in sequence and changes in opposite directions. These horizontal deflection signals h, h' are applied to electrodes 18 and 18' of the horizontal deflection electrode 7, respectively.
As a result, each horizontally divided electron beam is transmitted to the R, G, B,
The light is horizontally deflected so that R, G, and B (R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , B ₂ ) phosphors are sequentially irradiated for H/6 periods. Thus, in each line raster, the electron beam is divided into 180 sections in the horizontal direction.
Each phosphor 20 of R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ is sequentially irradiated with light.

Therefore, an electron beam is applied to each horizontal section of each line.
A color television image can be displayed on the screen 9 by modulating the video signals R ₁ , G ₁ , B ₁ , R _{2 ,} G ₂ , and B 2 .

Next, the modulation control portion of the electron beam will be explained. First, the television signal input terminal 23
The composite video signal applied to Combined with Y,
R, G, and B primary color signals (hereinafter referred to as R, G, and B video signals) are output. These R, G, and B video signals are processed by 180 sample and hold circuits 31-
1 to 31-n. Each sample hold circuit 31-1 to 31-n is for _R1 , _G1 ,
It has six sample and hold circuits for _B1 , _R2 , _G2 , and _B2 . These sample and hold outputs are stored in memories 32-1 to 32-n, respectively.
added to.

On the other hand, the reference clock oscillator 33 is constituted by a PLL (phase locked loop) circuit or the like, and in this example generates a reference clock 6fsc that is six times as large as the color subcarrier fsc and a reference clock 2fsc that is twice the color subcarrier fsc. The reference clock is controlled to always have a constant phase with respect to the horizontal synchronizing signal H.
The reference clock 2fsc is added to the deflection pulse generation circuit 42, which generates a signal 6H six times the horizontal synchronizing signal H and signal switching pulses r ₁ , g ₁ , b ₁ , r ₂ , g ₂ , every H/6.
A pulse of b ₂ (Fig. 3b, B) is obtained. On the other hand, the reference clock 6fsc is applied to the sampling pulse generation circuit 34, where the shift register
By delaying the clock by one cycle, the effective horizontal scanning period (approximately
1080 sampling pulses during 50μsec)
R ₁₁ , G ₁₁ , B ₁₁ , R ₁₂ , G ₁₂ , B ₁₂ , R ₂₁ , G ₂₁ ,
B ₂₁ , R ₂₂ , G ₂₂ , B ₂₂ ~ _{Rn 1} , Gn ₁ , Bn ₁ , Rn ₂ ,
Gn ₂ and Bn ₂ (FIG. 3bA) are generated sequentially, and then one transfer pulse t is generated. These sampling pulses R ₁₁ to Bn ₂ correspond to each picture element when one line of the video to be displayed is divided into 360 picture elements in the horizontal direction, and their positions are always constant with respect to the horizontal synchronizing signal H. controlled so that

These 1080 sampling pulses R ₁₁ to Bn ₂ each form 180 sets of sample hold circuits 31-1.
~ 31-n, and thereby each sample hold circuit 31-1 ~ 31-n has 1
When the line is divided into 180 lines, the video signals of R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ for each two picture elements are individually sampled and held. The sampled and held 180 pairs of R ₁ , G ₁ , B ₁ ,
The video signals of R ₂ , G ₂ , and B ₂ are stored in 180 sets of memories 32-1 to 32 after completing the sample hold for one line.
-n by a transfer pulse t and held here for the next horizontal period. The held signals R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ are applied to switching circuits 35-1 to 35-n. Each of the switching circuits 35-1 to 35-n
It is composed of a tri-state or analog gate having individual input terminals for R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ and a common output terminal for sequentially switching and outputting them.

The output of each switching circuit 35-1 to 35-n is 180 sets of pulse width modulation (PWM) circuits 37-1.
~37-n, where the reference pulse signal is pulse width modulated according to the magnitude of the sampled and held R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , B ₂ video signal and output. be done. The repetition period of the reference pulse signal is the above signal switching pulse r ₁ , g ₁ , b ₁ , r ₂ , g ₂ ,
It is desirable that the pulse width be sufficiently smaller than the pulse width of b ₂ , for example, a pulse width of about 1:10 to 1:100 is used.

The outputs of the pulse width modulation circuits 37-1 to 37-n are used as control signals for modulating the electron beam to the 180 conductive plates 15-1 of the control electrode 5 of the display element.
~15-n, respectively. The switching circuits 35-1 to 35-n are simultaneously controlled by switching pulses _r1 , _g1 , _b1 , _r2 , _g2 , _b2 applied from the switching pulse generating circuit 36. Switching pulse generation circuit 36
is controlled by the signal switching pulses r ₁ , g ₁ , b ₁ , r ₂ , g ₂ , b ₂ from the deflection pulse generation circuit 42 described above, and each horizontal period is divided into 6 and divided into H/6. Switch the switching circuits 35-1 to 35-n one by one,
Each video signal of R ₁ , G ₁ , B ₁ , R ₂ , G ₂ , B ₂ is time-divided and outputted sequentially, and the pulse width modulation circuits 37-1 to 3
Switching signals r ₁ , g ₁ , b ₁ ,
Generate r ₂ , g ₂ , b ₂ .

What should be noted here is that the switching circuit 3
R ₁ , G ₁ , B ₁ , R ₂ in 5-1 to 35-n,
G ₂ , B ₂ video signal supply switching and electron beams R ₁ , G ₁ , B ₁ , R ₂ ,
The horizontal deflection for switching the irradiation of G ₂ and B ₂ to the phosphor is
They are synchronously controlled to completely match both timing and order. As a result, when the electron beam is irradiating the R ₁ phosphor, the irradiation amount of the electron beam is controlled by the R ₁ video signal, and the same applies to G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ R ₁ , G ₁ , B ₁ , of each picture element are controlled by
R ₂ , G ₂ , B ₂ The emission of each phosphor is R ₁ ,
Each picture element is controlled by the video signals of G ₁ , B ₁ , R ₂ , G ₂ , and B ₂ , and each picture element is displayed by emitting light according to the input video signal. Such control is performed simultaneously for 180 sets of one line (2 picture elements each), so that an image of 360 picture elements per line is displayed, and then sequentially for 240 H of lines starting from the upper line. One image will be displayed.

The above operations are repeated for each field of the input television signal, and as a result,
The screen 9 is similar to a normal television receiver.
The television footage of the video is shown above.

In such an image display device, the white balance on the screen is achieved using input signals of red, green, and blue primary color signals (color demodulation circuit 3 in FIG. 3).
This has been done by modulating the level of the output R, G, B primary color signals).

For example, when it is necessary to lower the green primary color signal level (hereinafter abbreviated as S _G ), the overall S _G
The level decreases and the signal becomes smaller than the other two primary color signals. In this way, PWM circuit 3 in Figure 3
The input levels of 7-1 to 37-n become smaller,
The outputs of the PWM circuits 37-1 to 37-n are output as outputs with small pulse widths, and the white balance is adjusted. But at this time, this
As the S _G level has become smaller, the ratio of one step of the PWM circuit to the peak level of the S _G level has increased, and inevitably only the bits of the green color appear to be missing (bit loss). . Therefore, although the white balance can be adjusted as a whole, the problem arises that the gradation is significantly impaired, resulting in an image that is extremely difficult to view.

Purpose of the Invention The present invention solves the above-mentioned problems, and aims to provide an image display device that can completely adjust the white balance without sacrificing any deterioration in gradation. It is.

Structure of the Invention The present invention comprises a plurality of line cathodes as electron beam generation sources, which are stretched horizontally and arranged vertically at predetermined intervals, and electrons generated from the plurality of line cathodes. A back electrode that selectively emits the beam forward; a vertical deflection electrode that vertically deflects the electron beam emitted from each of the line cathodes; A control electrode extracts the electron beam in sections and controls the amount of the electron beam passing through according to the video signal for displaying each pixel, and a control electrode extracts the electron beam for each pixel divided horizontally. A display comprising: a horizontal deflection electrode that is deflected in the horizontal direction and sequentially irradiates phosphors of a plurality of colors on the screen in a time-sharing manner; and a screen coated with phosphor that emits light when irradiated with the electron beam. a memory means having a plurality of color elements and holding video signals of a plurality of colors sampled for each picture element, and a synchronization signal for deflection to irradiate the electron beam to the plurality of color phosphors in each horizontal section. switching means for extracting the video signal from the memory means; a pulse width modulation circuit for pulse width modulating a reference signal according to the magnitude of the video signal output from the switching means and applying it to the control electrode; A voltage-controlled clock generation circuit generates a reference signal for operating the modulation circuit, and a voltage-controlled clock generation circuit detects the peak level of the demodulated primary color signal and converts it into a DC voltage according to its magnitude. The clock frequency of the reference signal of the clock generation circuit is varied according to the DC voltage, and a good image without deteriorating gradation can be obtained.

DESCRIPTION OF EMBODIMENTS Hereinafter, one embodiment of the present invention will be described based on the drawings. The area 60 within the dashed line in FIG. 8 is the circuit that characterizes the present invention. Here, the white balance is adjusted based on the red primary color signal, and the circuit of the present invention is applied to two colors, green _SG and blue _SB . In FIG. 8, 61 and 62 are peak detection circuits that detect the peak levels (white levels) of S _G and S _B , hold this level, smooth it, and convert it into a clean DC voltage. It is thought that a holding period of about V period (vertical synchronization period) is sufficient, and may be around 30 to 50 ms.

Next, the output signals 63 and 64 from the peak detection circuits 61 and 62 are input to voltage controlled oscillators (hereinafter abbreviated as VCO) 65 and 66, and the output signals 63 and 6
A clock is generated in proportion to the DC level of 4.
At this time, the frequency of the clock output from the VCOs 65 and 66 is adjusted to vary in inverse proportion to the rate of decrease in the DC level of the output signals 63 and 64. The VCOs 65 and 66 are usually commercially available, and if they have a frequency of about 20 MHz, they can be sufficiently applied to the image display device.

Therefore, the output signals 67, 68 of VCO 65, 66
The clock frequency of can be reduced by lowering the S _G and S _B levels.
The gradation of the entire S _G and S _B levels, which are increased and decreased in proportion to this, is completely maintained when PWM conversion is performed. This situation is shown in FIG. Here, A indicates the red peak PWM output, and B and C indicate the green peak PWM output of the present invention and the conventional method.

Effects of the Invention According to the present invention, since the reference clock frequency of the PWM output generation circuit follows the DC level corresponding to the peak level of the primary color signal, the white balance can be arbitrarily selected based on the primary color signal level.
Moreover, PWM modulation can be performed without any loss of gradation, and a good image can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic electrode configuration of an image display device to which the present invention is applied, FIG. 2 is a diagram showing the minimum unit configuration on the screen, and FIG. 3 is a block diagram and diagram of the drive circuit in the device. Waveform diagrams of each part, Figure 4 is a correlation diagram between vertical deflection voltage and horizontal synchronization signal,
Figure 5 shows various timing charts, Figure 6 is a waveform diagram showing the relationship between cathode drive pulses, vertical deflection signals, and horizontal deflection signals, Figure 7 is a correlation diagram between horizontal deflection voltage and horizontal synchronization signal, and Figure 8 is FIG. 9 is a block diagram of the main parts of an image display device according to an embodiment of the present invention, and is a diagram showing a comparison between the PWM output after white balance adjustment of the present invention and a conventional one. 1... Back electrode, 2,2a-2o... Line cathode, 4...
Vertical deflection electrode, 5... Beam flow control electrode, 7... Horizontal deflection electrode, 9... Screen, 20... Fluorescent material, 23
...Input terminal, 24...Synchronization separation circuit, 30...Color bitonal circuit, 31-1 to 31-n...Sample hold circuit, 32-1 to 32-n...Memory, 33...Reference clock oscillator, 34...Sampling pulse generation Circuit, 35-1 to 35-n...Switching circuit, 3
6... Switching pulse generation circuit, 37-1 to 3
7-n...PWM circuit, 61, 62...Peak detection circuit, 65, 66...VCO.

Claims (1)

[Claims] 1. A plurality of linear cathodes as electron beam generation sources, which are stretched horizontally and arranged vertically at predetermined intervals, and electrons generated from the plurality of linear cathodes. A back electrode that selectively emits the beam forward; a vertical deflection electrode that vertically deflects the electron beam emitted from each of the line cathodes; A control electrode extracts the electron beam in sections and controls the amount of electron beam passing through it according to the video signal for displaying each pixel; A display comprising: a horizontal deflection electrode that is deflected in the horizontal direction and sequentially irradiates phosphors of a plurality of colors on the screen in a time-sharing manner; and a screen coated with phosphors that emit light when irradiated with the electron beam. a memory means for holding video signals of a plurality of colors sampled for each picture element; a switching means for extracting the video signal from the memory means by the switching means; a pulse width modulation circuit for pulse width modulating the reference signal according to the magnitude of the video signal output from the switching means and applying the pulse width to the control electrode; There is a voltage-controlled clock generation circuit that generates a reference signal for operating the modulation circuit, and a voltage-controlled clock generation circuit that detects the peak level of the demodulated primary color signal and converts it into a DC voltage according to its magnitude, which is then sent to the clock generation circuit. An image display device comprising: a peak detection circuit in which the clock frequency of the reference signal of the clock generation circuit is varied according to the DC voltage.