JPS61263181A - Formation of superconducting line - Google Patents

Abstract

PURPOSE:To miniaturize a circuit by etching a contact hole to a third insulator under conditions in which the etching rate of the third insulator is made larger than those of a second insulator and a superconductor wiring. CONSTITUTION:An insulator layer 4 is deposited to the upper sections of superconducting lines 1, 2 and an insulator layer 10, an etching mask, one part thereof extends over the superconducting line 2, for an opening section is formed onto the layer 4, and the insulator layer 4 is etched to shape a contact hole 6. The etching rate of the insulator 4 is set at a value larger than the etching rates of the superconducting lines and the insulator 10 as the conditions of etching at that time. The etching mask is removed, a superconducting layer is deposited to the upper sections of the insulator layer 4 and the contact hole 6, and a superconducting line 3 is formed through an ion etching method, and connected electrically to the superconducting line 2. Accordingly, an inter-layer short circuit in the contact hole 6 section can be prevented, thus bringing the line width 7 and inter-line width 8 of the superconducting lines 1, 2 to minimum size, then miniaturizing a circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for forming a superconducting wire pad, and more particularly to a method for forming a contact hole portion. Superconducting integrated circuits containing Josephson junctions are capable of high-speed signal transmission due to the high-speed switching characteristics of Josephson junctions, low power consumption characteristics, and lossless properties of superconducting lines, and are characterized by extremely low power consumption. Motsu. The superconducting integrated circuit has a multilayer structure consisting of Josephson junctions and multilayer superconducting lines. As a manufacturing method for realizing this circuit, a dry etching process using reactive ion etching technology or the like is often used, using a high-melting point metal for corners and the like, which is excellent in terms of reliability and microfabrication.

According to this manufacturing method, it is necessary to make contact holes in the interlayer insulating layer in order to establish electrical connections between the multilayer interconnections of the superconducting integrated circuit. As a circuit becomes more highly integrated, the number of contact holes increases, and the area occupied by the contact portion in the circuit increases. Therefore, reducing the size of the contact portion is very effective in reducing the size of the entire circuit.

(Prior art and its problems) FIG. 3 (aXb) is a diagram for explaining a conventional example of a contact hole forming method. FIG. 3(a) is a plan view showing an example of a superconducting line, and FIG. 3(b) is a sectional view of the cc' portion of FIG. 3(a). First and second superconducting lines 31.3
2 is patterned on the top of the first SiO insulator layer 35 by, for example, reactive ion etching. The line width at this time is t337, and the width between lines is t3'38 or t4'39. Next is the first one. and a second SiO insulator layer 3 to cover the second superconducting line 31 and 32.
4 and then a second Si on the second superconducting line 32.
A contact hole 36 is formed in the O insulator layer 34 by, for example, reactive ion etching. The width of the contact hole 36 is w41. A third superconducting line 33 is patterned above the contact hole 36 by, for example, reactive ion etching. Said 1st. Second. Third
For example, Nb can be selected for the superconducting lines 31, 32, 33. The etching conditions for forming the contact hole 36 are set so that the etching rate of SiO is higher than the etching rate of Nb.

According to the formation method of this conventional example, it is necessary to make the size of the second superconducting line 32 below the contact hole 36 larger than the contact hole 36 by the alignment dimension n. This is because there is a possibility of interlayer short-circuiting at the contact hole portion. Now, the minimum dimension is t. In addition, if the line width between the first superconducting line 31 and the second superconducting line 32 is t4' at the contact part and t3' at the other parts, then t3=t4' in order to minimize the circuit size. It is desirable that =w=to. However, the line width t3' is the minimum dimension t by the alignment dimension n. It will become bigger. In an integrated circuit, a large number of such contact portions must be used, and it is difficult to make the line spacing close to the minimum dimension. For these reasons, conventional methods for forming superconducting lines have limitations in circuit miniaturization.

(Objective of the Invention) An object of the present invention is to solve the problems of the conventional method and to propose a method for forming a superconducting line that enables miniaturization of the circuit.

(Structure of the Invention) According to the present invention, the first
a first step of forming a superconducting wiring, and etching at least a portion of the upper part of the first insulator under conditions that are higher than the etching rate of a second insulator other than the first superconducting wiring. A method for forming a superconducting line is obtained, which is characterized in that it includes a fourth step of etching a contact hole of an appropriate size so as to span the first superconducting line.

(Function of the Invention) In a dry etching process such as reactive ion etching, a certain degree of overetching is required due to non-uniformity of etching on a wafer, variation in film thickness during film formation, etc. Therefore, it is important that the etching speed ratio between the object to be etched and the underlying material is high. In the present invention, if a contact hole is etched in the third insulator under conditions such that the etching rate of the second insulator and superconducting wiring is smaller than the etching rate of the third insulator, if the contact hole is Even if the hole is larger than the superconducting wire, etching can be stopped with the second insulator. Therefore, interlayer short circuits at the contact portion can be prevented. Therefore, the width of the wiring can be determined regardless of the presence or absence of contacts.

Embodiments of the present invention will be described below with reference to the drawings.

(Example 1) FIGS. 1(a) and 1(b) are diagrams for explaining a first example of the present invention. FIG. 1(a) shows a plan view of the first embodiment, and FIG. 1(b) shows the A of FIG. 1(a).
It is a sectional view at A'. The first insulating layer 5 is, for example, a SiO film formed by resistance heating vapor deposition, a silica film formed by spin coating and baking, or an S film formed by bias sputtering.
A superconducting layer, such as a Nb film, is deposited on top of the iO film or the like by sputter deposition. Subsequently, the photoresist is patterned into a desired pattern, the resist mask is used as an etching mask, and the first pattern is etched by, for example, reactive ion etching. A second superconducting line 1°2 is formed. Next, the second
After depositing an insulator layer 10 such as an Al2O3 film formed by electron beam evaporation, the photoresist mask is removed and the first insulator layer 10 is deposited. The second superconducting lines 1 and 2 are flattened. Said 1st. A third insulating layer 4 is formed on the second superconducting lines 1, 2 and the second insulating layer 10, for example, an SiO film formed by resistance heating vapor deposition, or a silica film formed by spin coating and baking. Alternatively, a SiO film or the like formed by bias sputtering is deposited.

On the second insulator layer 4, an etching mask having an opening so that at least a part thereof covers the second superconducting line 2 is formed using photoresist, and the third insulator layer is etched through the etching mask. The layer is etched, for example by reactive ion etching, to form contact holes 6. The etching conditions at this time are set so that the etching rate of the third insulator is higher than the etching rate of the superconducting line and the second insulator. Subsequently, after removing the etching mask, a superconducting layer, such as a Nb film, is deposited on the third insulating layer 4 and the contact hole 6 by sputter deposition to a thickness equal to or greater than the depth of the contact hole 6, for example. A third superconducting line 3 is formed by reactive ion etching. The third superconducting line 3 and the second superconducting line 2 are electrically connected through the contact hole 6.

According to the formation method of the present invention, even if the contact hole portion is over-etched due to non-uniform etching or variation in film thickness when forming the contact hole 6, the etching will not occur in the second insulating layer 10. It will be stopped. Therefore, even if a superconducting layer exists under the first insulator layer 5, there is no possibility of an error such as an interlayer short circuit occurring at the contact hole 6 portion. Therefore, it is appropriate that the line widths t and 7 and the interline width t1'8 of the first and second superconducting lines 1 and 2 are the sum of the width and the alignment dimension 2n. The depth of the contact hole 6 is determined by the thickness of the third insulating layer 4, and it is easy to set the thickness of the third superconducting line 3. Also number 1. The second superconducting line can be made flat by appropriately selecting the thickness of the second insulator layer. Furthermore, the film thickness of the first insulator layer 5 can be selected to be thin, and the first insulator layer 5 can be selected to have a small thickness. The inductance of the second superconducting lines 1 and 2 can be lowered. This also leads to faster circuits.

(Embodiment 2) FIGS. 2(a) and 2(b) are diagrams for explaining a second embodiment of the present invention. FIG. 2(a) shows a plan view of the second embodiment, and FIG. 2(b) is a sectional view taken along BB' of FIG. 2(a). First insulator layer 15
For example, a superconducting layer such as a Nb film is deposited by sputter deposition on top of a SiO film formed by resistance heating vapor deposition, a silica film formed by spin coating and baking, or a 5i02 film formed by bias sputtering. do. Subsequently, the photoresist is patterned into a desired pattern, and a second insulating layer 16, such as an A1□03 film formed by electron beam evaporation, is deposited on the resist, and then the photoresist mask is removed and the first insulating layer 16 is deposited. ．． The second superconducting lines 11° and 12 are flattened. Said 1st. 2nd superconducting line 11° construction 2 and 2nd
On top of the insulator layer 16, a third insulator layer 4 is formed, for example, a SiO film formed by resistance heating vapor deposition, a silica film formed by spin coating and baking, or a SiO film formed by bias sputtering. accumulate. On the second insulator layer 14, an etching mask having an opening so that at least a part thereof covers the second superconducting line 12 is formed using photoresist, and the third insulator layer is etched through the etching mask. Contact holes 17 are formed by etching layer 14, for example by reactive ion etching. The etching conditions at this time are set so that the etching rate of the third insulator is higher than the etching rate of the superconducting line and the second insulator. Subsequently, after removing the etching mask, the third
A superconducting layer, for example a Nb film, is electrically connected to the top of the insulating layer 14 and the contact hole 17 via the sputter deposition hole 17.

According to the forming method of the present invention, even if the contact hole portion is over-etched due to non-uniform etching or variation in film thickness when forming the contact hole 17, the etching will not occur in the second insulating layer 16. It will be stopped at Therefore, even if a superconducting layer exists under the first insulator layer 15, there is no possibility of an error such as an interlayer short circuit occurring at the contact hole 17 portion. Therefore, the line width t118 and the interline width t,'19 of the first and second superconducting lines 11.12 can be selected to the minimum size regardless of the presence or absence of a contact hole.
The circuit can be made smaller. At this time, it is appropriate that the width of the contact hole is the line width of the second superconducting line plus the alignment dimension 2n. The depth of the contact hole 17 is determined by the thickness of the third insulating layer 14, and it is easy to set the thickness of the third superconducting line 13. Also number 1. The second superconducting line can be made flat by appropriately selecting the thicknesses of the second and fourth insulating layers. Furthermore, the film thickness of the first insulator layer 15 can be selected to be thin, and the first insulator layer 15 can be selected to have a small thickness. The line width and line spacing of the inductance conductive line of the second superconducting line 11.12, regardless of the presence or absence of a contact hole,
The smallest dimensions can be achieved, and the circuit can be significantly miniaturized. Furthermore, the maximum depth of the contact hole is determined, and it is easy to set the film thickness of the upper line. Furthermore, by selecting the film thicknesses of the second and fourth insulators, the superconducting wiring can be planarized.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are diagrams for explaining the present invention in detail,
FIG. 1(a) is a plan view of the first embodiment, and FIG. 1(b) is a sectional view of the first embodiment. FIG. 2(a) is a plan view of the second embodiment, and FIG. 2(b) is a sectional view of the second embodiment. FIG. 3 is a diagram for explaining the present invention in detail, and FIG. 3(a) is a plan view of a conventional example, and FIG. 3(b) is a sectional view of the conventional example. ' In each figure, 1.11.31...first superconducting line, 2, 12.32... second superconducting line, 3.13.33... third superconducting line, 5. 15
．． 359. First insulator layer, 10.16.34... Second insulator layer, 4, 14... Third insulator layer, 21.
... Fourth insulator layer, 6.17.36... Contact hole, 7.18.38... Line width of superconducting line, 8.
19.38.39...Width between superconducting lines, 9.20.
40... Indicates the alignment dimension, 41... Indicates the width of the contact hole. Figure 1 (b) '5 Z Figure Figure 3 <b)

Claims (1)

[Claims] a first step of forming a first superconducting wiring on at least an upper part of the first insulator; and depositing a second insulator on a part other than the first superconducting wiring on the first insulator. a second step, a third step of forming a third insulator on top of the first superconducting wiring and the second insulator, and an etching rate of the third insulator; A fourth step of etching a contact hole of an appropriate size so that at least a part of the contact hole covers the first superconducting wire under conditions that are higher than the etching rate of the superconducting wire and the second insulator. A method for forming a superconducting line, comprising the steps of: