JPS6126104B2 - - Google Patents
Info
- Publication number
- JPS6126104B2 JPS6126104B2 JP6105282A JP6105282A JPS6126104B2 JP S6126104 B2 JPS6126104 B2 JP S6126104B2 JP 6105282 A JP6105282 A JP 6105282A JP 6105282 A JP6105282 A JP 6105282A JP S6126104 B2 JPS6126104 B2 JP S6126104B2
- Authority
- JP
- Japan
- Prior art keywords
- bus
- memory
- main memory
- buses
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012545 processing Methods 0.000 claims description 42
- 238000012937 correction Methods 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 9
- 230000004044 response Effects 0.000 claims description 5
- 238000012546 transfer Methods 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 claims 1
- 102100034460 Cytosolic iron-sulfur assembly component 3 Human genes 0.000 description 19
- 101710095809 Cytosolic iron-sulfur assembly component 3 Proteins 0.000 description 19
- 238000010586 diagram Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
- 102100039307 Nuclear prelamin A recognition factor Human genes 0.000 description 1
- 101710112231 Nuclear prelamin A recognition factor Proteins 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
- Multi Processors (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6105282A JPS58178454A (ja) | 1982-04-14 | 1982-04-14 | メモリ制御方式 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6105282A JPS58178454A (ja) | 1982-04-14 | 1982-04-14 | メモリ制御方式 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58178454A JPS58178454A (ja) | 1983-10-19 |
JPS6126104B2 true JPS6126104B2 (es) | 1986-06-19 |
Family
ID=13160055
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6105282A Granted JPS58178454A (ja) | 1982-04-14 | 1982-04-14 | メモリ制御方式 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58178454A (es) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0527378Y2 (es) * | 1986-02-25 | 1993-07-13 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NO173304C (no) * | 1984-12-20 | 1993-11-24 | Honeywell Inc | Dobbelt buss-system |
US4612542A (en) * | 1984-12-20 | 1986-09-16 | Honeywell Inc. | Apparatus for arbitrating between a plurality of requestor elements |
-
1982
- 1982-04-14 JP JP6105282A patent/JPS58178454A/ja active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0527378Y2 (es) * | 1986-02-25 | 1993-07-13 |
Also Published As
Publication number | Publication date |
---|---|
JPS58178454A (ja) | 1983-10-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
AU620318B2 (en) | Arbitration technique for a split transaction bus in a multiprocessor computer system | |
US4591977A (en) | Plurality of processors where access to the common memory requires only a single clock interval | |
US4669079A (en) | Method and apparatus for bus arbitration in a data processing system | |
US4181974A (en) | System providing multiple outstanding information requests | |
US6651148B2 (en) | High-speed memory controller for pipelining memory read transactions | |
US4236203A (en) | System providing multiple fetch bus cycle operation | |
US4245299A (en) | System providing adaptive response in information requesting unit | |
JPS6043546B2 (ja) | デ−タ転送異常処理方式 | |
JPS6126104B2 (es) | ||
JPH07319829A (ja) | データ転送方法 | |
JP2713204B2 (ja) | 情報処理システム | |
US20010005870A1 (en) | External bus control system | |
JPS6125178B2 (es) | ||
JPH0562384B2 (es) | ||
JPS6153753B2 (es) | ||
JP2699873B2 (ja) | バス制御回路 | |
JPS60134956A (ja) | 情報処理システム | |
JPS61248153A (ja) | マルチプロセツサシステムにおけるメモリアクセス制御方式 | |
JP2856709B2 (ja) | バス間結合システム | |
JPH0113575B2 (es) | ||
JPS5825299B2 (ja) | メモリ制御方式 | |
JPH0248749A (ja) | バッファ記憶制御装置 | |
JPH09507939A (ja) | マルチプロセッサ・システムにおける入出力オペレーションの実行 | |
JPH05265932A (ja) | バス制御方式 | |
JPS62120566A (ja) | マルチ・プロセツサ・システムにおける高速主記憶アクセス制御方式 |