JPS61260347A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To maintain the consistency of operation time with other semiconductor integrated circuit devices which are combined as a system by providing an output circuit which switches a high impedance state and the output ready state of an input signal. CONSTITUTION:When a selecting circuit 9 sends out an input signal 5 as an output signal 12 by being commanded with selection signals 10 and 11, an output indication signal 4 is transmitted to an output circuit 14 most early and the output ready state and high impedance state are switched most quickly. When the selecting circuit 9 sends out an input signal 8 as the output signal 12 by being commanded with the selection signals 10 and 11, the output indication signal 4 is transmitted to the output circuit 14 most late and the output ready state and high impedance state are switched most late. Even when input signals 6-7 are selected and outputted as the output signal 12, the output indication signal 14 is transmitted to the output circuit 14 after being delayed correspondingly. Therefore, the delay time up to the arrival of the output indication signal 4 at the output circuit 14 is selectable in several ways.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and sometimes relates to a semiconductor integrated circuit device equipped with an output circuit having a function of switching between a high impedance state and an output enabled state based on an output instruction signal. .

[Conventional technology]

Conventionally, semiconductor integrated circuit devices equipped with an output circuit that has the function of switching between a high-impedance state and an output-enabled state in response to an output instruction signal have a delay time that is fixed to a constant value from the change in the output instruction signal to the switching of the output circuit. There is. For this reason, other semiconductors combined as a system -
It may not match the delay time of the same type of a-product circuit device, and it may not be guaranteed that the difference in delay time between them is within the allowable value range. There are problems such as insufficient hold time required for data acquisition.

[Problem that the invention seeks to solve]

The problem to be solved by the present invention is to solve the above-mentioned disadvantages of the conventional semiconductor integrated circuit device having an output circuit that switches the output state by an output instruction signal. An object of the present invention is to provide a semiconductor integrated circuit device including an output circuit.

[Means for solving problems]

The semiconductor integrated circuit device of the present invention includes a plurality of delay circuits that input an output instruction signal and output delayed output instruction signals that are sequentially delayed, and a plurality of delay circuits that input an output instruction signal and output delayed output instruction signals that are sequentially delayed; a selection circuit that inputs a plurality of the delayed output instruction signals and selects and outputs the output instruction signal or any one of the plurality of delayed output instruction signals according to a command of a selection signal; and an output circuit that receives the output signal of the selection circuit and switches between a high-impedance state and a state in which the input signal can be output based on the output signal of the selection circuit.

〔Example〕

Next, the present invention will be described in detail with reference to drawings showing embodiments.

The drawing is a circuit diagram showing an embodiment of the present invention.

In FIG. 2, delay circuits 1 to 3 input output instruction signal 4 and sequentially delay input signals 6 to 8 to select circuit 9.
Output to. Since the output instruction signal 4 is directly input to the selection circuit 9 as the input signal 5, the input signal 5 is inputted to the selection circuit 9 first, followed by the input signal 6, input signal 7, and input signal 8. input with a delay. The selection signals 10 to 11 are control signals for selecting any one of the input signals 5 to 8 to the selection circuit 9 and outputting the output signal 12. (Selection signals 10 to 11 are both 2
The value signal is 10'' or 1''.

Any one of the four input signals 5 to 8 is selected in combination. Therefore, if there are four or more delay circuits, the number of selection signals will also be three or more.)

The output circuit 14 outputs a signal corresponding to the input signal 13 to the output terminal 15 if it is in an output enabled state, and sets the output terminal 15 to a floating state if it is in a high impedance state. The output enable state and high impedance state of the output circuit 14 are controlled by the output signal 12 from the selection circuit 9.

Although the supply source of the output instruction signal 4 and the selection signals 10 to 11 is not shown, the input terminal of the semiconductor integrated circuit device or the output of a register inside the semiconductor integrated circuit device is connected.

Next, the operation of this example will be explained. In the figure, if the selection circuit 9 outputs the input signal 5 as the output signal 12 in response to the selection signals 10 and 110 commands, the output instruction signal 4 is transmitted to the output circuit 14 as soon as possible, and this makes it possible to output. The transition to the high-impedance state is the quickest. If the selection circuit 9 outputs the input signal 8 as the output signal 12 according to the selection signals 1o and 110 commands, the output instruction signal 4 is outputted from the output circuit 1 with the latest delay.
4, and thereby the switching between the output enabled state and the high impedance state is performed with the greatest delay. Even when input signals 6 to 7 are selected and output as output signals 12, output instruction signal 4 is transmitted to output circuit 14 after a corresponding delay time. Therefore, the delay time until the output instruction signal 4 is transmitted to the output circuit 14 can be selected from several options (four types in the example shown), and this is due to the delay time from the time when the output instruction signal 4 changes to the output circuit 14. This means that the delay time until the state change can be selected from four types.

In a system in which pass lines are connected, the output terminal 15 shown in the figure is connected to a similar output terminal of another semiconductor integrated circuit device. If there is a difference in delay time until the state changes, problems such as collision of signals on the path line and insufficient hold time for data acquisition will occur. On the other hand, in the output circuit shown in this embodiment, the selection signals 10 and 11 select one of a plurality of types of delay time from the time when the output instruction signal changes to the time when the state of the output circuit changes. Since this option is selectable, problems such as bus collisions and lack of hold time can be avoided. In this embodiment, four types of input signals having different delay times, indicated by input signal 5, input signal 6, input signal 7, and input signal 8, are generated from the output instruction signal 4, and any one of these is generated. is selected and input to the output circuit, but the number of delayed input signals generated from the output instruction signal 4 can be increased or decreased, and the number of selection signals to the selection circuit cannot be changed accordingly. it is obvious.

〔Effect of the invention〕

As explained above, by using the semiconductor integrated circuit device of the present invention, the delay time from the time when the output instruction signal changes to the time when the output circuit switches between the high impedance state and the output enabled state can be set to a desired value. Equipped with the means,
This has the effect of making it possible to maintain consistency in operating time with other semiconductor integrated circuit devices combined as a system, thereby preventing signal collisions on pass lines,
This has the effect of avoiding problems such as insufficient hold time for data capture.

[Brief explanation of the drawing]

The drawing is a circuit diagram showing an embodiment of the present invention. 5.6.7.8... Input signal, 12...
- Output signal, 13...Input signal. /, , -J-,...

Claims (1)

[Claims] a plurality of delay circuits that input an output instruction signal and output delayed output instruction signals that are sequentially delayed; and input the output instruction signal and the plurality of delayed output instruction signals from the plurality of delay circuits. and a selection circuit that selects and outputs the output instruction signal or any one of the plurality of delayed output instruction signals according to a command of a selection signal, and inputs an input signal and an output signal of the selection circuit. and an output circuit that switches between a high-impedance state and a state in which the input signal can be output based on an output signal of the selection circuit.