JPS61255171A - Digital horizontally synchronous circuit - Google Patents

Abstract

PURPOSE:To carry out a detection of a horizontally synchronous signal with high accuracy and to remarkably reduce jittering of a horizontally synchronous reproduction by detecting a phase correction signal of a horizontally synchronous signal by the use of a value of a synchronization separating level and the value of a digital video signal before and after thereof and correcting the phase of a horizontally synchronous oscillating output by a phase correcting signal. CONSTITUTION:A phase detecting circuit 13 between sampling clocks obtains a phase correcting signal CSDELTAtau by the use of a value of a synchronization separating level SEP and the value of a digital video signal immediately before and after thereof. A horizontally synchronous detecting signal HS, a phase compensating signal CSDELTAtau are supplied to a horizontal phase error detecting circuit 15. The horizontal phase error detecting circuit 15 forms together with a horizontal loop filter 16, a digital control oscillator 17, a phase locked loop. This horizontally phase locked loop detects a phase difference of an oscillating output phase of the control oscillator 17 and a horizontally synchronous signal in a video signal with high accuracy and operates so as to precisely lock a prescribed phase of a horizontally synchronous reproducing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital horizontal synchronization circuit used in a digital television receiver.

[Technical background of the invention]

Recently, due to advances in semiconductor technology, digital television receivers have been developed that digitize baseband video signals and perform various signal saturations. To facilitate processing, the frequency of the sampling clock K is selected to be three or four times the color subcarrier frequency, and processing is performed to synchronize the phase of the sampling clock with the color burst signal.

On the other hand, the phase relationship between the sampling clock and the horizontal synchronization signal is not particularly determined. Therefore, horizontal synchronization signal detection for signals such as black and white broadcasting and video recorders is
When the sampling is performed in units of the sampling clock, there is a dead zone for phase detection in the sampling period. As a result.

Jitter occurs in horizontal synchronized playback.

For example, if the sampling clock is four times the chrominance subcarrier frequency of the NTSC signal, the sampling period is 70 ns@e, and the jitter caused by 9 has a large adverse effect on the time difference.

Therefore, there is a need for a horizontal synchronization circuit that can detect horizontal synchronization signals with high precision and has less jitter.

[Purpose of the invention]

This invention was made in view of the above circumstances, and is a digital signal that can detect horizontal synchronization signals with high precision, obtain phase correction with a resolution greater than the period of the sampling clock, and significantly reduce jitter in horizontal synchronization playback. The purpose is to provide a horizontal synchronization circuit.

[Summary of the invention]

In this invention, for example, as shown in FIG. 1, FIG. 2, and FIG. 3! 5, an inter-sampling clock phase detection circuit 13 is provided to correct the horizontal synchronization detection signal (H8) synchronized with the cycle of the sampling clock φS with a phase finer than the cycle of the clock φS. This sampling clock interval phase/phase detection circuit 13 is a synchronization separation repeater 4si
Values (DA) of the digital video signal immediately before and after p)
Using (DB), (DB-8EP)/(DB-DA)
A phase correction signal (C8Δ) is obtained by the following calculation. Thereby, in the next stage circuit, the phase of the horizontal synchronization signal can be corrected more finely than the period of the sampling clock φS.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a horizontal synchronization circuit for a digital camera according to a first embodiment of the present invention. The analog video signal □ (muv8)' is converted into a digital video signal (DVS) by the sampling clock (φ8)K of the analog-to-digital converter 11.
is converted to In this embodiment, the frequency of the sampling clock (φS) is selected to be four times the color subcarrier frequency (f,), and this clock (φ−) is the basis of the entire system.

The digital video signal (PVS) is sent to the sync separation circuit 1'2.
, are supplied to the sampling clock phase detection circuit 13. The synchronization separation circuit 12 receives a digital video signal (nvs
) and the synchronization separation rep, Hsy).The synchronization signal is separated to obtain a composite synchronization signal (CS).

The composite synchronization signal (CB) is guided to the horizontal synchronization detection circuit 14. The horizontal synchronization detection circuit 14 detects the normal pulse period and width of the composite synchronization signal to detect [horizontal synchronization detection signal (
Ha) is obtained.

The inter-sampling clock phase detection circuit 13 is shown in FIG.
As explained in detail in FIG. 3, the phase difference between the sampling clock φS and the rising edge of the horizontal synchronization detection signal (US) is detected to obtain a phase correction signal (CSΔ).

The means to obtain the above phase correction signal (C8Δ) are as follows:
This will be explained with reference to FIGS. 2 and 3.

Figure 2 is a time chart showing an enlarged rising portion of the horizontal synchronization signal.In Figure 6, the digital video signal (DVS) is shown in analog form for the sake of clarity; The only part of the signal (DVS) with a black circle (the rising edge of the sampling clock φS) is obtained as the signal (DVS). Therefore, the rising edge of the composite synchronization signal '(c s ) is the sampling clock φ8 horizontal synchronization detection signal (US), which is synchronized with the rising edge of
is also phase-locked to the rising edge of the composite synchronization signal (CB).

However, now, at point B shown in the figure, the horizontal synchronization signal (Ha)
, the actual horizontal synchronization signal is considered to have crossed the synchronization separation level (SEP), and the time shown in Figure B is
This is a time point 08Δτ before the point. C8Δτ above
By determining , it is possible to detect the rising phase error of the horizontal synchronizing signal (II8) with finer precision than the period of the sampling clock φS.

FIG. 3 shows a sampling clock phase detection circuit 13 which obtains the above CSΔτ as a phase correction signal.

The separation level cross point detection circuit 131 obtains data (DA) at the time immediately before the rising edge detection time CB) of the horizontal synchronization detection signal (Ha) and data (DB) at the time CB). DB) is input to the inter-clock phase calculation circuit 132. This arithmetic circuit 132 further uses a synchronization separation rep, x (a) i8p).

Perform the following calculation.

csΔτ= DB -5EP DB -DA Here, the slope before and after the sync separation level of the video signal is:
An approximation is made that it is constant. Through this calculation, a phase correction signal (C84) is obtained.

Let me explain by going back to Figure 1.

The above horizontal synchronization detection signal (H8), phase correction signal (CSΔ
One is supplied to the horizontal phase error detection circuit 15.

The horizontal phase error detection circuit 15 forms a phase locked loop together with the horizontal loop filter 16 and the digitally controlled oscillator 11, as will be described in detail in FIG. This horizontal phase-locked loop is connected to the digitally controlled oscillator 170 oscillation output phase (
The phase difference between the horizontal synchronization signal (predetermined phase of the horizontal counter output) and the horizontal synchronization signal in the video signal is detected with high precision, and the horizontal counter output (HCTR), that is, the predetermined phase of the horizontal synchronization reproduction signal, is detected in the horizontal synchronization signal in the video signal. Works to lock accurately.

The phase-locked loop will be explained with reference to FIG.

The digitally controlled oscillator 11 outputs a horizontal synchronization detection signal (H8)
It is an all-digital oscillator whose oscillation period is controlled by the oscillator, and is capable of high-precision table operation with 48 clocks or more.

Digitally controlled oscillator 11 has a horizontal counter 111. The horizontal counter 111 receives a horizontal counter reset signal-I.
KBg) and counts the number of digits φB.

A count output (HCTR) as a horizontal synchronization reproduction signal of the horizontal counter 171 is supplied to the -number construction circuit 112 and the latch circuit 151 in the horizontal phase error detection circuit 15.

The latch circuit 151 latches the horizontal count output (HCTR) with the previous horizontal synchronization detection signal (H8) and supplies the value to the subtracter XSX.

The subtracter 152 subtracts the previous phase correction signal No. 4 (Can error) from the output value of the latch circuit 161. This means that the phase of the horizontal synchronization detection signal (Ha) is equal to the phase (value) of the horizontal counter output. From this value, the phase correction signal (C
SΔτ).

The output of subtracter 152 is input to subtracter 153. The subtracter 153 further subtracts the output phase correction signal (HCl) of the horizontal counter 171 from the output value of the subtracter 151. Even if the phase relationship becomes a predetermined phase relationship, true synchronization cannot be obtained if there is an error in the horizontal counter 171 itself.

Next, the output of the subtracter 153 is directly supplied to a subtracter 154, where the horizontal counter target phase value (Hr@f) is subtracted. In other words, if the horizontal synchronization detection signal (US) and the output phase of the horizontal counter 171 have a predetermined relationship, the subtracter 1
The output value of 54 can be calculated in advance. Therefore, subtractor 15
4, if the horizontal counter target phase value (Hrvf) is subtracted from the output value of the subtracter 153, the target phase value (Hr@f
) and the error can be obtained.

The output of subtracter 154 is supplied to limiter circuit 155. Limiter circuit 155 limits signals with large errors from subtracter 154. This limiter circuit 155 operates when the horizontal synchronization detection signal (Ha) is erroneously detected.
Limiter circuit 1 that works effectively to maintain stable circuit operation
The output of 55 is supplied to loop filter 16.

The roof filter 16 determines the stability, convergence time, etc. of the feedback loop system. In this embodiment, the phase error signal (ERJ) K from the limiter circuit 155 is multiplied by a coefficient a in a coefficient multiplier 161. , t, coefficient multiplier 1
The coefficient is multiplied by 65. Coefficients a and b set the loop filter 160 time constant. Coefficient multiplier 16
The output of 1 is integrated by an integrating circuit consisting of an adder 162 and a latch circuit 163.The integrated output is integrated by an adder 164.
, it is added to the output of the coefficient multiplier 165.

The output of the loop filter 16 is a horizontal periodic signal (CH
) is output. The horizontal periodic signal (CM) provides the oscillation period of the digitally controlled oscillator 17.

The horizontal periodic signal (CH) is divided into an integer component CHI (upper bit) and a decimal component: CHj) (lower bit).
CH2) is supplied to adder 114. Integer component (CH
ri indicates the clock φS unit oscillation period, and the fractional acid @ C
M') means an oscillation cycle within the clock -S01 cycle. In the adder 113, the integer value &CHJ) is added to the horizontal standard period value. Further, the adder 174 and the latte circuit 175 constitute an integrating circuit. The carry (CRT) of adder 114 is then added to adder 113.

Now, the horizontal counter 11 is clocked φS in one horizontal period.
It is assumed that 910 are counted. Here, assuming that no phase error occurs at any location, the horizontal periodic signal (CM
) are all 0. Here, the horizontal standard period value is 9
If 10 is set, then from the - number output circuit 112,
The horizontal counter 111 counts 910 times φS, and at the 9th point, a coincidence pulse (R8) is obtained. This coincidence pulse (R8) is used as a reset signal for the horizontal counter 171 and as a latch/intermediate pulse for the latch circuit 175.

Now, suppose that a phase shift of 1 clock φS occurs in 4 horizontal periods, then as a decimal adjustment (■), φ
Data for 0.25 minutes of S period is collected. This data is accumulated in the integrating circuit and is 4X0.25 (4 horizontal periods).
The result is 111, which is input to the adder 113 as a carry. Therefore, at this time, the horizontal counter 111 is 9
When counting 10+1, it is reset by a coincidence pulse (R8). Since the output of the latch circuit 175 is also given to the subtracter 153 of the horizontal phase error detection circuit 15, it is as if one cycle of the loop 8 is further broken down. , perform phase correction,
The output of the latch circuit 175 is a horizontal counter correction signal (HaΔD).

The explanation will be returned to FIG. 1. The above circuit first obtains the phase error of the horizontal synchronization detection signal (H8) that exists due to the sampling period of the clock φS, and then corrects the phase of the horizontal count output with an accuracy higher than the period of the clock φS. .

Furthermore, correction can be made so that the phase of the horizontal count output has a predetermined phase with respect to the horizontal synchronization signal of the video signal.

The above-described horizontal counter correction signal (HCΔτ) and horizontal count output (HCTR) are provided by the horizontal driver 41 circuit 21,
The signal is supplied to a flyback phase error detection circuit 19.

The flyback phase error detection circuit 19 detects the frequency of the television receiver's 7: Fiback pulse (HFB),! : Used to set the phase relationship with the horizontal synchronization signal to a predetermined phase. First, the phase of the flyback pulse (B) and the sampling clock φS within one cycle is detected. This detection circuit is a sampling clock phase detection circuit 18.
It is.

The sampling clock phase detection circuit 18 generates a flyback phase correction signal (FBΔτ).

A read timing pulse (FBT) of this signal is supplied to the flyback phase error detection circuit 19. The flyback phase error detection circuit 19 outputs a horizontal counter output (HC
Detect the phase difference information between the timing pulse (TR) and the timing pulse (FBT) (synchronized with the sampling clock).
Next, the phase difference information is corrected using the flyback phase correction signal (FBΔτ) and the horizontal counter correction signal (HCΔτ). Furthermore, the phase difference information corrected in this way is corrected by a horizontal plane vertical position control signal (HPH) K. Horizontal screen position information (HPH) is a signal given by an external operation in order to adjust the double-sided position according to the characteristics of the consort aircraft and according to Ede's preference.

The flyback phase error detection circuit 19 described above obtains a 79 Ipac phase error signal (ER2). This signal (ER) is passed through a two-stroke loop filter 20 to a horizontal drive flywheel arm phase control signal (DFB).
) and supplied to the horizontal drive generation circuit 21. The horizontal drive generation circuit 21 has a horizontal drive width counter explained in FIG. 7 and a comparator that compares a horizontal drive width control signal (HPW) to obtain a horizontal drive pulse (HD). In this case, horizontal drive/4
The phase of the pulse (HD) is determined by the phase relationship with the horizontal counter 171 (shown in FIG. 4) and the phase of the flyback/4 pulse (HF
B) has a predetermined phase relationship. Here, the horizontal counter 111 has its phase relationship with the horizontal synchronizing signal corrected to a predetermined relationship, and the flyback pulse (H
Phase information within one period of the sampling clock φS of FB) is also obtained. Therefore, the horizontal drive-Mallus (
ED), phase control can be obtained with accuracy higher than that of the clock φS.

The configurations of the above-described inter-clock phase detection circuit 18, flyback phase error detection circuit 19, loop filter 20, and horizontal drive generation circuit 21 will be explained in more detail.

FIG. 5 shows the inter-clock phase detection circuit 18,
FIG. 6 is a time chart for explaining the operation.

The flyback pulse (H) FB) is input to the input terminal 181.
The signal is supplied to the dart delay circuit 182 via the . r-
The delay circuit 182 is a non-inverter with a delay amount of approximately 1/16 of the sampling clock φS.
This is a series circuit of six f-) delay elements. Therefore, each f
-) The outputs (dJ to d16) of the delay elements are shifted by 16" of one cycle of the sampling clock φS, as shown in FIG.

The output (dJ to d16) is supplied to a two-way circuit 183 that latches it at the rising edge of the sampling clock φS. The two-way circuit 183 has outputs 1 to 16 corresponding to d1 to dot, and only output 10 is the latch circuit 18.
4, and the other outputs (.2 to..16) are supplied to the latch circuit 185. The latch circuit 184 doubles .multidot.1 at the rising edge of the sampling clock φS, and supplies the output to the clock input terminal ' of the latch circuit 185. In addition, the output of the latch circuit 184 is the timing pulse (
FBT).

The output (fj to f16) of the latch circuit 185 is supplied to a counting circuit 186. This counting circuit 186 has an output (f
2 to 116) O @1m is counted and the value is output as a flyback phase correction signal (FBΔτ).

Now, as shown in FIG. 6, at the rising edge (tgz) of the sampling clock φS, the flyback
Suppose that the phase information of FB ) is latched. However, the actual flyback pulse (FBT) is
) has risen at a time point (tgo) K earlier than ), so one ER in the figure corresponds to the flyback phase correction amount.

Therefore, by counting the number of @11 in the two-way circuit 185, this can be used as a phase correction signal. Since the phase correction signal (FBΔτ) needs to be read within one cycle of the sampling clock φSo, the timing pulse (FB'r) is configured to rise at the falling edge (t#J) of the sampling clock φS.

FIG. 7 shows the flyback phase error detection circuit 19, dip filter 20, and horizontal drive generation circuit 21.

The count output (HCTR) from the horizontal counter 171 in the horizontal phase error detection circuit 15 is doubled in the latch circuit 191 at the rising edge of the previous timing pulse (FBT). This allows the horizontal counter output (HC
TR) and phase information of the timing pulse (FBT) can be obtained. The output of latch circuit 191 is supplied to subtracter 192. The subtracter 192 subtracts the flyback phase correction signal (FBΔτ) from the output of the latch circuit 191. Furthermore, the output of the subtracter 192 is the subtracter 1ssyc.
Here, the phase correction signal (HeΔτ) of the horizontal counter 171 is subtracted.

As a result, phase information can be corrected in units smaller than one cycle of the sampling clock φS. Furthermore, the output of subtractor 192 is supplied to subtracter 194, where:
The error between the horizontal screen position control signal (HPH) and the horizontal screen position control signal (HPH) is calculated. The output of subtractor 194 is fed to limiter 195 to limit large errors and is derived as a flyback phase error signal (ER2).

The flyback phase error signal (ER2) is multiplied by a coefficient C in the coefficient multiplier 201 of the loop filter 20, and the resulting signal is integrated in an integration circuit composed of an adder 202 and a latch circuit 203. . And the integral output is
Phase control signal between horizontal drive and 7-ray park nose (
DFB), the subtracter 21 of the drive generation circuit 21
1.

The horizontal drive generation circuit 21 maintains a predetermined phase relationship between the flyback/4 pulse whose phase error is detected as described above and the horizontal drive nodal pulse (HD).

The phase control signal (DFB) is input to a subtracter 211. This subtracter 211 receives a horizontal screen position control signal (H
PH) is supplied. In the attenuator 211, the horizontal drive signal from the horizontal screen position control signal (HPH)
The flyback interpulse phase control signal (DFB) is subtracted to determine the rising phase of the horizontal drive generation circuit.

The subtracter 211 corrects the delay of the flyback pulse.

Next, the output of the subtracter 211 is supplied to an adder 212 and added to the horizontal counter phase correction signal (HCΔτ). This is because the sampling clock φS is 1 time before the comparison with the horizontal counter output (HCTR) in units of φ8.
This is to improve the accuracy of the horizontal drive pulse (HD) by correcting it with an accuracy one finer than the period.

Integer portion of the upper bits of the output of the adder 211 (CFJ)
is supplied to the matching circuit JJJ, and the decimal fraction σ of the lower C cut is
F2) is given to the selection circuit 217 as a control signal.

In the matching circuit 213, a reset pulse (R8J) is obtained when the integer fraction (CFJ) and the horizontal count output (HCTR) match, and this reset pulse (
R8,? ) resets the horizontal drive width counter 214.

By being reset, the horizontal drive width counter 214 causes the drive f pulse (we) to rise in units of φS and counts the clock φB. This count value is converted into a horizontal drive and drive width control signal (HPW) by a comparator 215.
) compared to .

Comparator 215 outputs a horizontal drive width control signal (HPW
), when the value of the output of the horizontal drive width counter 214 becomes larger than that, the drive generation circuit (HDS) is caused to fall.

The drive generation circuit (HD8) is r-)f ishi circuit 2
16. This dirt delay circuit 216 is
It has the same configuration as the f-) delay circuit 182 shown in FIG. 5, and obtains a plurality of dry horn pulses having a phase with finer precision than the period of the clock φS. Any one of the plurality of drive generation circuits is selected by the selection circuit 211
is selected and output as a true horizontal drive norm (HD). The selection circuit 211 determines a selection pulse according to the fractional component (CF2) from the adder 212. That is, the horizontal drive noculus (HD) is controlled to a phase with finer precision than the period of the sampling clock φS.

The above horizontal flyback phase error detection circuit 19, flyback phase error detection circuit 19,
As shown in FIG. ) to match the point in time (t#J). For this reason, after the horizontal drive nolus (HD) is generated,
The time delay information until the horizontal flyback pulse (HFB) is obtained, that is, DFB, is detected by the phase error detection circuit 19,
obtained by loop filter 20.

In this case, the phase of the timing information obtained from the flyback pulse is subjected to a finer phase correction than the clock φS, and the count information obtained from the count output of the horizontal counter 171 is also subjected to a finer phase correction than the clock φS. There is. Based on the horizontal drive/flyback phase control signal (DFB) K, the phase of the horizontal drive/fourth pulse (HD) is determined with high accuracy.

FIG. 9 shows the circuit of FIG. 7 further divided into blocks. As shown in FIG. 9, the synchronization means 31 synchronizes the horizontal flyback pulse (HFB) with the sampling clock (φS).

Next, in the correction signal generating means 32, the flyback/
A flyback phase correction signal (FBΔτ) is obtained which is the difference between the phase of the synchronization signal of the parent pulse (HFB) and the predetermined phase of the sampling clock (φS).

On the other hand, the horizontal drive means 34 uses a horizontal synchronization signal to
A horizontal drive of 14 lus (HD) is generated. Furthermore, the phase of the horizontal drive/mother pulse (HD) is
It is controlled by the flyback pulse phase control signal (DFB). The horizontal drive/7-ray packet noise phase control signal (DFB) is obtained by integrating the phase difference between the timing signal (FBF) synchronized with the period of the sampling clock φS, the horizontal synchronization signal, and '□ by the phase control means 33. It is obtained by K.

Therefore, a flyback phase correction signal FBΔ which collects phase information of the flyback pulse (HFB) in units finer than the cycle of the sampling clock φS is further input to the phase control means 33, and the phase control means 33 By correcting the signal (DFB), the flyback pulse (
It is possible to reduce horizontal jitter caused by HFB).

[-Ming effect]

As explained above, the present invention detects a horizontal periodic signal with high precision, detects phase correction information with a resolution greater than the period of a sampling clock, and uses a horizontal synchronization detection circuit to
Effective for highly accurate phase correction.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing an embodiment of the present invention, FIG. 2 is an operation waveform diagram shown for obtaining a horizontal synchronization correction signal, and FIG. 3 is a detailed diagram of the inter-clock phase detection circuit shown in FIG. 1. Figure shown. FIG. 4 is a diagram showing in more detail the horizontal synchronization reproduction signal generation section which is the first cause, FIG. 5 is a diagram showing in detail the phase detection circuit between flyback clocks in FIG. 1, and FIG. Operation waveform diagram; Figure 7 is a diagram showing the horizontal drive pulse generation section of Figure 1 in more detail; Figure 8 is a waveform diagram showing the operation of the circuit in Figure 1; Figure 9 is a diagram showing the operation of the circuit in Figure 1;
8 is a block diagram showing the circuit of FIG. 7; FIG. DESCRIPTION OF SYMBOLS 11... Analog-digital converter, 12... Synchronization separation circuit, 13... Phase detection circuit between sampling clocks, 14... Horizontal synchronization detection circuit, 15... Horizontal phase error detection circuit, 16.・Horizontal loop filter, 11
...Digital control oscillator, J 8-...Sampling clock phase detection circuit, 19...Flyback phase error detection circuit, 20...Flyback Frug filter, 21...Horizontal drive generation circuit/Machi No. Figure 1 Figure 2 Figure 3

Claims (2)

[Claims] (1) An analog-to-digital converter that converts an analog video signal into a digital video signal at a predetermined sampling clock, and a sync separation circuit that separates the sync signal from the digital video signal at a predetermined sync separation level to obtain a composite sync signal. and a horizontal synchronization detection circuit that detects a horizontal synchronization signal from the composite synchronization signal and outputs a horizontal synchronization detection signal synchronized with the sampling clock period, and inputs the horizontal synchronization detection signal, the synchronization separation level, and the digital video signal. year,
an inter-sampling clock phase detection circuit that detects a phase correction signal of the horizontal synchronization detection signal using the value of the synchronization separation level and the values of the digital video signal before and after the synchronization separation level; and the horizontal synchronization detection signal and the phase correction signal. A digital horizontal synchronization circuit, comprising means for correcting the phase of the horizontal synchronization oscillation output using the phase correction signal. (2) The sampling clock phase detection circuit uses the values (DA) (DB) of the digital video signal before and after the value (SEP) of the synchronization separation level to detect (DB
2. The digital horizontal synchronization circuit according to claim 1, further comprising an arithmetic circuit that performs an arithmetic operation of -SEP)/(DB-DA) and uses the result as the phase correction signal (CSΔτ).