JPS61253893A - Circuit pattern formation - Google Patents

Circuit pattern formation

Info

Publication number
JPS61253893A
JPS61253893A JP9488585A JP9488585A JPS61253893A JP S61253893 A JPS61253893 A JP S61253893A JP 9488585 A JP9488585 A JP 9488585A JP 9488585 A JP9488585 A JP 9488585A JP S61253893 A JPS61253893 A JP S61253893A
Authority
JP
Japan
Prior art keywords
circuit pattern
insulating layer
sides
substrate
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9488585A
Other languages
Japanese (ja)
Inventor
渡辺 喜夫
健治 大沢
昭一 村本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP9488585A priority Critical patent/JPS61253893A/en
Publication of JPS61253893A publication Critical patent/JPS61253893A/en
Pending legal-status Critical Current

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  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 A、産業上の利用分野 本発明は絶縁層を挾んで両面にそれぞれ回路パターンを
形成する際に用いられる回路パターン形成方法に関し、
特に絶縁層の厚みが厚い場合における両面パターン間の
電気的接続方法を改善したものである。
DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to a circuit pattern forming method used when forming circuit patterns on both sides of an insulating layer.
This is an improved method of electrical connection between patterns on both sides, especially when the thickness of the insulating layer is thick.

B6発明の概要 本発明は、絶縁層を挾んで両面にそれぞれ回路パターン
を形成する際に用いられる回路パターン形成方法におい
て、エツチングにより回路パターンを形成し、部分的に
絶縁層を薄膜化し、貫通孔を形成した後に、電解メッキ
を施すことによって、パターンの肉付けと両面パターン
間の電気的接続を同時に行うことができると共に、導体
抵抗の低い微細なパターンを容易に得ることができるよ
うにしたものである。
B6 Summary of the Invention The present invention is a circuit pattern forming method used to form circuit patterns on both sides of an insulating layer, in which a circuit pattern is formed by etching, the insulating layer is partially thinned, and through holes are formed. By applying electrolytic plating after forming the pattern, it is possible to simultaneously thicken the pattern and make electrical connections between the patterns on both sides, and it is also possible to easily obtain a fine pattern with low conductor resistance. be.

C5従来の技術 従来より、絶縁層を挾んでその両面にそれぞれ回路パタ
ーンの形成されたいわゆる両面基板が一般に知られてい
る。この両面基板における回路パターンは、通常、絶縁
層の両面に設けられた銅等の金属箔等に対して選択的に
エツチングを施すことにより形成される。
C5 Prior Art Conventionally, so-called double-sided substrates in which circuit patterns are formed on both sides of an insulating layer are generally known. The circuit pattern on this double-sided board is usually formed by selectively etching metal foils such as copper provided on both sides of the insulating layer.

D2発明が解決しようとする問題点 ところで、上記両面基板においては、両面に形成された
回路パターン間の電気的接続(導通)を図ることが一般
に必要である。この電気的接続は、たとえば、回路パタ
ーンの存在する基板の所定部分にスルーホールとなる貫
通孔を設け、絶縁層の壁面にパラジウムコロイド等で無
電解メッキを施し金属化した後、電解メッキを施すこと
により行われている。しかし、この方法では、無電解メ
ッキによる物質を貫通孔内のみに析出させることは難し
く、貫通孔以外の部分をマスキングする必要があるなど
、製造工程が極めて複雑となりコストアップの原因とな
っている。
D2 Problems to be Solved by the Invention By the way, in the above-mentioned double-sided substrate, it is generally necessary to establish electrical connection (continuity) between the circuit patterns formed on both sides. This electrical connection can be made, for example, by creating a through hole in a predetermined part of the board where the circuit pattern is present, electrolessly plating the wall surface of the insulating layer with palladium colloid, etc. to metallize it, and then electrolytically plating it. This is done by However, with this method, it is difficult to deposit the electroless plating substance only inside the through-hole, and it is necessary to mask areas other than the through-hole, which makes the manufacturing process extremely complicated and increases costs. .

また、微細な回路パターンを形成するには、元となる金
属箔層が薄いことが要求されるが、薄いと導体抵抗が高
いという難点があり、容易に微細なパターンを得ること
ができないという問題点がある。
In addition, in order to form fine circuit patterns, the metal foil layer that serves as the base must be thin, but if it is thin, the conductor resistance is high, making it difficult to easily obtain fine patterns. There is a point.

そこで、本発明は上述した従来の問題点に鑑みて提案さ
れたものであり、特に、絶縁層の厚みが厚い場合でも両
面の回路パターン間の電気的接続が容易に行えるような
回路パターン形成方法を提供することを目的とする。ま
た、本発明は導体抵抗の低い微細な回路パターンが容易
に得られるような回路パターン形成方法を提供すること
を他の目的とする。
Therefore, the present invention has been proposed in view of the above-mentioned conventional problems, and in particular, it provides a circuit pattern forming method that allows easy electrical connection between circuit patterns on both sides even when the thickness of the insulating layer is thick. The purpose is to provide Another object of the present invention is to provide a method for forming a circuit pattern by which a fine circuit pattern with low conductor resistance can be easily obtained.

E1問題点を解決するための手段 本発明に係る回路パターン形成方法は、上述した目的を
達成するために、絶縁層を挾んで両面に金属箔層を形成
した基板において、上記両面の金属箔層にエツチングを
施し各々の面内でそれぞれ一体導通をなす回路パターン
を形成する工程と、上記基板の所定部分を加圧して上記
絶縁層を薄膜化する工程と、上記基板の所定部分に貫通
孔を形成する工程と、上記回路パターンに対して電解メ
ッキを施す工程とから成り、上記貫通孔を介して両面の
回路パターン間の電気的接続を図ることを特徴とするも
のである。
Means for Solving Problem E1 In order to achieve the above-mentioned object, the circuit pattern forming method according to the present invention provides a circuit pattern forming method according to the present invention, in which a metal foil layer is formed on both sides of a substrate with an insulating layer sandwiched therebetween. a step of etching the substrate to form a circuit pattern that is integrally conductive within each surface; a step of pressurizing a predetermined portion of the substrate to thin the insulating layer; and a step of forming a through hole in a predetermined portion of the substrate. It consists of a step of forming the circuit pattern and a step of electrolytically plating the circuit pattern, and is characterized in that the circuit patterns on both sides are electrically connected through the through hole.

11作用 本発明によれば、両面に回路パターンの形成された基板
の所定部分における絶縁層が薄膜化され、貫通孔が形成
された後に、該回路パターンの表面にたとえば銅等の金
属が電解メッキによって析出される。
11.According to the present invention, after the insulating layer at a predetermined portion of a substrate on which circuit patterns are formed on both sides is thinned and through holes are formed, a metal such as copper is electrolytically plated on the surface of the circuit pattern. It is precipitated by

G、実施例 以下、本発明に係る回路パターン形成方法の一実施例に
ついて図面を用いて詳細に説明する。
G. Example Hereinafter, an example of the circuit pattern forming method according to the present invention will be described in detail with reference to the drawings.

まず、第1図に示すように、絶縁層1の両面に銅箔層2
A、2Bが形成された基板を用意する。
First, as shown in FIG.
A substrate on which A and 2B are formed is prepared.

上記絶縁層1には、たとえばポリイミド、ポリアミド、
ポリエステル、ポリブタジェン等の材料を用いることが
でき、厚みTOIは15〜100μm程度である。また
、上記銅箔層2A、 2Bは電解メッキ、圧延等による
ものであり、厚みToeは5〜40μm程度である。
The insulating layer 1 may be made of, for example, polyimide, polyamide,
Materials such as polyester and polybutadiene can be used, and the thickness TOI is about 15 to 100 μm. Further, the copper foil layers 2A and 2B are formed by electrolytic plating, rolling, etc., and have a thickness Toe of about 5 to 40 μm.

次に、第2図に示すように、フォトレジスト3A、3B
をパターニングする。上記フォトレジスト3A、3Bに
は、液状レジストを用いるのが好ましいが、ドライフィ
ルムレジストを用いることもできる。
Next, as shown in FIG. 2, photoresists 3A and 3B are
pattern. Although it is preferable to use a liquid resist as the photoresists 3A and 3B, a dry film resist can also be used.

゛ 次に、エツチング処理を施し、フォトレジスト3A
、3Bを剥離して、第8図に示すような回路パターン4
A、4Bを形成する。上記エツチング処理は、たとえば
1.塩化第二鉄あるいは塩化第二銅等のエツチング液を
用い、2kl?/cm程度の条件でスプレー法により行
うようにすれば良い。
゛ Next, an etching process is performed and the photoresist 3A is
, 3B is peeled off to form a circuit pattern 4 as shown in FIG.
A, form 4B. The above etching process may be performed in, for example, 1. Using an etching solution such as ferric chloride or cupric chloride, 2kl? It may be carried out by a spray method under conditions of about /cm.

次に、基板の所定部分、本実施例においては心中中央部
分を加圧して絶縁層1を薄膜化した後、第4(2)に示
すように、スルーホールとなる貫通孔5を形成する。上
記基板の加圧は、たとえば、プレス圧500〜2000
 kli / cm2%温度20〜250℃程度の条件
で加圧プレスにより行えば良い。
Next, after the insulating layer 1 is thinned by applying pressure to a predetermined portion of the substrate, in this embodiment, the central portion thereof, a through hole 5 serving as a through hole is formed as shown in No. 4 (2). The pressure applied to the substrate is, for example, a press pressure of 500 to 2000.
It may be carried out using a pressure press at a temperature of about 20 to 250°C at kli/cm2%.

また、上記貫通孔5は、たとえばドリルを用いて0.5
〜1.5mm程度の径に形成すれば良い。なお、加圧し
ながらパンチング式に貫通孔5を形成することもできる
Further, the through hole 5 is formed by using a drill, for example, with a diameter of 0.5 mm.
It may be formed to have a diameter of about 1.5 mm. Note that the through holes 5 can also be formed by punching while applying pressure.

そして、最後に、たとえば、硫酸銅あるいはピロリン酸
銅等のメッキ浴を用いて電解メッキを施し、回路パター
ン4A、4Bの表面に銅を析出させて、第5図に示すよ
うな最終的な回路パターン5A、6Bを得る。また、こ
の時、図示の如くスルーホール7が形成され両面の回路
パターン間の電気的接続(導通)も同時に行うことがで
きる。
Finally, electrolytic plating is performed using a plating bath such as copper sulfate or copper pyrophosphate to deposit copper on the surfaces of the circuit patterns 4A and 4B, resulting in the final circuit shown in FIG. Patterns 5A and 6B are obtained. Further, at this time, through holes 7 are formed as shown in the figure, and electrical connection (continuity) between the circuit patterns on both sides can be made at the same time.

硫酸銅メッキを行う場合の条件の一例を以下に示すO 温  度:20〜40℃ このような条件の下で電解メッキを行うことにより、1
0〜16μm程度のメッキ厚を得ることができる。
An example of the conditions for performing copper sulfate plating is shown below.
A plating thickness of about 0 to 16 μm can be obtained.

上述したように、本実施例の回路パターン形成方法は、
絶縁層1の両面に回路パターン4A、4Bの形成された
基板において、両面パターン間の電気的接続を図ろうと
する部分を加圧して絶縁層1を薄膜化し貫通孔5を形成
した後に、電解メッキを施して回路パターン4A、4B
の表面に銅を析出させるようにしたものであり、回路パ
ターン4A、4Bの肉付けと、両面パターン間の電気的
接続を同時に行うことができる。これは絶縁層1を薄膜
化したことにより無電解メッキを不要とし電解メッキの
みでの接続が可能となったからであり、特に、本実施例
のように絶縁層1の厚みTo!が厚い場合に大きな効果
が得られる。また、絶縁層1が薄い場合には加圧工程は
不要となることは勿論である。
As mentioned above, the circuit pattern forming method of this example is as follows:
In the substrate on which circuit patterns 4A and 4B are formed on both sides of the insulating layer 1, pressure is applied to the part where electrical connection between the patterns on both sides is to be made to thin the insulating layer 1 and through holes 5 are formed, and then electrolytic plating is performed. to create circuit patterns 4A and 4B.
Copper is deposited on the surface of the circuit patterns 4A and 4B, and the electrical connection between the patterns on both sides can be performed simultaneously. This is because the thinning of the insulating layer 1 eliminates the need for electroless plating and allows connection using only electrolytic plating.In particular, as in this embodiment, the thickness of the insulating layer 1 To! A great effect can be obtained when the thickness is thick. Furthermore, it goes without saying that if the insulating layer 1 is thin, the pressurizing step is not necessary.

更に、電解メッキにより回路パターン4A、4Bの肉付
けを行うことができるため、元となる銅箔層2A、2B
の厚みTocが薄くても最終的に得られる回路パターン
5A、 6Bは導体抵抗の低いものとなり、微細なパタ
ーンを容易に形成することができる。このような本実施
例の回路パターン形成方法は、たとえば、小型モータ用
のコイル(プリントコイル)を製造するのに用いて好適
であ 4゜す、コストの低減化も図れる。
Furthermore, since the circuit patterns 4A and 4B can be fleshed out by electrolytic plating, the original copper foil layers 2A and 2B can be thickened.
Even if the thickness Toc is small, the circuit patterns 5A and 6B finally obtained have low conductor resistance, and a fine pattern can be easily formed. The circuit pattern forming method of this embodiment is suitable for use in manufacturing coils (printed coils) for small motors, for example, and can also reduce costs.

なお、エツチングζこよる回路パターン4A、4Bの形
成工程、加圧による絶縁層1の薄膜化工程、および貫通
孔5の形成工程については頴序を任意に設定することが
できる。
Note that the process of forming the circuit patterns 4A and 4B by etching ζ, the process of thinning the insulating layer 1 by applying pressure, and the process of forming the through holes 5 can be arbitrarily set.

H0発明の効果 上述した実施例の説明から明らかなように、本発明によ
れば、絶縁層の両面に回路パターンの形成された基板の
所定部分を加圧して絶縁層を薄膜化し、貫通孔を形成し
た後に、電解メッキを施すことによって、絶縁層の厚み
が厚い場合でも回路パターンの肉付けと両面パターン間
の電気的接続を同時に行うことができる。また、電解メ
ッキによって回路パターンの肉付けが行え導体抵抗を低
くすることができるため、元の金属箔層は薄くても良(
導体抵抗の低い微細な回路パターンを容易に得ることが
できる。
H0 Effects of the Invention As is clear from the description of the embodiments described above, according to the present invention, a predetermined portion of a substrate on which a circuit pattern is formed on both sides of the insulating layer is pressurized to thin the insulating layer, and a through hole is formed. By applying electrolytic plating after formation, even if the insulating layer is thick, it is possible to simultaneously thicken the circuit pattern and make electrical connections between the double-sided patterns. In addition, because electrolytic plating can thicken the circuit pattern and lower conductor resistance, the original metal foil layer may be thin (
A fine circuit pattern with low conductor resistance can be easily obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1〜第5図は本発明の一実施例を工程順に示す各断面
図である。 1・・・・・・・・・・・・絶縁層 2A、2B・・・・・・銅箔層
1 to 5 are cross-sectional views showing an embodiment of the present invention in the order of steps. 1......Insulating layer 2A, 2B...Copper foil layer

Claims (1)

【特許請求の範囲】  絶縁層を挾んで両面に金属箔層を形成した基板におい
て、 上記両面の金属箔層にエッチングを施し各々の面内でそ
れぞれ一体導通をなす回路パターンを形成する工程と、 上記基板の所定部分を加圧して上記絶縁層を薄膜化する
工程と、 上記基板の所定部分に貫通孔を形成する工程と、上記回
路パターンに対して電解メッキを施す工程とから成り、 上記貫通孔を介して両面の回路パターン間の電気的接続
を図ることを特徴とする回路パターン形成方法。
[Scope of Claims] A step of etching the metal foil layers on both surfaces of a substrate having metal foil layers formed on both sides with an insulating layer sandwiched therebetween to form a circuit pattern that is integrally conductive within each surface; The method comprises the steps of: applying pressure to a predetermined portion of the substrate to thin the insulating layer; forming a through hole in a predetermined portion of the substrate; and electrolytically plating the circuit pattern. A method for forming a circuit pattern, the method comprising making an electrical connection between the circuit patterns on both sides through holes.
JP9488585A 1985-05-02 1985-05-02 Circuit pattern formation Pending JPS61253893A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9488585A JPS61253893A (en) 1985-05-02 1985-05-02 Circuit pattern formation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9488585A JPS61253893A (en) 1985-05-02 1985-05-02 Circuit pattern formation

Publications (1)

Publication Number Publication Date
JPS61253893A true JPS61253893A (en) 1986-11-11

Family

ID=14122495

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9488585A Pending JPS61253893A (en) 1985-05-02 1985-05-02 Circuit pattern formation

Country Status (1)

Country Link
JP (1) JPS61253893A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59197193A (en) * 1983-04-25 1984-11-08 旭化成株式会社 Method of producing through hole circuit board

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59197193A (en) * 1983-04-25 1984-11-08 旭化成株式会社 Method of producing through hole circuit board

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