JPS61248430A - Thin layer formation of compound semiconductor substrate - Google Patents
Thin layer formation of compound semiconductor substrateInfo
- Publication number
- JPS61248430A JPS61248430A JP8854885A JP8854885A JPS61248430A JP S61248430 A JPS61248430 A JP S61248430A JP 8854885 A JP8854885 A JP 8854885A JP 8854885 A JP8854885 A JP 8854885A JP S61248430 A JPS61248430 A JP S61248430A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- etching
- compound semiconductor
- glass plate
- etched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 150000001875 compounds Chemical class 0.000 title claims description 16
- 230000015572 biosynthetic process Effects 0.000 title 1
- 238000005530 etching Methods 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 abstract description 10
- 239000011521 glass Substances 0.000 abstract description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 3
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 abstract 1
- 239000000203 mixture Substances 0.000 abstract 1
- 235000011149 sulphuric acid Nutrition 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 102220043690 rs1049562 Human genes 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67075—Apparatus for fluid treatment for etching for wet etching
- H01L21/67086—Apparatus for fluid treatment for etching for wet etching with the semiconductor substrates being dipped in baths or vessels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、半導体基板の薄層化法に係わる。特に簡便に
かつ均一にエツチングするための化合物半導体基板の薄
層化法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for thinning a semiconductor substrate. In particular, the present invention relates to a method for thinning a compound semiconductor substrate for simple and uniform etching.
Ｇ ａ Ａ ｓ高周波、高出力Ｆ Ｅ Ｔ （Ｆｉｅｌ
ｄ ＥｆｆａｃｔＴｒａｎｃｉｓｔｏｒ ）ではソース
・インダクタンスを小さくシ、熱の放出を促すために、
ヴイア ホール（１／１ａ−Ｈｏｌｅ） が多く採用
されている。ヴイアホール（Ｖｉａ −１４ｏｌｅ ）
を形成するためには化合物半導体基板表面に素子を
形成した後裏面をエッチして１０〜５０μｍ厚みの均一
な化合物半導体基板を得なければならない。G a As high frequency, high output FET (Fiel
In order to reduce the source inductance and promote heat release,
Via hole (1/1a-Hole) is often used. Via Hall (Via-14ole)
In order to form a compound semiconductor substrate, it is necessary to form a device on the front surface of the compound semiconductor substrate and then etch the back surface to obtain a uniform compound semiconductor substrate with a thickness of 10 to 50 μm.
半導体基板を傾体てエツチングする例を示すものとして
公開公報特開昭４９−３５７５号が挙げられる。An example of etching a semiconductor substrate by tilting it is disclosed in Japanese Patent Application Laid-Open No. 49-3575.
この公知例ではエツチング液を流下させて均一なエツチ
ングを行なっているが１本発明によれば、後述するよう
に半導体基板を傾斜させ、ゆっくり回転させることによ
って簡便にかつ均一にエツチングできる。In this known example, uniform etching is performed by letting the etching solution flow down, but according to the present invention, etching can be easily and uniformly performed by tilting the semiconductor substrate and rotating it slowly as described later.
本発明の目的は化合物半導体基板を１０〜５０μｍの厚
さまで簡便にかつ均一に薄くする方法を提供することに
ある。An object of the present invention is to provide a method for simply and uniformly thinning a compound semiconductor substrate to a thickness of 10 to 50 μm.
半導体基板の裏面をエツチングして１０〜５０μｍに薄
くする方法としては１機械的なもの、化学的なもの、そ
してこれらを組み合わせてものとがある。化学的な方法
は結晶にひずみが入ることも少なく、エツチング速度も
かなり大きくすることができ、短時間で薄くすることが
可能である。Methods for etching the back surface of a semiconductor substrate to a thickness of 10 to 50 .mu.m include mechanical methods, chemical methods, and a combination of these methods. Chemical methods are less likely to cause distortion in the crystal, and the etching rate can be considerably increased, making it possible to thin the crystal in a short time.
化学的なエツチングの問題は、特にエツチング速度を大
きくした時、化合物半導体基板全体にわたって均一な厚
みにエツチングすることが難しいことである。A problem with chemical etching is that it is difficult to etch to a uniform thickness across the entire compound semiconductor substrate, especially when the etching rate is increased.
本発明は、半導体基板のエツチングする面以外の主表面
を当該エツチング液に対し保護し、該半導体基板を傾け
て（その傾斜角度が６０〜７５度の範囲になるように傾
けてるのが良い）、且回転させながらエツチングするも
のである。In the present invention, the main surface of the semiconductor substrate other than the surface to be etched is protected from the etching solution, and the semiconductor substrate is tilted (preferably, the tilt angle is in the range of 60 to 75 degrees). , and etching is performed while rotating.
本発明の方法によれば、化合物半導体基板を傾けること
により反応生成物が化合物半導体基板の表面に沿って流
れるため水平に静置するより均一にエツチングできる。According to the method of the present invention, by tilting the compound semiconductor substrate, the reaction products flow along the surface of the compound semiconductor substrate, so that etching can be more uniform than when the compound semiconductor substrate is left standing horizontally.
回転を加えることにより厚みのばらつきが平均化されさ
らに均一性よくエツチングできる。By applying rotation, variations in thickness are averaged out, allowing for more uniform etching.
〔発明の実施例〕 以下本発明の実施例を第１図、第２図により説明する。[Embodiments of the invention] Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.
第２図は第１図の直面の方向からの断面図である。FIG. 2 is a sectional view taken from the plane of FIG. 1.
第１図に示すように、ガラス板（２）にはりっけたＧ
ａ Ａ ｓ半導体基板（３）をエツチング治具（１）に
７０度傾けてビー力（４）内に立て。As shown in Figure 1, the G plated on the glass plate (2)
a As Semiconductor substrate (3) is tilted 70 degrees to the etching jig (1) and placed within the beam force (4).
Ｈ，ＳＯ，：Ｈ２Ｏ，：Ｈ２０＝１：８：４ ４０℃の
エツチング液（５）中で毎分０．１ 回転の速さで辺（
６）が辺（７）の位置になるように回転させる。エツチ
ングする以外の主面は、ガラス板（２）にはりつけられ
保護されている０本実施例によれば、４００μｍ厚みの
２インチＧ ａ Ａ ｓ半導体基板が第４図の厚み分布
でエツチングできる。H,SO,:H2O,:H20=1:8:4 Side (
Rotate so that 6) is at the position of side (7). The main surface other than that to be etched is protected by being attached to a glass plate (2). According to this embodiment, a 2-inch GaAs semiconductor substrate with a thickness of 400 μm can be etched with the thickness distribution shown in FIG.
第４図のＡ、Ｂ、Ｃは第３図に示したウェハ内の位置を
示している。また第５図に示すように半導体基板の傾斜
角度は６０〜７５度の時が厚みばらつきが最も小さくな
る。厚みばらつきは、ＧａＡｓ半導体基板の端がなくな
るまでエツチングした時の最も厚い部分の厚みである。A, B, and C in FIG. 4 indicate positions within the wafer shown in FIG. 3. Further, as shown in FIG. 5, the thickness variation is the smallest when the inclination angle of the semiconductor substrate is 60 to 75 degrees. The thickness variation is the thickness of the thickest portion when the GaAs semiconductor substrate is etched until the edge is removed.
本発明によれば、化合物半導体基板を、欠陥を導入する
ことなく、Ｓ便に７！！１つ均一に薄層化できる。According to the present invention, compound semiconductor substrates can be shipped by S-mail without introducing defects. ! One layer can be uniformly thinned.
第１図は、ガラス板にはりつけた化合物半導体を６０〜
７５度傾けてエツチング液中に置いた時の横断面図、第
２図は第１図の正面図、第３図は第４図の測定点の２イ
ンチ半導体基板中での代表点位置を摺示する図、第５図
は傾斜角度と厚みばらつきの関係を示す図である。
１・・・エツチング治具、２・・・ガラス板、３・・・
化合物半導体基板、４・・・ピー力、５・・・エツチン
グ液、６・・・ガラス板の一辺、７・・・ガラス板の一
辺。Figure 1 shows a compound semiconductor attached to a glass plate with 60~
A cross-sectional view when placed in an etching solution at an angle of 75 degrees, Figure 2 is a front view of Figure 1, and Figure 3 shows the representative point positions of the measurement points in Figure 4 on a 2-inch semiconductor substrate. The figure shown in FIG. 5 is a diagram showing the relationship between the inclination angle and the thickness variation. 1... Etching jig, 2... Glass plate, 3...
Compound semiconductor substrate, 4...Piece strength, 5...Etching liquid, 6...One side of the glass plate, 7... One side of the glass plate.
Claims (1)
り、他の主表面を当該エッチング液に対して保護しエッ
チング液中で該化合物半導体基板を傾けて、かつ回転さ
せながらエッチングする化合物半導体基板の薄層化法。When etching one main surface of a compound semiconductor substrate, the other main surface is protected from the etching solution, and the compound semiconductor substrate is etched while being tilted and rotated in the etching solution, thereby reducing the thickness of the compound semiconductor substrate. Law.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8854885A JPS61248430A (en) | 1985-04-26 | 1985-04-26 | Thin layer formation of compound semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8854885A JPS61248430A (en) | 1985-04-26 | 1985-04-26 | Thin layer formation of compound semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61248430A true JPS61248430A (en) | 1986-11-05 |
Family
ID=13945907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8854885A Pending JPS61248430A (en) | 1985-04-26 | 1985-04-26 | Thin layer formation of compound semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61248430A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109698123A (en) * | 2017-10-24 | 2019-04-30 | 山东浪潮华光光电子股份有限公司 | A kind of substrate etching method of GaAs base LED wafer |
-
1985
- 1985-04-26 JP JP8854885A patent/JPS61248430A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109698123A (en) * | 2017-10-24 | 2019-04-30 | 山东浪潮华光光电子股份有限公司 | A kind of substrate etching method of GaAs base LED wafer |
| CN109698123B (en) * | 2017-10-24 | 2020-09-18 | 山东浪潮华光光电子股份有限公司 | Substrate corrosion method of GaAs-based LED wafer |
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