JPS62283678A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62283678A JPS62283678A JP12565586A JP12565586A JPS62283678A JP S62283678 A JPS62283678 A JP S62283678A JP 12565586 A JP12565586 A JP 12565586A JP 12565586 A JP12565586 A JP 12565586A JP S62283678 A JPS62283678 A JP S62283678A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- light
- semiconductor substrate
- thin film
- incident direction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000005530 etching Methods 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000010409 thin film Substances 0.000 claims abstract description 13
- 239000010408 film Substances 0.000 abstract description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 8
- 239000013078 crystal Substances 0.000 abstract description 7
- 238000001259 photo etching Methods 0.000 abstract description 5
- 230000003287 optical effect Effects 0.000 abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- 238000001514 detection method Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- NWZSZGALRFJKBT-KNIFDHDWSA-N (2s)-2,6-diaminohexanoic acid;(2s)-2-hydroxybutanedioic acid Chemical compound OC(=O)[C@@H](O)CC(O)=O.NCCCC[C@H](N)C(O)=O NWZSZGALRFJKBT-KNIFDHDWSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- IKDUDTNKRLTJSI-UHFFFAOYSA-N hydrazine monohydrate Substances O.NN IKDUDTNKRLTJSI-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000003756 stirring Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
3、発明の詳細な説明
〔発明の利用分野〕
本発明は、薄膜構造を有する半導体装置、例えば、半導
体圧力センサ等を製造する方法に関し、特にエツチング
の制御技術に関するものである。[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a method of manufacturing a semiconductor device having a thin film structure, such as a semiconductor pressure sensor, and particularly relates to an etching control technique. It is.
薄膜構造を有する半導体装置としては、例えば、半導体
のピエゾ抵抗効果を利用した半導体圧力センサがある(
例えば特開昭60−225480等に記載)。An example of a semiconductor device having a thin film structure is a semiconductor pressure sensor that utilizes the piezoresistance effect of a semiconductor (
For example, as described in JP-A-60-225480, etc.).
第5図は、上記の半導体圧力センサの製造工程を示す図
である。FIG. 5 is a diagram showing the manufacturing process of the above semiconductor pressure sensor.
第5図において、まず、(A)では(100)結晶面を
有するn型のSi半導体基板1の上下両面に熱酸化法に
よって約700nmの酸化シリコン膜2および3を形成
する。In FIG. 5, first, in (A), silicon oxide films 2 and 3 of approximately 700 nm in thickness are formed on both upper and lower surfaces of an n-type Si semiconductor substrate 1 having a (100) crystal plane by thermal oxidation.
次に、(B)において、通常のフォトエツチング技術を
用いて所定部分の酸化シリコン膜を除去し、さらにイオ
ン注入法と高温熱処理によってp型の拡散抵抗領域4を
形成する。Next, in (B), a predetermined portion of the silicon oxide film is removed using a conventional photoetching technique, and a p-type diffused resistance region 4 is formed by ion implantation and high-temperature heat treatment.
次に、(C)において、真空蒸着法とフォトエツチング
によりM配線層5を形成し、化学気相成長法によってP
SG膜6を形成する。Next, in (C), an M wiring layer 5 is formed by vacuum evaporation and photoetching, and a P wiring layer 5 is formed by chemical vapor deposition.
SG film 6 is formed.
次に、(D)において、フォトエツチングによって酸化
シリコン膜3の所定部分を除去し、それをマスクとして
、例えば、抱水ヒドラジンをエツチング液とする結晶面
選択エツチング法によってSi半導体基板1をエツチン
グし、ダイアフラム部7を形成する。Next, in (D), a predetermined portion of the silicon oxide film 3 is removed by photoetching, and using this as a mask, the Si semiconductor substrate 1 is etched by a crystal plane selective etching method using, for example, hydrazine hydrate as an etching solution. , forming the diaphragm portion 7.
最後に(E)において、外部配線取り出し孔8を形成す
る。Finally, in (E), an external wiring extraction hole 8 is formed.
上記の一半導体圧カセンサは、圧力を印加することによ
ってダイアフラム部7が歪み、それによって拡散抵抗領
域4にピエゾ抵抗効果が生じ、その抵抗変化を検出する
ことによって圧力を検出するものである。In the one semiconductor pressure sensor described above, the diaphragm portion 7 is distorted by applying pressure, thereby producing a piezoresistance effect in the diffused resistance region 4, and pressure is detected by detecting the change in resistance.
上記のごとき従来の半導体装置の製造方法においては、
Si半導体基板1を所定時間エツチング液中に浸漬し、
かつ、エツチング液の温度と拡散状態を一定に維持する
ことによってダイアフラム部7を形成していた。In the conventional semiconductor device manufacturing method as described above,
Immersing the Si semiconductor substrate 1 in an etching solution for a predetermined time,
In addition, the diaphragm portion 7 was formed by maintaining the temperature and diffusion state of the etching solution constant.
しかし、エツチング中における二゛ツチング液の組成変
化およびSi半導体基板の加工形状変化に起因して、エ
ツチング速度が変化するのを避けることは出来ず、した
がって、所定の厚みを有するダイアフラム部7を形成す
るために必要なエツチング時間を選定することが極めて
困難であるという問題があった。However, it is impossible to avoid changes in the etching rate due to changes in the composition of the etching solution and changes in the processed shape of the Si semiconductor substrate during etching, and therefore, the diaphragm portion 7 having a predetermined thickness cannot be avoided. There has been a problem in that it is extremely difficult to select the etching time necessary for this purpose.
本発明は、上記のごとき従来技術の問題を解決するため
になされたものであり、エツチングの際に、必要とされ
る薄膜の厚さを正確、かつ容易に加工することの出来る
半導体装置の製造方法を提供することを目的とするもの
である。The present invention has been made in order to solve the problems of the prior art as described above, and is capable of manufacturing a semiconductor device that can accurately and easily process the required thin film thickness during etching. The purpose is to provide a method.
・ 上記の目的を達成するため、本発明においては、半
導体基板の薄膜構造以外の所定部分も薄膜構造と同時に
エツチングし、かつ、エツチング中に上記所定部分に光
を照射し、上記所定部分からの反射光または透過光の強
度を測定することによってエツチングの深さを検知し、
それに応じてエツチングを制御するように構成している
。- In order to achieve the above object, in the present invention, a predetermined portion of a semiconductor substrate other than the thin film structure is also etched at the same time as the thin film structure, and during etching, the predetermined portion is irradiated with light to remove light from the predetermined portion. The depth of etching is detected by measuring the intensity of reflected or transmitted light,
The structure is such that etching is controlled accordingly.
第1図は、本発明の一実施例図であり、前記第5図と同
様の半導体圧力センサを製造する場合に本発明を適用し
た例を示す。FIG. 1 is a diagram showing an embodiment of the present invention, and shows an example in which the present invention is applied to manufacture a semiconductor pressure sensor similar to that shown in FIG. 5.
第1図において、(A)では、まず、前記の従来方法と
同様にn型のSi半導体基板1の上下両面に酸化シリコ
ン膜2お、よび3を形成し、また、p型の拡散抵抗領域
4、Afi配線層5、PSG膜6を形成する。In FIG. 1, in (A), first, silicon oxide films 2 and 3 are formed on both upper and lower surfaces of an n-type Si semiconductor substrate 1, as in the conventional method described above, and a p-type diffused resistance region is formed. 4. Form Afi wiring layer 5 and PSG film 6.
次に、(B)に示すごとくフォトエツチングによってダ
イアフラム部7とエツチング終点検出領域9との部分の
酸化シリコン膜3を除去し、それをマスクとしてエツチ
ングを行なう。Next, as shown in (B), the silicon oxide film 3 in the portions of the diaphragm portion 7 and the etching end point detection region 9 is removed by photoetching, and etching is performed using this as a mask.
そして、エツチング中は、(C)に示すごとく、エツチ
ング終点検出領域9に光学系11を介して光源10から
垂直に光を照射し、その反射光を受光部12で検出する
。During etching, as shown in (C), the etching end point detection area 9 is irradiated with light perpendicularly from the light source 10 via the optical system 11, and the reflected light is detected by the light receiving section 12.
また、エツチング液としては、例えば、抱水ヒドラジン
のような結晶面選択エツチング液を用い、従来方法と同
様の温度および攪伴条件でエツチングを行なう。Further, as the etching solution, for example, a crystal face selective etching solution such as hydrazine hydrate is used, and etching is carried out at the same temperature and stirring conditions as in the conventional method.
上記のごとき結晶面選択エツチングによる異方性エツチ
ングを行なった場合には、エツチングによる加工形状が
(111)結晶面で囲まれたV字形の溝となる。When anisotropic etching is performed by crystal plane selective etching as described above, the etched shape becomes a V-shaped groove surrounded by (111) crystal planes.
また、7字形の溝の表面は鏡面になるので、この部分か
らの反射はほぼ正反射のみとなる。Further, since the surface of the figure 7 groove is a mirror surface, the reflection from this portion is almost exclusively regular reflection.
したがって、エツチングの途中で、破線9′に示すよう
な光の入射方向と垂直な面が残っている間は、入射方向
に対する反射光が生じるが、7字形の溝が完成すると入
射方向に対する反射は殆ど0になる。Therefore, during etching, while a surface perpendicular to the light incident direction remains as shown by the broken line 9', reflected light is generated in the incident direction, but once the figure 7-shaped groove is completed, there is no reflection in the incident direction. It becomes almost 0.
第3図は、上記のごときエツチングにおけるエツチング
時間と反射光強度との関係を示す図である。FIG. 3 is a diagram showing the relationship between etching time and reflected light intensity in the above etching.
第3図に示すごとく、7字形の溝が完成した時点で反射
光強度は大幅に低下する。As shown in FIG. 3, the reflected light intensity decreases significantly when the figure-7 groove is completed.
したがって、ダイアフラム部の厚さdが所望の値になっ
たときにV字形の溝が完成するように、エツチング終点
検出領域9の幅Wを設定しておけば、ダイアプラム部の
厚さdが所望の値になったとき反射光の検出強度が急変
することになるので、その点においてエツチングを終了
すればよい。Therefore, if the width W of the etching end point detection area 9 is set so that the V-shaped groove is completed when the thickness d of the diaphragm part reaches the desired value, the thickness d of the diaphragm part can be set to the desired value. Since the detected intensity of the reflected light changes suddenly when the value reaches , the etching may be terminated at that point.
すなわち、第1図の場合には、Si半導体基板1の厚さ
をり、目的とするダイアフラムの厚さをdとした場合に
、7字形の溝が完成した時の溝の深さがD−dになるよ
うにエツチング終点検出領域9の幅Wを設定してやれば
良い。In other words, in the case of Fig. 1, if the thickness of the Si semiconductor substrate 1 is equal to d and the thickness of the desired diaphragm is d, then the depth of the groove when the figure 7-shaped groove is completed is D-d. It is sufficient to set the width W of the etching end point detection area 9 so that the width W of the etching end point detection area 9 is satisfied.
この場合には、エツチング終点検出領域9の幅Wを、W
= 2 (D −d )/ tan54.7に設定す
ればよい。In this case, the width W of the etching end point detection area 9 is set to W
= 2 (D - d)/tan54.7.
第2図は、上記のごとき製造方法を行なうための装置を
示す図であり、13はエツチング層、14はエツチング
液である。FIG. 2 is a diagram showing an apparatus for carrying out the above manufacturing method, in which 13 is an etching layer and 14 is an etching solution.
次に、第4図は本発明の他の実施例図である。Next, FIG. 4 shows another embodiment of the present invention.
この実施例においては、まず、エツチング終点検出領域
9の部分のSi半導体基板1を予め所望のダイアフラム
の厚さ分dだけエツチングしておき、その後、ダイアフ
ラム部7とエツチング終点検出領域9とを同時にエツチ
ングする。In this embodiment, first, the Si semiconductor substrate 1 in the etching end point detection region 9 is etched in advance by a desired diaphragm thickness d, and then the diaphragm portion 7 and the etching end point detection region 9 are etched at the same time. Etching.
また、この場合には、(B)に示すごとく光源10から
の光をエツチング終点検出領域9に照射し。In this case, the etching end point detection area 9 is irradiated with light from the light source 10 as shown in FIG.
受光部12を用いて透過光を検出する。The transmitted light is detected using the light receiving section 12.
なお、この際のエツチング終点検出領域9の幅Wは、W
= 2 D /1an54.7に設定する。Note that the width W of the etching end point detection area 9 at this time is W
= 2D/1an54.7.
この実施例の場合には、ダイアフラム部の厚みが所望の
値dに達したときに、エツチング終点検出領域9の部分
ではV字形の溝がSi半導体基板1の上面まで到達し、
この時点で透過光の強度が急激に増加する。In the case of this embodiment, when the thickness of the diaphragm reaches the desired value d, the V-shaped groove reaches the upper surface of the Si semiconductor substrate 1 in the etching end point detection region 9.
At this point, the intensity of the transmitted light increases rapidly.
したがって、その時点を検出してエツチングを終了すれ
ばよい。なお、Si半導体基板1の表面に形成している
酸化シリコン膜2等は、厚さが極めて薄いので容易に光
を透過する。Therefore, it is sufficient to detect that point and terminate the etching. Note that the silicon oxide film 2 and the like formed on the surface of the Si semiconductor substrate 1 are extremely thin, so light easily passes through them.
なお、上記の実施例においては、結晶面選択エツチング
を用いて異方性エツチングを行なった場合を例示したが
、等方性のエツチングを行なう場合であっても前記の幅
Wを適宜設定することにより1本発明を適用することが
可能である。In addition, in the above embodiment, the case where anisotropic etching was performed using crystal plane selective etching was illustrated, but even when performing isotropic etching, the above-mentioned width W should be set appropriately. Accordingly, it is possible to apply the present invention.
また、前記の実施例においては、エツチングの終点を検
出するための領域を半導体′!A置のチップ表面上に設
ける場合を例示したが、これに限らず。Further, in the above embodiment, the area for detecting the end point of etching is the semiconductor'! Although the case where it is provided on the chip surface at position A is illustrated, the present invention is not limited to this.
例えば、スクラブライン内に設けることにより、従来と
同等の集積度を確保することが出来る。For example, by providing it within the scrub line, it is possible to ensure the same degree of integration as in the past.
また、前記の実施例においては、薄膜構造を有する半導
体装置として半導体圧力センサを例示したが、これに限
らず本発明は半導体装置めに薄膜構造部を有する全ての
半導体装置に適用することが出来ることは勿論である。Further, in the above embodiments, a semiconductor pressure sensor was exemplified as a semiconductor device having a thin film structure, but the present invention is not limited to this, and the present invention can be applied to all semiconductor devices having a thin film structure. Of course.
〔発明の効果〕
以上説明したごとく本発明においては、エツチングの終
点検出を光を用いて行なうように構成して゛いるので、
薄膜構造の厚み精度および繰返し加工精度を大幅に向上
させることが出来、かつ、エツチングの制御を容易に行
なうことが可能となる、という優れた効果が得られる。[Effects of the Invention] As explained above, in the present invention, the end point of etching is detected using light.
Excellent effects can be obtained in that the thickness accuracy and repeatability of the thin film structure can be greatly improved, and etching can be easily controlled.
第1図は本発明の製造方法の一実施例図、第2図は本発
明の製造方法に用いる装置の一例図、第3図はエツチン
グ時間と反射光強度との関係図、第4図は本発明の製造
方法の他の実施例図、第5図は従来の製造方法を示す図
である。
〈符号の説明〉
1・・・SL半導体基板 2.3・・・酸化シリコ
ン膜4・・・拡散抵抗領域 5・・・Aa配線層6
・・・PSG膜 7・・・ダイアフラム部8・
・・外部配線取り出し孔
9・・・エツチング終点検出領域
10・・・光源 11・・・光学系12・
・・受光部 13・・・エツチング層14・
・・エツチング液
代理人弁理士 中 村 純之助
エラずし71号間
t5図FIG. 1 is a diagram showing an example of the manufacturing method of the present invention, FIG. 2 is a diagram of an example of the apparatus used in the manufacturing method of the present invention, FIG. 3 is a diagram showing the relationship between etching time and reflected light intensity, and FIG. Another embodiment of the manufacturing method of the present invention, FIG. 5, is a diagram showing a conventional manufacturing method. <Explanation of symbols> 1...SL semiconductor substrate 2.3...Silicon oxide film 4...Diffused resistance region 5...Aa wiring layer 6
...PSG film 7...Diaphragm part 8.
... External wiring extraction hole 9 ... Etching end point detection area 10 ... Light source 11 ... Optical system 12 ...
・Light receiving part 13 ・Etching layer 14 ・
... Etching liquid agent Junnosuke Nakamura Elazushi 71 t5 diagram
Claims (1)
形成する半導体装置の製造方法において、半導体基板の
上記薄膜構造以外の所定部分も上記薄膜構造と同時にエ
ッチングし、かつエッチング中に上記所定部分に光を照
射し、上記所定部分からの反射光または透過光の強度を
測定することによってエッチングの深さを検知してエッ
チングを制御することを特徴とする半導体装置の製造方
法。In a method of manufacturing a semiconductor device in which a thin film structure is formed by etching a semiconductor substrate, a predetermined portion of the semiconductor substrate other than the thin film structure is also etched at the same time as the thin film structure, and the predetermined portion is irradiated with light during etching. . A method of manufacturing a semiconductor device, characterized in that etching is controlled by detecting the etching depth by measuring the intensity of reflected light or transmitted light from the predetermined portion.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12565586A JPS62283678A (en) | 1986-06-02 | 1986-06-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12565586A JPS62283678A (en) | 1986-06-02 | 1986-06-02 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62283678A true JPS62283678A (en) | 1987-12-09 |
Family
ID=14915386
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12565586A Pending JPS62283678A (en) | 1986-06-02 | 1986-06-02 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62283678A (en) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0491434A (en) * | 1990-08-02 | 1992-03-24 | Nippondenso Co Ltd | Method and apparatus for etching |
US5964643A (en) * | 1995-03-28 | 1999-10-12 | Applied Materials, Inc. | Apparatus and method for in-situ monitoring of chemical mechanical polishing operations |
US6537133B1 (en) | 1995-03-28 | 2003-03-25 | Applied Materials, Inc. | Method for in-situ endpoint detection for chemical mechanical polishing operations |
US6676717B1 (en) | 1995-03-28 | 2004-01-13 | Applied Materials Inc | Apparatus and method for in-situ endpoint detection for chemical mechanical polishing operations |
US6719818B1 (en) | 1995-03-28 | 2004-04-13 | Applied Materials, Inc. | Apparatus and method for in-situ endpoint detection for chemical mechanical polishing operations |
US6849152B2 (en) | 1992-12-28 | 2005-02-01 | Applied Materials, Inc. | In-situ real-time monitoring technique and apparatus for endpoint detection of thin films during chemical/mechanical polishing planarization |
US6994607B2 (en) | 2001-12-28 | 2006-02-07 | Applied Materials, Inc. | Polishing pad with window |
US7001242B2 (en) | 2002-02-06 | 2006-02-21 | Applied Materials, Inc. | Method and apparatus of eddy current monitoring for chemical mechanical polishing |
JP2007301719A (en) * | 2004-09-27 | 2007-11-22 | Idc Llc | Process control monitor regarding interferometric modulator |
JP2011222790A (en) * | 2010-04-12 | 2011-11-04 | Fuji Electric Co Ltd | Method and apparatus for manufacturing semiconductor device |
JP2014099546A (en) * | 2012-11-15 | 2014-05-29 | Fuji Electric Co Ltd | Semiconductor device manufacturing method and semiconductor device manufacturing apparatus |
-
1986
- 1986-06-02 JP JP12565586A patent/JPS62283678A/en active Pending
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0491434A (en) * | 1990-08-02 | 1992-03-24 | Nippondenso Co Ltd | Method and apparatus for etching |
US6849152B2 (en) | 1992-12-28 | 2005-02-01 | Applied Materials, Inc. | In-situ real-time monitoring technique and apparatus for endpoint detection of thin films during chemical/mechanical polishing planarization |
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