JPS61232641A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JPS61232641A
JPS61232641A JP60074810A JP7481085A JPS61232641A JP S61232641 A JPS61232641 A JP S61232641A JP 60074810 A JP60074810 A JP 60074810A JP 7481085 A JP7481085 A JP 7481085A JP S61232641 A JPS61232641 A JP S61232641A
Authority
JP
Japan
Prior art keywords
section
package
sealing
sealing surface
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60074810A
Other languages
Japanese (ja)
Inventor
Hiroyuki Sato
博幸 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60074810A priority Critical patent/JPS61232641A/en
Publication of JPS61232641A publication Critical patent/JPS61232641A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal
    • H01L2924/16315—Shape

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the scattering or flowing-in of a sealer on the sealing of a package by forming a fitting section consisting of a projecting section and a groove section to a sealing section for the package. CONSTITUTION:A semiconductor package has structure in which a package proper 3 composed of alumina ceramics, etc. is covered with a cover member 1 consisting of a metal such as kovar and sealed, a groove section 7 making a round on a sealing surface in the periphery of an opening section is shaped to the package proper 3, and a projecting section 6 going round on the sealing surface of the peripheral section is formed to the cover member 1. The groove section 7 and the projecting section 6 are fitted, and sealed through a sealer 2 such as a gold tin solder material, and the sealer 2 is arranged on a sealing surface outer than a fitting section. Accordingly, the flowing-in and scattering of a molten solder material into the opening section can be prevented, and the fitting section can be used for positioning on the sealing of the package.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子を収納する容器に関し、特に容器本
体を蓋部材で封止する際の容器本体と蓋部材との封止面
分に改良を施した容器に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a container for storing semiconductor devices, and in particular improves the sealing surface between the container body and the lid member when the container body is sealed with the lid member. Concerning containers that have been treated with

〔従来の技術〕[Conventional technology]

従来のフラットタイプの半導体容器は、第２図の縦断面
図（外部リードは図示せず）に示すように、半導体素子
５を収納する開口部を備えた容器本体３と、これに被せ
る蓋部材１との封止面分の形状が、それぞれ平面状であ
った０ 〔発明が解決しようとする問題点〕 上述した従来の半導体容器は、第２図に示すように、金
属ろう材である封着剤２の量が多過ぎれば、開口部に流
れ込んで流れ出し部８ａとなってボンディング線４を溶
かしたり、あるいは飛び散ｎ５ｓｂとなって半導体素子
５上に乗り、ショートしたりするなどの欠点があり、一
方、封着剤２の量が少なければ、十分な封止がなされな
いため気密性を維持できない、などの欠点があり、封着
剤の量のコントロールが困難であった。As shown in the vertical cross-sectional view of FIG. 2 (external leads are not shown), a conventional flat type semiconductor container includes a container body 3 having an opening for housing a semiconductor element 5, and a lid member to cover the container body 3. [Problems to be Solved by the Invention] The conventional semiconductor container described above has a sealing surface made of a metal brazing material, as shown in FIG. If the amount of the adhesive 2 is too large, it may flow into the opening and form a flow-out portion 8a, which may melt the bonding wire 4, or it may scatter and land on the semiconductor element 5, causing a short circuit. On the other hand, if the amount of sealant 2 is small, there is a drawback that airtightness cannot be maintained because sufficient sealing is not achieved, and it is difficult to control the amount of sealant 2.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体容器は、半導体素子を収納する開口部を
備えた容器本体と、この容器本体を封止する蓋部材とか
らなり、容器本体の封止面となる開口部周囲には、開口
部を一周する溝部が設けられ、又蓋部材の封止面となる
周縁部には、周縁部を一周する突起部が設けられ、この
溝部と突起部とが嵌合して封止されていることを特徴と
する半導体容器である。The semiconductor container of the present invention is comprised of a container body having an opening for accommodating a semiconductor element, and a lid member for sealing the container body. A groove that goes around the lid member is provided, and a protrusion that goes around the circumference is provided on the periphery that becomes the sealing surface of the lid member, and the groove and the protrusion fit together and are sealed. This is a semiconductor container characterized by:

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例の縦断面図（外部ＩＪ−ドは
図示せず）である。本発明の容器は、アルミナセラミッ
クなどからなる容器本体３に、コバールなどの金属から
なる蓋鄭羽１を被せて封止する構造であって、容器本体
３には、開口部周囲の封止面を一周する溝部７が設けら
れ、蓋部材１には、その周縁部の封止面を一周する突起
部６が設けられている。そして、この溝部７と突起部６
とを嵌合させ、金錫ろう材などの封着剤２を介して封止
を行う。FIG. 1 is a longitudinal cross-sectional view of one embodiment of the present invention (external IJ-board not shown). The container of the present invention has a structure in which a container body 3 made of alumina ceramic or the like is sealed by covering a lid 1 made of metal such as Kovar. A groove 7 is provided that goes around the lid member 1, and a protrusion 6 that goes around the sealing surface of the peripheral edge of the lid member 1 is provided. Then, this groove portion 7 and the protrusion portion 6
are fitted together and sealed via a sealing agent 2 such as gold-tin brazing material.

この際、封着剤２を嵌合部分より外側の封止面に配置す
ることＩＩＣ，１：って、開口部内への溶融ろう材の流
れ込みや飛び散りを阻止することができる。At this time, by arranging the sealant 2 on the sealing surface outside the fitting portion, it is possible to prevent the molten brazing material from flowing into the opening or scattering.

また、この嵌合部は、容器を封止する際の位置決めとし
て用いることができる。Further, this fitting portion can be used for positioning when sealing the container.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、容器の封止面に突起部
及び溝部からなる嵌合部を設けたことによって、容器を
封止する際の封着剤の飛散あるいは流れ込みを防止する
ことができる。As explained above, the present invention prevents the sealant from scattering or flowing in when sealing the container by providing a fitting portion consisting of a protrusion and a groove on the sealing surface of the container. can.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の半導体容器の縦断面図、第
２図は従来の半導体容器の縦断面図である０ １・・・・・・蓋部材、２・・・・・・封着剤、３・・
・・・・容器本体、４・・・・・・ボンディング線、５
・・・・・・半導体素子、６・・・・・・突起部、７・
・・・・・溝部、８ａ・・・・・・流れ出し部、８ｂ・
・・・・・飛び散り部。FIG. 1 is a longitudinal sectional view of a semiconductor container according to an embodiment of the present invention, and FIG. 2 is a longitudinal sectional view of a conventional semiconductor container. Sealing agent, 3...
... Container body, 4 ... Bonding wire, 5
... Semiconductor element, 6 ... Protrusion, 7.
...Groove section, 8a...Outflow section, 8b.
...Scattered part.

Claims (1)

【特許請求の範囲】[Claims] 容器本体の開口部に半導体素子を収納し蓋部材を被せて
封止する半導体容器において、容器本体の封止面には溝
部が設けられ、又蓋部材の封止面には、この溝部に嵌合
する突起部が設けられていることを特徴とする半導体容
器。In a semiconductor container in which a semiconductor element is housed in an opening of a container body and sealed by covering with a lid member, a groove is provided in the sealing surface of the container body, and a groove is provided in the sealing surface of the lid member to fit into the groove. A semiconductor container characterized by being provided with a matching protrusion.
JP60074810A 1985-04-09 1985-04-09 Semiconductor package Pending JPS61232641A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60074810A JPS61232641A (en) 1985-04-09 1985-04-09 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60074810A JPS61232641A (en) 1985-04-09 1985-04-09 Semiconductor package

Publications (1)

Publication Number Publication Date
JPS61232641A true JPS61232641A (en) 1986-10-16

Family

ID=13558032

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60074810A Pending JPS61232641A (en) 1985-04-09 1985-04-09 Semiconductor package

Country Status (1)

Country Link
JP (1) JPS61232641A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63242693A (en) * 1987-03-31 1988-10-07 三菱電機株式会社 Semiconductor-device card
JPS63242694A (en) * 1987-03-31 1988-10-07 三菱電機株式会社 Semiconductor-device card
JPS6464891A (en) * 1987-09-07 1989-03-10 Mitsubishi Electric Corp Plastic package for memory medium built-in card
JPS6475296A (en) * 1987-09-17 1989-03-20 Mitsubishi Electric Corp Plastic package for memory medium built-in card
JPH02177349A (en) * 1988-12-27 1990-07-10 Nec Corp Container for semiconductor device
JPH0395657U (en) * 1990-01-17 1991-09-30

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63242693A (en) * 1987-03-31 1988-10-07 三菱電機株式会社 Semiconductor-device card
JPS63242694A (en) * 1987-03-31 1988-10-07 三菱電機株式会社 Semiconductor-device card
JPS6464891A (en) * 1987-09-07 1989-03-10 Mitsubishi Electric Corp Plastic package for memory medium built-in card
JPS6475296A (en) * 1987-09-17 1989-03-20 Mitsubishi Electric Corp Plastic package for memory medium built-in card
JPH02177349A (en) * 1988-12-27 1990-07-10 Nec Corp Container for semiconductor device
JPH0395657U (en) * 1990-01-17 1991-09-30

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