JPH0326544B2 - - Google Patents
Info
- Publication number
- JPH0326544B2 JPH0326544B2 JP24211884A JP24211884A JPH0326544B2 JP H0326544 B2 JPH0326544 B2 JP H0326544B2 JP 24211884 A JP24211884 A JP 24211884A JP 24211884 A JP24211884 A JP 24211884A JP H0326544 B2 JPH0326544 B2 JP H0326544B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor component
- cap
- semiconductor
- input
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 12
- 150000001875 compounds Chemical class 0.000 claims description 10
- 238000007789 sealing Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 6
- 239000003566 sealing material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- -1 aluminum oxide Chemical class 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電子装置等に使用される配線基板に
半導体部品を実装するために用いる半導体容器に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor container used for mounting semiconductor components on a wiring board used in electronic devices and the like.
入出力ピン付き基板に半導体部品をフエイスア
ツプで実装する半導体容器には第２図、第３図に
示す２種類の構造のものがある。
There are two types of semiconductor containers in which semiconductor components are mounted face-up on a substrate with input/output pins, as shown in FIGS. 2 and 3.
第２図に示す半導体容器は効率よく放熱するた
めに半導体部品３３を収容する基板３１の裏側に
ヒートシンク３７を設け、基板３１の表側にキヤ
ツプ３５をシール材３６にて設けたものである
（例えば特開昭56−85842号）。３２は入出力ピン、
３４はリードである。このものは基板３１内の凹
部３１ａの開口側に入出力ピン３２を設け、該凹
部３１ａを入出力ピン３２側からキヤツプ３５に
て閉塞しているため、キヤツプ３５により入出力
ピン３２の数に制限を受けるという欠点があつ
た。また第３図に示すように基板３１の裏側に入
出力ピン３２を設けたものがある（例えば特開昭
56−120139号）が、ヒートシンクを備えておら
ず、放熱に対して考慮されていない欠点があつ
た。
In the semiconductor container shown in FIG. 2, a heat sink 37 is provided on the back side of a substrate 31 housing a semiconductor component 33 in order to efficiently dissipate heat, and a cap 35 is provided on the front side of the substrate 31 with a sealing material 36 (for example, Japanese Patent Publication No. 56-85842). 32 is an input/output pin,
34 is a lead. In this device, input/output pins 32 are provided on the opening side of a recess 31a in the board 31, and the recess 31a is closed from the input/output pin 32 side with a cap 35. It had the disadvantage of being limited. Furthermore, as shown in FIG.
No. 56-120139) had the disadvantage that it did not have a heat sink and did not take heat radiation into consideration.
本発明の目的は上述の従来の半導体容器の欠点
を解決した半導体容器を提供することにある。 SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor container that overcomes the above-mentioned drawbacks of conventional semiconductor containers.
本発明は内面に半導体部品のリードと接続され
るリード用パツドが形成された凹部を有し、外面
に上記リード用パツドと接線された入出力ピンを
設けた基板と、内側に突起を設けた半導体部品の
密封用キヤツプと、該キヤツプに接続されるヒー
トシンクとからなり、前記基板の凹部内にフエイ
スアツプで半導体部品を実装し、該半導体部品
と、基板の凹部を閉塞し半導体部品を密封する前
記キヤツプの突起との〓間及びその周辺に熱伝導
率の高いコンパウンドを充填したことを特徴とす
る半導体容器である。
The present invention comprises a substrate having a concave portion formed with a lead pad connected to the lead of a semiconductor component on the inner surface, an input/output pin provided on the outer surface with an input/output pin tangential to the lead pad, and a protrusion provided on the inner surface. The cap consists of a cap for sealing a semiconductor component and a heat sink connected to the cap, and the semiconductor component is mounted face-up in the recess of the substrate, and the semiconductor component and the semiconductor component are sealed by closing the recess of the substrate. This is a semiconductor container characterized by filling a compound with high thermal conductivity between the cap and the protrusion and its surroundings.
次に本発明の実施例について図面を参照して詳
細に説明する。
Next, embodiments of the present invention will be described in detail with reference to the drawings.
第１図は本発明の一実施例を示す断面図であ
る。 FIG. 1 is a sectional view showing one embodiment of the present invention.
第１図において、基板１の凹部１ａにはリード
用パツド１１が形成されており、下面にはリード
用パツド１１と接線された入出力ピン２が形成さ
れていて、外部の配線基板（図示せず）と反田付
け等により接続される。そして、半導体部品３が
基板１の凹部１ａ内にフエイスアツプで接合材１
２により搭載され、リード４がリード用パツド１
１に接続されている。また基板１の凹部１ａは、
上記半導体部品３との間にわずかな〓間１４を形
成するように先端を平面とした突起１３を有する
キヤツプ５と、シール材６とにより封止され、半
導体部品３は凹部１ａ内に密封される。また凹部
１ａ内には熱伝導率の高いコンパウンド８が充填
され、特にわずかな〓間１４には完全にコンパウ
ンド８が充填されている。そして、キヤツプ５に
は接合材１５によりヒートシンク７が接合され、
これにより半導体部品３で発生する熱をわずかな
〓間１４のコンパウンド８、キヤツプ５の突起１
３、キヤツプ５の本体、接合材１５、そしてヒー
トシンク７へ効率よく伝えられる。また、コンパ
ウンド８はゲル化することにより弾力性のあるゲ
ル状樹脂になり、ゲル化前は液体の流動性があ
り、ゲル化後は流動性がなくなるシリコーン樹脂
に熱伝導率の高い粉末、例えばベリリア（BeO）
やアルミナ（Al2O3）などの金属酸化物、窒化ホ
ウ素（BN）を混合したゲル化コンパウンドであ
る。したがつて、長期間の使用によるコンパウン
ドの流動や分離がなく、高い信頼性が得られる。
また、基板１の入出力ピン２と半導体部品３とが
基板１の同一面にないので、入出力ピン２の数が
多く設けられる。また本実施例におけるキヤツプ
５、接合材１５およびヒートシンク７は一体にし
ても良い。 In FIG. 1, a lead pad 11 is formed in a concave portion 1a of a board 1, an input/output pin 2 is formed on the bottom surface and is tangential to the lead pad 11, and an external wiring board (not shown) is formed on the bottom surface. ) and are connected by soldering, etc. Then, the semiconductor component 3 is face-up into the recess 1a of the substrate 1, and the bonding material 1 is
2, and lead 4 is mounted on lead pad 1.
Connected to 1. Further, the recessed portion 1a of the substrate 1 is
The semiconductor component 3 is sealed in the recess 1a by a cap 5 having a projection 13 with a flat tip so as to form a slight gap 14 with the semiconductor component 3, and a sealing material 6. Ru. Further, the concave portion 1a is filled with a compound 8 having high thermal conductivity, and in particular, the small gap 14 is completely filled with the compound 8. A heat sink 7 is bonded to the cap 5 using a bonding material 15.
As a result, the heat generated in the semiconductor component 3 is reduced to a small amount by the compound 8 of the space 14 and the protrusion 1 of the cap 5.
3. It is efficiently transmitted to the main body of the cap 5, the bonding material 15, and the heat sink 7. In addition, Compound 8 becomes an elastic gel-like resin by gelling, and has the fluidity of a liquid before gelling, but loses its fluidity after gelling. In addition, the compound 8 is a powder with high thermal conductivity, such as a silicone resin. Bereria (BeO)
It is a gelling compound that is a mixture of metal oxides such as aluminum oxide, alumina (Al 2 O 3 ), and boron nitride (BN). Therefore, there is no flow or separation of the compound due to long-term use, resulting in high reliability.
Furthermore, since the input/output pins 2 of the substrate 1 and the semiconductor components 3 are not on the same surface of the substrate 1, a large number of input/output pins 2 are provided. Further, the cap 5, the bonding material 15, and the heat sink 7 in this embodiment may be integrated.
本発明は以上説明したように、入出力ピン付き
基板に半導体部品をフエイスアツプで実装して、
熱を半導体部品の表側の面が放散できるので、放
熱効率に優れ、かつ入出力ピン数を多くできる効
果がある。
As explained above, the present invention mounts semiconductor components face-up on a board with input/output pins,
Since the front surface of the semiconductor component can dissipate heat, it has excellent heat dissipation efficiency and has the effect of increasing the number of input/output pins.
第１図は本発明の一実施例を示す断面図、第２
図および第３図は従来技術を示す断面図である。
１，３１……基板、１ａ……凹部、２，３２…
…入出力ピン、３，３３……半導体部品、４，３
４……リード、５，３５……キヤツプ、６，３６
……シール材、７，３７……ヒートシンク、８…
…コンパウンド、１１……リード用パツド、１２
……接合材、１３……キヤツプ５の突起、１４…
…〓間。１５……接合材。
FIG. 1 is a cross-sectional view showing one embodiment of the present invention, and FIG.
3 and 3 are cross-sectional views showing the prior art. 1, 31... Substrate, 1a... Recess, 2, 32...
...Input/output pin, 3,33...Semiconductor component, 4,3
4...Lead, 5,35...Cap, 6,36
...Sealing material, 7,37...Heat sink, 8...
... Compound, 11 ... Lead pad, 12
...Binding material, 13...Protrusion of cap 5, 14...
…〓A pause. 15... Bonding material.
Claims (1)
ド用パツドが形成された凹部を有し、外面に上記
リード用パツドと接線された入出力ピンを設けた
基板と、内側に突起を設けた半導体部品の密封用
キヤツプと、該キヤツプに接合されるヒートシン
クとからなり、前記基板の凹部内に半導体部品を
フエイスアツプで実装し、該半導体部品と、基板
の凹部を閉塞し半導体部品を密封する前記キヤツ
プの突起との〓間及びその周辺に熱伝導率の高い
コンパウンドを充填したことを特徴とする半導体
容器。1. A substrate having a concave portion on the inner surface with a lead pad connected to the lead of the semiconductor component, an input/output pin on the outer surface that is tangential to the lead pad, and a semiconductor component with a protrusion on the inside. a sealing cap, and a heat sink joined to the cap, a semiconductor component is mounted face-up in the recess of the board, and the cap closes the recess of the board to seal the semiconductor component. A semiconductor container characterized in that a compound with high thermal conductivity is filled between and around the protrusion.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24211884A JPS61120451A (en) | 1984-11-16 | 1984-11-16 | Semiconductor package |
| FR8513819A FR2570383B1 (en) | 1984-09-20 | 1985-09-18 | STABLE HEAT CONDUCTING COMPOSITION AND SEMICONDUCTOR DEVICE BLOCK IN WHICH THIS COMPOSITION IS USED |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24211884A JPS61120451A (en) | 1984-11-16 | 1984-11-16 | Semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61120451A JPS61120451A (en) | 1986-06-07 |
| JPH0326544B2 true JPH0326544B2 (en) | 1991-04-11 |
Family
ID=17084561
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24211884A Granted JPS61120451A (en) | 1984-09-20 | 1984-11-16 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61120451A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04192552A (en) * | 1990-11-27 | 1992-07-10 | Nec Corp | Package for semiconductor use |
| JPH05129482A (en) * | 1991-08-27 | 1993-05-25 | Kyocera Corp | Package for containing electronic component |
| JP4715049B2 (en) * | 2001-07-03 | 2011-07-06 | 株式会社デンソー | Seating detection mechanism and method for detecting the device |
| JP4696621B2 (en) * | 2005-03-22 | 2011-06-08 | ソニー株式会社 | Semiconductor device |
-
1984
- 1984-11-16 JP JP24211884A patent/JPS61120451A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61120451A (en) | 1986-06-07 |
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