JPS61232632A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the degree of integration of a three-dimensional LSI, and to inhibit trouble on wirings by forming a conductor pattern having general- purpose properties to the same layer as a semiconductor element as a lower layer, trimming the conductor pattern according to a custom wiring design and constituting a wiring by the conductor pattern and a wiring layer shaped onto a semiconductor element as an upper layer. CONSTITUTION:A large number of conductor patterns 4 are formed mutually in parallel among the arrays of semiconductor elements 3 by using gate electrode layers for FETs, and one parts of the conductor patterns 4 mutually connect gate electrodes for adjacent FETs. An SiO2 film 5 as a first insulating film is applied onto a wafer, and semiconductor elements 6 as second layers are shaped onto the film 5. The semiconductor elements 6 as the second layers are overlapped onto the semiconductors 3 as first layers, and disposed to an array shape. The conductor patterns 4 buried are utilized sufficiently as a use in a division manner into a plurality of wiring sections on the design of wirings, and wirings meeting the demand are constituted by employing wiring layers by aluminum, etc. fitted onto the semiconductor elements 6 as second layers through a second insulating film and the conductor patterns 4.

Description

[Detailed Description of the Invention] [Required 4] The present invention provides a method for manufacturing a three-dimensional semiconductor integrated circuit device using a mask slicing method, by providing a versatile conductor pattern in the same layer as the underlying semiconductor element, and The device is trimmed according to a custom wiring design and connected to the wiring formed on the upper layer semiconductor element, thereby increasing the degree of integration and suppressing wiring failures.

[Industrial application field]

In order to cope with the diversification of systems under the conditions of shortening the development period and improving economic efficiency, and to realize more advanced large-scale semiconductor integrated circuit devices (hereinafter referred to as LSI), Custom 1, Sl. The manufacturing method is mask slicing (mas
ter 5lice) method is widely used. The mask slicing method is a method in which an LSI is completed by preparing a semiconductor wafer with the necessary elements in advance and connecting it with wiring according to the customer's requirements, and it has a great effect on the realization of custom LSIs. .

On the other hand, with the aim of further increasing the integration and speed of LSIs, three-dimensional structures for three-dimensionally integrating semiconductor elements have been developed. Regarding three-dimensional structures, a mask slicing method is desired as a manufacturing method for custom LSIs, but wiring connections to stacked lower layer semiconductor elements and the like are a major problem.

[Conventional technology]

In the mask slicing method, the central part of each chip area is usually divided into an area where unit cells (basic circuits consisting of multiple transistors, resistors, etc.) necessary to construct a functional block such as a logic circuit are arranged in an array, and the surrounding area. For peripheral circuit areas such as input/output cells, for example, for field effect transistor (PET) elements, standardized semiconductor wafers are used in which gate electrodes, source, and drain regions are formed.

A wiring pattern that connects elements within a unit cell is designed according to the function of each block, and a wiring pattern for the entire chip that connects functional blocks and peripheral circuits is designed according to the functions required for the LSI. .

In the conventional mask slicing method, this wiring pattern usually has two wiring layers, the main wiring direction is determined for each wiring layer, and the lower first layer wiring connects the internal wiring of the functional block and the wiring area between the arrays. Set it parallel to the wiring, and
The layer wiring is orthogonal to the first layer wiring, and the second layer wiring is mainly connected to the first layer wiring.

In order to suppress the number of wiring layers or increase the degree of freedom in wiring, a conductive pattern such as a 7-lay pattern is formed in the wiring area between cell arrays by using an impurity diffusion region or a gate electrode layer using the same layer as the semiconductor element. There is also an attempt to form a layer in advance, select this layer, and use it as the first wiring layer.

On the other hand, as mentioned above, three-dimensional structures for three-dimensionally integrating semiconductor elements have been developed for the purpose of further increasing the integration and speed of LSIs. In a three-dimensional LSI, semiconductor elements in at least the second layer or higher are Sol (Silicon (S
emiconductor) on In5ulato
r) structure.

In the Sol structure, for example, polycrystalline silicon (Si) is deposited on an insulating film such as silicon dioxide (SiO□), and then made into a single crystal by a method such as laser beam scanning. Transistor elements and the like are formed here and wiring connections are made. It is something. This SQ, I structure has the characteristics that the capacitance between the substrate and the substrate is reduced compared to the usual structure in which transistor elements are formed on a semiconductor substrate, and no launch amplifier is generated even if the element spacing is shortened. Suitable for high speed and high integration. Because of this feature, the Sol structure was first developed as a single layer, and is often applied to the first layer of a three-dimensional structure.

[Problem that the invention seeks to solve]

When applying the mask slicing method to such a three-dimensional LSI, it is necessary to provide various wiring connections on a wafer formed by stacking semiconductor elements in advance.

Connection to the semiconductor element in the lower layer can be made by using the upper layer as a wiring area without a semiconductor element, but this makes the three-dimensional structure meaningless, and it is necessary to overlap the upper and lower semiconductor element formation areas and use the lower layer as a wiring area. It is also necessary to make full use of these facilities to increase the degree of integration.

Note that as the number of wiring layers increases, failures such as stencil failures become more prominent, so it is particularly desirable for three-dimensional LSIs to suppress the number of wiring layers.

[Means for solving problems]

As seen in FIG. 1, which is a schematic plan view of the process order of the embodiment of the present invention, the above problem is solved by disposing the conductor pattern 4 near the semiconductor element 3 of the first layer, and the semiconductor element of the first layer. A first layer is formed on the element 3 and the conductor pattern 4.
forming an insulating film 5, forming a second layer semiconductor element 6 on the first insulating film 5, and cutting the exposed conductor pattern 4 by providing an open lower part in the first insulating film 5; A second insulating film is formed on the second layer semiconductor element 6 and the open lower part, and a wiring 8 connected to the conductor pattern 4 is formed on the second insulating film. The problem is solved by a method of manufacturing an integrated circuit device.

[For production]

In the manufacturing method according to the present invention, a versatile conductor pattern is previously provided on the same layer as the underlying semiconductor element, this is trimmed according to a custom wiring design, and a wiring layer is formed on the conductor pattern and the upper semiconductor element. Configure the wiring with.

This wiring configuration makes it possible to increase the degree of integration of the three-dimensional LSI and to suppress wiring failures.

〔Example〕

The present invention will be specifically explained below using examples.

Refer to FIG. 1 F8) According to the conventional technique, an SiO□ insulating film 2 is formed on the St semiconductor substrate 1 to a thickness of, for example, about 1 μm, and this SiO2 film 2 is
An St polycrystalline layer is formed thereon to a thickness of, for example, about 0.5 μm, and is made into a single crystal by scanning with a laser beam, for example.

For example, a semiconductor element 3 with an SOI structure such as a MOS FET
can be formed by conventional techniques using this Si single crystal layer, but in this embodiment, a standardized conductor pattern 4, which is highly versatile, is formed in parallel with the semiconductor element 3.

That is, in this embodiment, a large number of conductor patterns 4 are formed in parallel with each other between an array of semiconductor elements 3 using the gate I/electrode layer of the FET, and some of these conductor patterns 4 are connected to the adjacent F[ The gate electrodes of the iTs are interconnected.

Note that the conductor pattern according to the present invention can also be formed by simultaneously performing the patterning of the Si single crystal layer and the introduction of high concentration impurities for the semiconductor element 3, which is the semiconductor element of the first layer, and the conductor pattern 4. It is also possible to perform the patterning not by etching but by field oxide film formation.

Refer to FIG. 1(b). SiO□ film 5, which is the first insulating film, is formed on the wafer.
is deposited, and a second layer of semiconductor element 6 is formed on -1=. This second layer semiconductor element 6 is similar to the first layer semiconductor element 3.
They are arranged in an array, superimposed on top of each other.

A wafer on which semiconductor elements 3.6 are formed in two layers, upper and lower, is the mask slice of this embodiment.

Customized wiring is arranged in accordance with the customer's request in this neem. First, in the wiring design, the buried conductor pattern 4 is divided into multiple wiring parts, etc., to make full use of this, and to connect the 2N semiconductor element. A wiring layer made of aluminum (AI') and the conductor pattern 4 provided on the conductor pattern 4 via the second insulating film (not shown) are used to construct a wiring according to the requirements.

When the conductor pattern 4 is to be divided into multiple wiring parts or for the purpose of reducing capacitance, the conductor pattern 4 can be cut by providing an open lower part as shown in the figure in the SiO□ film 5 and etching the conductor pattern 4. It can be easily implemented by

The wiring 8 (the figure shows only a part) of the A1 wiring layer is usually formed parallel to each other and perpendicular to the conductor pattern 4, and for example, the conductor pattern 4 and the second layer semiconductor are connected at the connection point 9 shown in the figure. It is connected to the element 6 and the first layer semiconductor element 3.

Although this connection can be made using conventional techniques, in this embodiment, the connection to the first layer semiconductor element 3 is performed simultaneously with etching to cut the conductor pattern 4, and simultaneously etching the second layer semiconductor element 3 at the connection position. An opening is provided in the element 6 in advance.

As explained above, the formation and trimming of the conductor pattern 4 can be easily carried out without increasing the number of steps in the conventional manufacturing method, and it is often possible to limit the number of wiring layers to one using AI or the like. This is possible in some cases, and the mask slicing method can increase the degree of integration of three-dimensional LSIs and reduce failures.

Furthermore, in order to further increase the scale, it is possible to use two wiring layers using AI or the like without any problem.

〔Effect of the invention〕

As explained below (according to the present invention), when manufacturing a three-dimensional LSI by the mask slicing method, the degree of integration can be increased without increasing the number of steps, and the problems caused by multilayer wiring can be reduced. is obtained.

[Brief explanation of the drawing]

FIG. 1 (al, (bl) is a schematic plan view showing an embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is an insulating film, 3 is a first layer semiconductor element, 4 is a conductor pattern, 5 6 is an insulating film, 6 is a semiconductor element in the second layer, 7 is an opening for cutting the conductor pattern, 8 is wiring by AI or the like, and 9 is a connection point of the wiring.

Claims (1)

[Claims] A conductive pattern (4) in the vicinity of the first layer semiconductor element (3)
the first layer semiconductor element (3) and the conductor pattern (4);
A first insulating film (5) is formed on the first insulating film (5).
) a second layer of semiconductor elements (6) is formed on the second layer, an opening (7) is provided in the first insulating film (5) and the exposed conductor pattern (4) is cut; on the semiconductor element (6) and the opening (7).
1. A method of manufacturing a semiconductor integrated circuit device, comprising: forming an insulating film, and forming a wiring (8) connected to the conductor pattern (4) on the second insulating film.