JPS61230482A - Processor for composite video signal waveform of television - Google Patents

Abstract

PURPOSE:To match an average video signal level with an operating point having the least distortion in an electric charge connecting element by providing an AC connecting circuit and a bias setting circuit at the input part of a 0.5H delay circuit which consists of the electric charge connecting element that delays a reproducing signal from a demodulation circuit by 1/2H of a horizontal synchronizing period. CONSTITUTION:At a 0.5H delay circuit 25, a video signal is supplied to the base of a transistor Tr 6 through a capacitor C7. And to the base of the transistor Tr 6, bias is given from a variable resistor VR2 through a resistor R15. Thereby, the average potential on the emitter of the transistor Tr 6 is set by the variable resistor VR2. Also, the average video signal level outputted from the emitter of the transistor Tr 6 is inputted to a CCD delay part 251 utilizing a self-bias effect by a CCD input power source through a parallel circuit consisted of a capacitor C8 and a resistor R17. Therefore, by providing the variable resistor VR2, it is possible to set the most stable position of the operating point of the CCD delay part 251 where the average video signal level that is inputted to the CCD delay part 251 is positioned.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a television composite video signal waveform processing device used, for example, when reading a composite video signal from a disk memory in an electronic still camera and displaying it on a television.

[Prior Art] The normal television standard system uses 1/2 interlaced scanning. For example, in the NTSC system, the horizontal scanning line of one field is 262.58 (IH is one horizontal opening period), and one frame - two fields is 525H. Therefore, when reproducing a rotating disk of an electronic still camera in which one field = 262.5H is recorded in one revolution, the horizontal synchronization at the recording joint (starting point or ending point) is 0.5H, that is, 1 horizontal synchronization period. This results in a shift of /2, which causes distortion on the screen of a normal television receiver, making normal display impossible. For this reason, it is necessary to generate a continuous horizontally synchronized reproduction signal from the recording joint by passing the reproduction signal from the disk through a 0.5H delay circuit every other field repetition period. In other words, (
A) shows the playback signal from the disk, but it is necessary to create the playback signal shown in Figure 4 (b) by extending this by 0.58N every other field in each field repetition period. . In the figure, Vs is a vertical synchronization signal, Hs
is a horizontal synchronizing signal, and in this case, both signals are delayed every other signal.

The basic circuit configuration of a television composite video signal waveform processing apparatus that performs such waveform processing is shown in FIG. This circuit supplies a reproduction signal read from a disk by a head 1 to a demodulation circuit 4 via an amplifier 2 and a bypass filter 3, and supplies the reproduction signal output from the demodulation circuit 4 to a 0.5 day delay circuit 5. Analog switch 5 that alternately switches its contacts every field repetition period
At the same time as inputting to one of the contacts, inputting directly to the contact of the user. The reproduced signal output from the analog switch 5 is outputted via the output amplifier 7 as a composite video signal Sv.

As a 0.5H delay circuit used in such a device, the one shown in FIG. 6 is conventionally known.

That is, the video signal input to the input terminal 11 is
PNP is supplied to the base of a transistor Tr11 of the type, and a PNP
type transistor Tr12 and NPN type transistor T
It is supplied to a circuit consisting of r13.

The video signal output from the transistor Tr13 is supplied to a delay unit 51 consisting of a charge-coupled device (COD).On the other hand, the synchronizing pulse input to the input terminal I2 is passed through a capacitor C12 and a resistor R21 to an NPN transistor. This transistor Tr14 has its emitter connected to the base of the transistor Tr14.
12, and its collector is connected to the movable terminal of a variable resistor VR1 connected between the power supply terminal and ground, and is also grounded via a capacitor C13.

In this conventional circuit, the video signal is sync-chip clamped by the action of the transistor Tr14.

That is, a positive synchronization pulse is applied to the base of the transistor Tr14, the transistor Trid is turned on at this sync tip, the sync tip potential is maintained at the charging voltage of the capacitor Q13 set by the variable resistor VRt, and the COD The input DC voltage level to the delay section 51 is set.

[Problems to be Solved by the Invention] However, in this circuit, the operating point is fixed regardless of changes in the average image level of the video signal. If the operating point is chosen so that the average distortion is small for
For a signal with a low average image level that contains a large amount of black level in the video signal, a delay operation is performed near the end of the transition from linearity to nonlinearity in the COD operating characteristic, causing a unidirectional waveform. There was a problem that distortion occurred. In addition, the sync tip clamp potential is susceptible to temperature-related fluctuations, and the bias is affected by the synchronization pulse waveform, which also causes non-linear distortion in the waveform.

Such problems appear in the form of flickering caused by differences in image brightness, and images becoming unstable due to temperature fluctuations.

This invention was made in view of the above circumstances, and there is no possibility that the waveform of the video signal will be distorted even if the image changes from a bright image to a dark image, and therefore flicker will occur in the image. It is an object of the present invention to provide a television composite video signal waveform processing device that is free from the risk of damage and can ensure stable operation even against temperature changes.

[Means for Solving the Problems] The present invention provides a method for extracting a composite video signal for displaying one frame of image using a 1/2 interlaced scanning method from a video signal storage medium that stores it as a one-field repetitive reproduction signal. a 0.5H delay circuit configured with a charge-coupled device that delays the reproduced signal from this demodulation circuit by 1/2 of the horizontal synchronization period; In a television composite video signal waveform processing device having circuit switching means for alternately passing the signal and the reproduced signal outputted from the demodulation circuit as they are in each field repetition period, the O05 day delay circuit has an AC coupling circuit at its input section. This circuit includes a bias setting circuit and a bias setting circuit.

E-Function: By having the above-described configuration, the present invention adjusts the average video signal level input to the charge-coupled device to the operating point with the least distortion of the charge-coupled device, regardless of whether the image is bright or dark. A video signal waveform with less distortion can be obtained.

Furthermore, it is also possible to eliminate the need for inputting a synchronization pulse for delay control operation.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 21 is a head, and this head 21 is 1/
The reproduction signal is read out from a disk, which is a video signal storage medium, in which a composite video signal for displaying one frame of image in a 2-interlace scanning method is stored as a one-field repeated reproduction signal. The reproduced signal read by this head 21 is sent to an amplifier 22 and a bypass filter 2.
3 to the demodulation circuit 24.

The demodulation circuit 24 has the function of outputting a reproduction signal and a synchronization signal, and supplies the reproduction signal to a 0,5H delay circuit 25 composed of a charge-coupled device (COD) and a PNP type transistor via a capacitor C1. It is supplied to the base of Tri.

The delay circuit 25 delays the input reproduced signal by 1/2 time of the horizontal synchronization period, and sends this delayed reproduced signal to the input terminal 2 of the balanced modulation circuit 26 constituting the peak level correction means and to the adder 27. supplying.

The balanced modulation circuit 26 has resistors R1 and R at its input terminal B.
The reference voltage obtained by the voltage dividing circuit No. 2 is inputted, and the error voltage from the peak level difference detection means described later is inputted to the input terminal C thereof, and the reproduced signal is inputted with a gain according to the magnitude of the error voltage. A positive or negative polarity signal is output from the output terminal O, and the signal is sent to the adder 27.
is supplied to.

The adder 27 superimposes the signal from the balanced modulation circuit 26 on the reproduction signal from the delay circuit 25, corrects the level, and sends the level-corrected delayed reproduction signal to the base of the PNP transistor Tr2 via the capacitor C2. is supplied to.

The collector of the transistor Tri is grounded, and the emitter of the transistor Tri is connected to an analog switch 2 constituting circuit switching means.
The other end of a parallel circuit consisting of a resistor R4 and a capacitor C3, one end of which is connected to one fixed contact 28 of 8, and one end of which is grounded through a diode D1 in the forward direction and a resistor R3, and an NPN emitter follower. type transistor Tr
It is connected to the base of 3. Further, the collector of the transistor Tr2 is grounded, and the emitter thereof is connected to the other fixed contact 282 of the analog switch 28, and is connected to the resistor R in the forward direction through the diode D2.
A resistor R6 and a capacitor C4 whose one end is grounded through 5
and the other end of the parallel circuit with the emitter follower NPN transistor Tr4. The circuit consisting of the diode D1, the resistor R3, a parallel circuit of the resistor R4 and the capacitor C3, and the transistor Tr3 constitutes a peak level detecting means for detecting the peak level of the video signal in the undelayed reproduced signal, and the diode D
2. A circuit consisting of a resistor R5, a parallel circuit of a resistor R6 and a capacitor C4, and a transistor Tr4 constitutes a peak level detecting means for detecting the peak level of the video signal in the delayed reproduction signal. Each of the transistors Tr
3. The collector of Tr4 is connected to the power supply terminal, and the emitter is grounded via a resistor. In this circuit, if the capacitances of the capacitors CI and C4 are made relatively large, even if the peak level of the video signal has a waveform, the average value of the peak levels can be detected as the peak level.

The emitter output of the transistor Tr3 is supplied via a voltage follower operational amplifier 29 to one input terminal (+) of a differential amplifier 30 constituting peak level difference detection means. Further, the emitter output of the transistor Tr4 is supplied to the other input terminal (-) of the differential amplifier 30. The differential amplifier 30 includes each transistor T.
The peak level of the undelayed video signal and the peak level of the delayed video signal inputted via r3 and Tr4 are input, the level difference is detected, and the difference is output as an error voltage. It is supplied to the input terminal C of the balanced modulation circuit 26.

The common contact 283 of the analog switch 28 is connected to the connection point between the resistor R7 and the switch 31 of the series circuit of the resistor 7, the switch 31, and the capacitor C5 connected between the + power supply terminal and the ground, and to the input terminal of the synchronous separation circuit 32. output amplifier 33 via resistors R8 and R9 in series.
is connected to the input terminal of

The synchronization separation circuit 32 outputs a pulse generated only during the pedestal period of the reproduced signal and a synchronization pulse, turns on the switch 31 for the pedestal period by the pulse generated during the pedestal period, and configures the synchronization pulse as a sync chip level setting means. It is supplied to the base of the NPN transistor +r5. The voltage across the terminals of the capacitor C5 is supplied to the input terminal of the pedestal clamp circuit 34. The output of this pedestal clamp circuit 34 is supplied to the base of the transistor Trl via a resistor R10, and is also supplied to the base of the transistor Tr2 via a resistor R11. The resistor R7, RIO1Rll, switch 31, capacitor C5, and pedestal clamp circuit 34 constitute a pedestal level control circuit.

The emitter of the transistor Tr5 is grounded via a capacitor C6, and is also connected to a movable terminal of a variable resistor VR1 in a series voltage divider circuit consisting of a resistor R12, a variable resistor VRI, and a resistor R13 connected between the power supply terminal and the ground. It is connected. The collector of the transistor Tr5 is connected to the connection point between the resistors Rs and Rg. Note that a resistor R1 is connected between the base and emitter of the transistor Tr5.
4 is connected.

The O05 day delay circuit 25 has a configuration as shown in FIG. That is, the video signal input to the input terminal 11 is passed through the capacitor C7 to the PN of the emitter follower.
It is supplied to the base of the P-type transistor Tr6. The base of the transistor 7r6 is connected via a resistor R15 to a movable terminal of a variable resistor VR2 connected between a power supply terminal and ground. The collector of the transistor Tr6 is grounded, and the emitter is connected to a power supply terminal via a resistor R16, and connected to a COD (charge-coupled device) delay unit 25 via a parallel circuit of a capacitor C8 and a resistor R17.
1 input terminal. The transistor Tr
6. A circuit consisting of capacitors C7 and Cs and resistors R16 and R17 constitutes an AC coupling circuit, and a circuit consisting of the variable resistor VR2 and resistor R15 constitutes a bias setting circuit.

In the apparatus according to the embodiment of the present invention configured as described above, the reproduced signal read from the disk by the head 21 is outputted via the amplifier 22, the bypass filter 23, and the demodulation circuit 24. The reproduced signal from the demodulation circuit 24 is delayed by a delay circuit 25 by 1/2 time of the horizontal synchronization period, that is, by 0.58. This delayed reproduction signal is supplied to a balanced modulation circuit 26 and an adder 27. Then, the balanced modulation circuit 2 receives the reproduced signal delayed by the adder 27 as it is.
7 is superimposed and level-corrected, and the level-corrected reproduction signal is supplied to the base of the transistor Tr2 via the capacitor C2.

On the other hand, the undelayed reproduced signal outputted from the demodulation circuit 24 is passed through the transistor T via the capacitor C1.
supplied to the base of rl. However, transistor T
An undelayed reproduction signal is output to the emitter of rl,
A delayed reproduction signal is also output to the emitter of the transistor Tr2.

The peak level of the video signal in the reproduced signal output to the transistor Tr1 is detected by a circuit consisting of a diode D1, a resistor R3, a resistor R4, a capacitor C3, and a transistor Tr3. The peak level of the video signal in the reproduced signal supplied to the input terminal (+) and output to the transistor Tr2 is determined by the diode D2 and the resistor Rs.
, is detected by a circuit consisting of a resistor R6, a capacitor C4, and a transistor Tra, and is supplied to the other input terminal (-) of the differential amplifier 3o. Therefore, the differential amplifier 3
0, the peak level of the video signal in the undelayed reproduced signal and the peak level of the video signal in the delayed reproduced signal are compared, and an error voltage corresponding to the difference is output. Therefore, the balanced modulation circuit 26 receives the input reproduction signal with a gain corresponding to the error voltage obtained by comparing the peak level of the video signal in the undelayed reproduction signal and the peak level of the video signal in the delayed reproduction signal. It will be processed. Therefore, the adder 2 superimposes the output of the balanced modulation circuit 26 on the delayed reproduced signal as it is.
The level-corrected playback signal output from 7 has been corrected so that the peak level of the video signal matches the peak level of the video signal in the undelayed playback signal.

Further, the pedestal level of the reproduced signal obtained via the analog switch 28 is held in the capacitor c5 by the on/off operation of the switch 31. This holding voltage is supplied to the base of the transistor Tr1 through the pedestal clamp circuit 34, roughly through the resistor R10, and is also supplied to the base of the transistor Tr2 through the resistor R11, and is caused by the operation of each of the transistors Trl and Tr2. The pedestal level of the undelayed reproduction signal and the pedestal level of the delayed reproduction signal are controlled so as to match. Therefore, the reproduced signal obtained via the analog switch 28 is a signal in which the peak level and pedestal level of the video signal of the delayed signal and the undelayed signal match.

Furthermore, the transistor Tr5 is turned on by the synchronization pulse from the synchronization separation circuit 32, and the resistor R8 is thereby turned on.
A voltage set by a variable resistor vR1 and held in a capacitor C6 appears at the connection point between and RB. This voltage is set to a level that sets the sync tip level of the reproduced signal, and thereby the sync tip levels of the undelayed reproduced signal and the delayed reproduced signal are fixed at the set level. Therefore, the reproduced signal Sv finally output from the output amplifier 33 is a signal in which the three levels of the video signal peak level, pedestal level, and sync tip level are the same between the undelayed signal and the delayed signal. . Therefore, if the reproduced signal Sv output from the output amplifier 33 is displayed as a composite video signal on a television receiver, flicker due to level changes does not appear in the image, and a clear screen without flicker can be obtained.

Further, in the 0.58 delay circuit 25, the video signal is supplied to the base of the transistor Tr6 via the capacitor C7. Since a bias is applied to the base of the transistor Tr6 from the variable resistor VR2 via the resistor R15, the average potential of the emitter of the transistor Tr8 can be set by the variable resistor VR2. In addition, the average video signal level output from the emitter of the transistor 7r6 is adjusted to the capacitor c8 and the resistor R17 by using the self-bias effect of the CCD input power supply.
It is input to the COD delay unit 251 via a parallel circuit with. Therefore, depending on the setting of the variable resistor VR2, the average video signal level input to the CCD delay section 251 is
The operating point of the delay section 251 can be set to the most stable position, and by setting it in this way, the video signal input from the input terminal 11 changes from a bright image to a dark image. Even if it is a video signal, the average level of the video signal is always controlled to be at the most stable operating point of the CCD delay section 251, so the video signal always follows the straight line of the operating characteristics of the COD delay section 251. Since the delay is controlled in the natural part, there is no possibility that the waveform of the video signal will be distorted due to changes from the image. Therefore,
Flicker due to the operation of the 0.58 delay circuit 25 does not occur on the screen.

In general, there is no need to clamp the sync tip using a synchronization pulse as in the conventional case, so there is no risk of fluctuations due to temperature changes. Furthermore, the bias is not affected by the synchronization pulse waveform. Therefore, the stability of the display screen also increases in this respect.

In this way, images with higher clarity can be displayed on the receiver.

Next, another embodiment of the invention will be described with reference to the drawings.

Components that are the same as those in the embodiment described above are given the same reference numerals and detailed explanations will be omitted.

This shows another embodiment of the 0.5H delay circuit 25 as shown in FIG. 3, in which the capacitor C7 inserted on the base side of the transistor Tr6 is omitted, and the variable resistor VR
2 and resistor R15 are connected to the input terminal of CCD delay section 251, and resistor R17 is also omitted.

In this circuit as well, the average input potential to COD is the variable resistor VR.
2, and the self-bias effect of COD can also be used, so that the video signal input from the input terminal 11 is a video signal that changes from a bright image to a dark image, etc., as in the previous embodiment. However, the average level of the video signal can always be controlled to be at the most stable operating point of the COD delay section 251, and the video signal can always be controlled to the linear part of the operating characteristics of the CCD delay section 251. Since the delay can be controlled by , there is no possibility that the waveform of the video signal will be distorted due to changes in the image frame. In this circuit, in order to effectively utilize the self-bias effect of the COD, it is necessary to set the resistance value of the resistor R15 to a large value.

[Effects of the Invention] As detailed above, according to the present invention, even if the image changes from a bright image to a dark image, there is no possibility that the waveform of the video signal will be distorted, and therefore flicker will not occur in the image. It is possible to provide a television composite video signal waveform processing device that is free from the risk of this occurring and can ensure stable operation even against temperature changes.

[Brief explanation of the drawing]

FIG. 10 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a specific circuit diagram of a 0, 5H delay circuit in the same embodiment,
Fig. 3 is a specific circuit diagram of a 0.5 day delay circuit showing another embodiment of the present invention, Fig. 4 is a waveform diagram for explaining delay control of a reproduced signal by the delay circuit, and Fig. 5 is a basic circuit diagram. FIG. 6 is a block diagram showing a typical circuit configuration, and FIG. 6 is a circuit diagram showing a conventional example. 21...Head, 24...Demodulation circuit, 25...0
．． 5H delay circuit, 28...analog switch, Tr8
...Emitter follower PNPN upper type resistor, C7
, CB... Capacitor, VR2... Variable resistor, R
15, RlB, R17...Resistance. Applicant's agent Patent attorney Takehiko Suzue Figure 1 [ Figure j12 + Figure 3 + Figure 4 Figure 5

Claims (1)

[Claims] A demodulation circuit that outputs the playback signal taken out from a video signal storage medium that stores a composite video signal for displaying one frame of an image in a 1/2 interlace scanning method as a one-field repeated playback signal, and the demodulation circuit A 0.5H delay circuit composed of a charge-coupled device that delays the reproduction signal from the circuit by 1/2 time of the horizontal synchronization period, and the reproduction signal output from this delay circuit and the reproduction signal output from the demodulation circuit as it is. In a television composite video signal waveform processing device having a circuit switching means for passing the signal alternately in each field repetition period, the 0.5H delay circuit is provided with an AC coupling circuit and a bias setting circuit at its input section. A television composite video signal waveform processing device characterized by: