JPH0455031B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a television receiver suitable for application to, for example, a television receiver in which display with twice the field frequency is performed.

BACKGROUND TECHNOLOGY AND PROBLEMS The current television system uses a scanning method called interlace. That is, 1
A single image (frame) is transmitted by two vertical scans (fields), and the aim is to increase the number of scanning lines as much as possible without causing flicker to the viewer's eyes in a limited frequency band. It was designed to do so.

However, in the CCIR system mainly used in Europe, the field frequency is 50Hz, and flickering cannot be completely eliminated at this frequency, and flickering can be felt, especially on screens with high brightness.

Therefore, conventionally, a television receiver has been proposed in which the field frequency is doubled. FIG. 1 shows an example.

In the figure, 1 is an antenna, 2 is a tuner,
3 is an intermediate frequency amplifier, and 4 is a video detection circuit.
From the video detection circuit 4, a video signal S _V of 625 lines/50 fields, 2:1 interlaced format, for example, is obtained.

This video signal S _V is converted into a digital signal by an A/D converter 5 and then supplied to a conversion circuit 6 .

The conversion circuit 6 includes field memories (random access memories 6a and 6b having a storage capacity for pixels of one field period (1V)), and a switch circuit 6.
It consists of c and 6d. The switch circuit 6c is
It is switched to the memory a and 6b side every 1V, while the switch circuit 6d is switched to the opposite side. Further, the memory selected by the switch circuit 6c is supplied with a write clock pulse having the above-mentioned pixel timing, and the memory selected by the switch circuit 6d is supplied with a read clock pulse of twice the frequency. be done.

The video signal S _V converted into a digital signal by the A/D converter 5 is supplied to the memories 6 a and 6 b for 1 field every 1 V via the switch circuit 6 c and is written into the memories 6 b and 6 a. One field's worth of video signal written in the immediately preceding 1V is read out twice in succession with a period of 1/2V, and this is obtained via the switch circuit 6d. In other words, a double-speed field video signal S _V ' whose field frequency is doubled is obtained from this switch circuit 6d.

This video signal S _V ' is converted into an analog signal by a D/A converter 7 and then supplied to a signal processing circuit 8. Red, green, and blue primary color signals R, G, and B are obtained from this signal processing circuit 8, and the picture tube 9 receives the red, green, and blue primary color signals R, G, and B, respectively.
supplied to

In addition, a video signal obtained from the video detection circuit 4
_SV is supplied to the vertical synchronization separation circuit 10. The vertical synchronizing signal P _V obtained from this separation circuit 10 is
The signal is doubled by a multiplier 11 to produce a signal with twice the frequency, and this signal is supplied to a deflection coil 13 through a vertical deflection circuit 12.

Also, the video signal obtained from the D/A converter 7
S _V ' is supplied to the horizontal sync separation circuit 14. The horizontal synchronizing signal P _H ′ (having twice the normal frequency) obtained from this separation circuit 14 is sent to the horizontal deflection circuit 15.
It is supplied to the deflection coil 13 through.

The example shown in FIG.
Since G and B are supplied and horizontal and vertical deflection scanning is performed at twice the speed, the picture tube 9 displays a color image at twice the field frequency. Therefore, even in the CCIR method mentioned above,
The field frequency is doubled to 100Hz, so you won't notice any flickering.

However, in the case of the example shown in FIG. 1, there is a disadvantage that the horizontal synchronization of the video signal S _V ' obtained from the conversion circuit 6 is periodically disrupted, causing distortion in the upper part of the screen.

That is, the video signal obtained from the video detection circuit 4
The write state of S _V to the memories 6a and 6b is represented as shown in FIG. 2A. F ₁ and F ₂ indicate the first and second fields. The video signal S _V ' from the conversion circuit 6 is expressed as shown in FIG. 2B. In the figure, the arrow indicates the position of the vertical synchronization signal. As is clear from FIG. 2B, the horizontal synchronization phase of the video signal S _V ' shifts by 180 degrees every two fields, that is, every 1/50 second (indicated by the dashed arrow), and this causes the screen This disrupts the synchronization at the top and causes image distortion.

Therefore, the present applicant has previously proposed a method that does not cause such image distortion. FIG. 3 shows an example. In FIG. 3, parts corresponding to those in FIG. 1 are designated by the same reference numerals.

In the figure, a video signal S _V obtained from a video detection circuit 4 is converted into a digital signal by an A/D converter 5 and then supplied to a conversion circuit 16 .

The conversion circuit 16 includes field memories (random access memories) 16a and 16b, each having a storage capacity for pixels of 313 horizontal periods (313H) and 312 horizontal periods (312H), and switch circuits 16c and 16d. The switch circuit 16 is alternately switched 313H to the memory 16a side and 312H to the memory 16b side. On the other hand, the switch circuit 16
d is switched to the opposite side. Switching control of these changeover switches 16c and 16d is performed by a control circuit 17. This control circuit 17 receives a horizontal and vertical synchronizing signal P _H separated by a synchronizing separation circuit 18 based on a video signal S _V
PV is supplied.

The memory selected by the switch circuit 16c is supplied with the write clock pulse at the pixel timing described above, and the memory selected by the switch circuit 16c
The memory selected at d is supplied with a read clock pulse having twice the frequency.

The video signal S _V converted into a digital signal by the A/D converter is supplied to the memories 16a and 16b via the switch circuit 16c, and is alternately written by 313H and 312H, respectively. Figure 4A is
It shows the write state of the memories 16a and 16b, and F ₁ and F ₂ indicate the first and second fields. In addition, the video signals written in the immediately preceding 312H and 313H are read out twice from the other memory 16b and 16a into the memories 16b and 16a, which are written in one of them, and this is the field double-speed video signal S _V ^* as switch circuit 1
Obtained from 6d. Figure 4B shows the switch circuit 16.
It shows the video signal S _V ^* obtained from d,
Field portions corresponding to those in FIG. 1A are designated by the same reference numerals. By the way, due to the difference between the writing time and the reading time, the video signal S _V ^* has an excess or omission of one line per field.

In FIG. 4B, for example, in the portion of the F ₁ and F ₁ fields (the portion read from the memory 16a), line 313 is not read out due to time constraints. Also, for example, in the F ₂ and F ₂ field portion (read portion from the memory 16b),
The video signal for one line is insufficient, reading is stopped during that time, and the video signal for one line is missing (1
(Illustrated with dash-dot lines). Such excess or lack of video signals occurs during the vertical blanking period, and does not cause any problem on the actual screen.

Writing to the above memories 16a and 16b,
Reading is controlled by a control circuit 17.

Video signal S _V ^* obtained from switch circuit 16d
is converted into an analog signal by the D/A converter 7 and then supplied to the signal processing circuit 8. Then, from this signal processing circuit 8, red, green, and blue primary color signals R, G
and B are obtained and supplied to the picture tube 9, respectively.

Further, the vertical synchronizing signal P _V ^* is generated from the controller circuit 17 at the timing shown by the arrow in FIG. 4B. That is, the start of the first F ₁ field, 312 lines after this, or the start of the second F ₁ field, 311.5 lines after this, 313 lines after this, 313.5 lines after this, or the first F ₁ field. The vertical synchronization signal P _V ^* is generated at the same timing. This synchronizing signal P _V ^* is supplied to the deflection coil 13 through the vertical deflection circuit 12, and vertical deflection scanning is performed. By generating the synchronization signal P _V ^* at the timing mentioned above, F ₁
Scanning lines are formed at the same position between the fields and between the F ₂ fields, and the scanning lines formed in the F ₁ field and the F ₂ field are shifted by a 1/2 scanning line interval. That is, the video signal
It is said that the interlace relationship of _SV is maintained as is.

Also, the video signal S _V ^* obtained from the D/A converter 7
is supplied to the horizontal sync separation circuit 14. and,
Horizontal synchronization signal P _H ^* obtained from this separation circuit 14
(having twice the normal frequency) is supplied to the deflection coil 13 through the horizontal deflection circuit 15, and horizontal deflection scanning is performed.

According to the example in FIG. 3, the horizontal synchronization of the video signal S _V ^* is continuous as shown in FIG. 4B,
Therefore, there is no synchronization disturbance due to discontinuity of horizontal synchronization as in the example of FIG. 1, and no image distortion occurs due to this.

However, in this example in Figure 3, F ₁
The vertical synchronization signal P _V ^* is applied so that the scanning lines between fields and F ₂ fields are formed at the same position.
Since the timing of occurrence of is determined (see the arrow in FIG. 4B), each vertical period is slightly different.

Incidentally, the vertical deflection circuit 12 has conventionally been configured as shown in FIG. 5, for example. In the figure, a vertical synchronizing signal P _V ^* (shown in FIG. 6A) is supplied to a terminal 19, and this vertical synchronizing signal P _V ^* is supplied to a sawtooth wave generator 20, from which its peak level ( Sawtooth signal with constant starting point level)
S ₁ (illustrated in FIG. 6B) is obtained. This generator 2
0 is, for example, the connection switch 2 as shown in FIG.
0a, charging capacitor 20b, constant current source 20
The connection switch 20a is turned on at the timing of the vertical synchronizing signal P _V ^* , and is turned off during other periods, so that a sawtooth wave signal _S1 is obtained.

The sawtooth signal S ₁ obtained from the generator 20 is supplied to the non-inverting input terminal of the differential amplifier 21 . Further, the output side of this amplifier 21 is connected to the vertical deflection coil 1.
3v, is grounded via a capacitor 22 and a resistor 23, and a vertical deflection current _S2 is passed through the deflection coil 13v. Then, the parabolic wave signal S ₃ obtained at the connection point P between the deflection coil 13v and the capacitor 22 is supplied to an integrating circuit 24, and the output of this integrating circuit 24 is used as a DC (direct current) feedback and vertical linearity correction signal to an adder. 25. Further, a signal obtained at the connection point between the capacitor 22 and the resistor 23 is supplied to the adder 25 for AC (alternating current) feedback. The addition output from the adder 25 is then supplied to the inverting input terminal of the amplifier 21.

In the case where the vertical deflection circuit 12 is configured as shown in FIG. 5, DC feedback is applied to prevent DC fluctuations, and since each vertical period is different as described above, the vertical deflection current S ₂
The peak level (starting point level) is not constant. Therefore, there is a drawback that image vibration (jitter) occurs in the vertical direction.

Further, in the case where the vertical deflection circuit 12 is configured as shown in FIG. 5, the parabolic wave signal _S3 obtained at the connection point P is used for correcting left and right pink distortion distortion. In this case, since each vertical period is different as described above, the peak level of the signal _S3 fluctuates in each vertical period as shown in FIG. 6D. Therefore, when this parabolic wave signal _S3 is used for correcting left and right pink distortion, there is a drawback that the amount of correction differs for each vertical period, causing image vibration (jitter) in the horizontal direction.

Furthermore, in the case where the vertical deflection circuit 12 is configured as shown in FIG. 5, the integrating circuit 24 also integrates the parabolic wave signal _S3 to obtain a sine wave signal for vertical linearity correction. As shown above, since the parabolic wave signal _S3 varies in each vertical period and each vertical period is different, this sine wave signal becomes different in each vertical period,
The disadvantage is that image vibration (jitter) occurs in the vertical direction.

Purpose of the Invention In view of the above, the present invention is designed to prevent image vibration (jitter) from occurring in the vertical and horizontal directions.

Summary of the Invention In order to achieve the above object, the present invention adds a correction circuit to the vertical deflection circuit so that the starting point level of the vertical deflection current is constant. Therefore, it is possible to prevent image vibration in the vertical direction caused by the vertical deflection current. Further, in the present invention, a parabolic wave signal obtained by integrating a vertical deflection current is derived via a clamp circuit to correct left and right pink distortion distortion. Therefore, it is possible to prevent horizontal image vibration caused by the parabolic wave signal for right and left pink distortion correction. Further, in the present invention, a parabolic wave signal obtained by integrating a vertical deflection current is supplied to an integrating circuit via a clamp circuit, and this integrated signal is derived via the clamp circuit to correct vertical linearity. be. Therefore, it is possible to prevent image vibration in the vertical direction caused by the signal for vertical linearity correction.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to FIG. This FIG. 8 shows the vertical deflection circuit in this example, and the other parts are constructed similarly to the example in FIG. 3. In this figure 8,
Portions corresponding to those in the figures are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In Figure 8, terminal 19 has a vertical synchronizing signal.
P _V ^* (shown in FIG. 9A) is supplied, and this vertical synchronizing signal P _V ^* is supplied to a sawtooth wave generator 20, which generates a sawtooth wave signal S ₁ (shown in FIG. 9A) whose peak level is constant. 9B) is obtained. This sawtooth signal S ₁ is supplied to the non-inverting input terminal of the differential amplifier 21 . The output side of this amplifier 21 is grounded via an adder 26, an amplifier 27, a deflection coil 13v, a capacitor 22, and a resistor 23, and a vertical deflection current S ₂ ' is caused to flow through the deflection coil 13v. In this case, the signal obtained at the connection point of the capacitor 22 and the resistor 2 is supplied to the inverting input terminal of the amplifier 21 via the adder 28 and subjected to AC feedback.
In this case, the parabolic wave signal S ₃ ' (shown in FIG. 9C) obtained at the connection point P between the deflection coil 13v and the capacitor 22 is supplied to the adder 26 via the sample and hold circuit 29, and is subjected to DC feedback. It will be done. Since the parabolic wave signal S ₃ ' has different vertical periods, its peak level fluctuates. The sample hold circuit 29 is supplied with a sampling pulse P _S (shown in FIG. 9D) formed by a sampling pulse forming circuit 30 based on the vertical synchronizing signal P _V ^* . This pulse P _S is
Continuous 312 lines, 311.5 lines, 313 lines,
It is formed to correspond to, for example, a vertical period of 312 lines among the four vertical periods of 313.5 lines. Therefore, in the sample-and-hold circuit 29, only the 312-line period part of the parabolic wave signal S ₃ ' is sampled, and a stable signal that does not fluctuate in each vertical period is obtained as a hold output, which is sent to the adder 26. DC feedback is applied.
Therefore, in this example, the vertical deflection current S ₂ ' flowing through the deflection coil 13v has a constant peak level (starting point level) as shown in FIG. 9E.
Note that the reason for DC feedback to the adder 26 is to prevent oscillation, which occurs when the gain is high.

Further, in FIG. 8, the parabolic wave signal S ₃ ' obtained at the connection point P is supplied to the clamp circuit 31,
It is clamped to a predetermined value at the timing of the vertical synchronization signal P _V ^* . Then, the left and right pink tension distortion is corrected based on the parabolic wave signal S ₃ ″ (shown in FIG. 9F) obtained from this clamp circuit 31. In this case, as described above, the vertical deflection current
Since the peak level of S ₂ ' is constant, the connection point P
312 lines of parabolic wave signal S ₃ ′ obtained in
The peak level based on the starting point of the parabolic wave in each vertical period of the 311.5 line, 313 line, and 313.5 line is constant. Therefore, the parabolic wave signal S ₃ ″ obtained from the clamp circuit 31 has a constant peak level.

In FIG. 8, the parabolic wave signal S ₃ ″ obtained from the clamp circuit 31 is supplied to the integrating circuit 32,
From this, a sine wave signal _S4 as shown in FIG. 9G is obtained. This sine wave signal S ₄ is then supplied to the clamp circuit 33 and clamped to a predetermined value at the timing of the vertical synchronization signal P _V ^* . The sine wave signal S ₄ ' (shown in FIG. 9H) obtained from the clamp circuit 33 is sent to the adder 2 via a capacitor 34.
8, and the vertical linearity is corrected based on this. In this case, the sine wave signal
S ₄ ′ is a parabolic wave signal with a constant peak level.
Since it is obtained by clamping the sine wave signal S ₄ obtained by integrating S ₃ ″, the level is constant.

According to this example, since the peak level (starting point level) of the vertical deflection current S ₂ ' (shown in FIG. 9E) flowing through the deflection coil 13v is constant, no image vibration occurs in the vertical direction. Furthermore, since the peak level of the parabolic wave signal S ₃ '' (shown in Figure 9F) that corrects the left and right pink distortion distortion is constant, the amount of correction in each vertical period is approximately the same, and the vibration of the image in the horizontal direction is In addition, since the level of the sine wave signal S ₄ ' (shown in Figure 9H) for vertical linearity correction is constant, the amount of correction in each vertical period is approximately the same, and the vibration of the image in the vertical direction is Does not occur.

In the above-mentioned embodiment, the sampling and holding circuit 29 is provided as a method of DC feedback, and the DC component detected by sampling once every four vertical periods is fed back to eliminate the fluctuation component of the feedback. The feedback time constant may be made sufficiently long to eliminate feedback fluctuations. In addition, as a method for obtaining a parabolic wave signal for pink-tension distortion correction, apart from the above-mentioned embodiment, a parabolic wave signal is written in advance in a memory (ROM, RAM), and obtained by reading it from the input of the vertical synchronization signal P _V ^* . Method,
Alternatively, there is a method of obtaining the vertical deflection current by integrating it from a constant value. In addition, as a method for obtaining a sine wave signal for vertical linearity correction, in addition to the above embodiment, a sine wave signal is stored in advance in a memory (ROM, RAM).
There is also a method of obtaining the signal by writing it in and reading it from the input of the vertical synchronizing signal P _V ^* , or by integrating a parabolic wave signal whose peak level does not fluctuate from a constant value.

Effects of the Invention As is clear from the embodiments described above, according to the present invention, since the starting point level (peak level) of the vertical deflection current is constant, vertical image vibration caused by the vertical deflection current is prevented. can do. Further, according to the present invention, since the peak level of the parabolic wave signal for correcting right pink distortion distortion is constant, it is possible to prevent horizontal image vibration caused by the parabolic wave signal for correcting left and right pink friction distortion. Further, according to the present invention, since the level of the sine wave signal for vertical linearity correction is constant, it is possible to prevent image vibration in the vertical direction caused by the sine wave signal for vertical linearity correction.

[Brief explanation of the drawing]

1 to 7 are diagrams for explaining conventional examples, FIG. 8 is a configuration diagram showing a vertical deflection circuit according to an embodiment of the present invention, and FIG. 9 is a waveform diagram for explaining the same. . 12 is a vertical deflection circuit, 13v is a vertical deflection coil, 20 is a sawtooth wave generator, 29 is a sample and hold circuit, 31 and 33 are respective clamp circuits, 3
2 is an integrating circuit.

Claims (1)

[Scope of Claims] 1. A television receiver configured to receive an interlaced video signal, convert the field frequency of the video signal using a field memory, and then supply the field frequency of the video signal to a picture tube. A sync separation circuit that supplies a signal to separate horizontal and vertical sync signals; and 1 frame of the received video signal is divided into integer lines, respectively, based on the horizontal and vertical sync signals output from the sync separation circuit. Each field is divided into multiple fields and written to the above field memory, and the 1 field written to the above field memory is
If the frame worth of video signals is read out multiple times in succession for each of the above fields at multiple times the writing speed, and the two continuously read out field signals are based on the same field signal, this is not applicable. Controlling the vertical deflection of the picture tube so that the scanning lines according to the field signals are formed at the same position, and when the scanning lines are based on different field signals, the scanning lines according to the field signals are formed shifted by a predetermined amount so as to perform interlacing. a control circuit that controls writing and reading of the field memory so as to generate a vertical synchronization signal with timing such that the vertical synchronization signal output from the control circuit generates a vertical deflection current that vertically deflects the picture tube; 1. A television receiver comprising: a vertical deflection circuit which causes the vertical deflection current to be constant; and a correction circuit which maintains a starting point level of the vertical deflection current at a constant level. 2. The television set forth in claim 1, wherein a parabolic wave signal obtained by integrating the vertical deflection current is derived through a clamp circuit to correct left and right pink distortion distortion. receiver. 3. A parabolic wave signal obtained by integrating the vertical deflection current is supplied to an integrating circuit via a clamp circuit, and this integrated signal is derived via another clamp circuit to correct vertical linearity. A television receiver according to claim 1.