JP2000324354A - Television deflector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a television deflector that prevents a start point of time of a ramp part of, e.g. a drive signal from being substantially affected by a change in an amplitude of the drive signal such as a change in a peak amplitude for each deflection cycle. SOLUTION: A deflection current i27 of a vertical deflection winding 27 corresponds to a trace part of a 2nd signal V0 from a sawtooth save generator 500 for a trace period, has the trace part that receives phase modulation according to a vertical control signal Vu4 from a control signal generator 501 and a vertical deflection current is kept to have the same phase as the vertical control signal for each deflection cycle where the phase of the vertical control signal changes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television deflection system and, more particularly, to a system in which the field frequency of a displayed image is increased to reduce flicker.

2. Description of the Related Art In a television display system, a threshold value at which field flicker can be perceived can be expressed as a function of the frequency of flicker and the luminance of a display device. Over the years, the brightness of the display device has been such that flickering is noticeable even in relatively high field frequency schemes (eg, NTSC 60 Hz scheme), and even lower field frequency schemes (eg, PSC).
(AL50Hz system), it has been increased to such a degree that it is clearly unpleasant. One solution to this problem is to double the field frequency of the displayed image. In one conventional scheme, the video input signal is stored in a field memory. Each stored field is recovered or read out of memory twice and displayed on a display which is scanned at twice the line frequency and twice the field frequency of the incoming video signal. As a result, the flicker frequency of the displayed image is doubled, and the degree of flicker is reduced.

[0002] The title of the invention is "Television Display System with Flicker Reduction Processing Device".
with Flicker Reduction Processor), the inventor of which is W. den Hollander.
U.S. Patent Application No. 857,375 (Republic of China Patent Application No.
(Corresponding to No. 75-101655) discloses a television display device that reduces flicker. In this device, an interlaced baseband television input signal having a predetermined field frequency is provided. A write cycle for storing one field of the input signal;
A first and a second read cycle for reading one field stored before that twice during one write cycle, and outputting a video output signal having a field frequency twice the predetermined field frequency. The memory to be generated is used. This output signal provides image information for display on a display device. A timing section responsive to the video input signal supplies a read control signal having a pulse waveform that repeats on the basis of two fields to the memory, and supplies a vertical synchronization signal having a pulse waveform that repeats on the basis of four fields to the display device. The pulse of the vertical synchronizing pulse waveform is phase-modulated on the basis of one field at a normal frequency which is twice the predetermined field frequency. The vertical synchronization pulse waveform pattern is selected so that a display image in which an even field is overlapped on an even field, an odd field is overlapped on an odd field, and a pair of even and odd fields is interlaced is displayed on the display device. Have been. Each pulse of the vertical sync signal initiates a corresponding vertical retrace scan period. The pulses of the vertical sync pulse waveform cause a corresponding phase modulation in the vertical deflection current. Furthermore, these pulses change the duration of the corresponding vertical scan cycle on a one-field basis and repeat on a four-field basis.

A typical vertical deflection circuit includes a sawtooth generator that generates a drive signal having a sawtooth waveform synchronized with a synchronization signal. During the retrace period, the capacitor is discharged by the switch and is charged by the current source during the trace period. The drive signal is coupled to a switching circuit that generates a deflection current having a corresponding sawtooth waveform.
The drive signal includes a ramp portion, which corresponds to the vertical trace, such that its starting point corresponds to a deflection current scanning the top of the display raster.

For example, in the apparatus of the above-mentioned US Patent Application No. 857,375, it is necessary to phase-modulate the pulse waveform of the vertical synchronization signal.
The peak amplitude of the drive signal at the end of the vertical trace is also
It may change based on one field according to the pulse waveform pattern.

When the peak amplitude of the drive signal changes,
The starting point of the ramp portion changes with respect to the corresponding pulse of the vertical synchronization signal that causes this ramp portion. This is because if the field changes, the discharge time of the capacitor of the sawtooth generator changes according to the peak amplitude of the different drive signal. As a result, the phase of the trace portion of the deflection current is different from the phase set by the phase-modulated vertical synchronization signal.
Therefore, even fields originally overlap with even fields, and odd fields overlap with odd fields, which makes it impossible to completely satisfy the requirement that odd field pairs and even field pairs should be interlaced.

Accordingly, in each deflection cycle, for example, the starting point of the ramp portion of the drive signal is:
It is desirable to prevent the drive signal from being substantially affected by a change in amplitude, for example, a change in peak amplitude.

According to one aspect of the present invention, a television deflection device responsive to a synchronization input signal at a frequency associated with a deflection frequency has a frequency associated with the frequency of the synchronization input signal and a phase to be modulated. Generate control signals. A sawtooth generator responsive to the control signal generates a second signal having a sawtooth waveform synchronized by the control signal. The second signal includes, in a predetermined deflection cycle, a ramping (changing at a constant rate) first portion that changes in a first direction;
A second portion that ramps in the opposite direction, and in each deflection cycle, when the second signal starts ramping in the first direction at the start of the first portion.
Has a predetermined value which is not affected by the modulation of the phase of the control signal. A deflection current having a sawtooth waveform according to the second signal is supplied to the deflection winding. The deflection current has a trace portion corresponding to a first portion of the second signal during a trace period. The trace portion of the deflection current is phase-modulated according to the control signal. This trace portion remains in phase with the control signal during each deflection cycle, even if the phase of the control signal changes.

Referring to FIG. 2, in accordance with one embodiment of the present invention, a vertical oscillator circuit 501 of a vertical scan generator 64 includes
A double frequency synchronization pulse 2V 'is supplied. This synchronization pulse 2V 'is supplied to the input terminal 702 of the inverting amplifier U1. This inverting amplifier U1 is biased by the voltage formed between resistors 704 and 706. The pulse 2V 'is phase-modulated and is generated by a method described later. Regular frequency of pulse 2V 'is a 2f _v. Where f
_v is the frequency of a vertical synchronization signal in a baseband television signal such as the NTSC or PAL standard. The pulses 2V 'are separated by corresponding periods with different durations. The normal length of the connection time is 1/2 V, where V represents, for example, a vertical scanning period of 20 milliseconds in the PAL system.

When the leading edge of the pulse 2V 'rises, the pulse U1a generated at the output terminal of the amplifier U1 makes a transition from a high level to a low level. The pulse U1a is converted into a pulse U1b by the resistor 708 and supplied to the corresponding non-inverting input terminals of the amplifiers U2 and U3 and the inverting input terminal of the amplifier U4. As a result, the amplifier U4 forms a pulse _VU4 at its output terminal. Pulse V _U4 has a waveform having the same polarity and width, for example, the period t ₀ -t ₂ sync pulse 2V as shown between the Figure 3 '.

[0007] Amplifiers U2 and U3 are coupled in feedback mode to form a vertical oscillator. Resistor 72 of FIG. 2 coupled between the output terminal of amplifier U3 and the non-inverting input terminal.
Since a positive return path is formed by 0, for example,
3, a during the period t ₀ -t _2, the pulse U1b is maintained at a low level, keeping the pulse V _U4 to the high level. At the same time, the capacitor 712 is rapidly discharged by the amplifier U2 of FIG. When the voltage at the inverting input terminal of amplifier U3, which corresponds to the voltage across capacitor 712, falls below the corresponding level of pulse U1b, amplifier U3 stops conducting and output voltage U3a goes high. However, trailing edge 901 of pulse 2V '
Until the pulse U1b is maintained at a low level. On the other hand, during the period between the leading edge 900 and the trailing edge 901 of 2V ', the pulse _VU4 remains high. Should pulse 2V 'disappear, pulse _VU4 is obtained from the output of amplifier U3 and resistor 7
It is extracted from the pulse U3a supplied to the amplifier U4 via 20.

[0008] Pulse V _U4 is ramp generating circuit 500 embodying an aspect of the present invention for generating a ramp voltage V ₀ which FIG 3, b
To control this. The ramp generation circuit 500 includes a current source transistor that is biased by the resistors R0, R1, R2, and R3 and supplies a current to a current integration capacitor Co connected in parallel to the conductive path of the transistor switch Q1. This ramp generation circuit 500
3, to generate an output ramp voltage V ₀ as shown by the solid line in b. Capacitor Co in Figure 2, starts to discharge when the leading edge 900 of pulse 2V 'occurs, the time before the trailing edge of each pulse V _U4, for example, FIG. 3, before the time t ₂ shown in b Discharge to the saturation voltage level of transistor Q1. Pulse V in FIG.
By _U4, the transistor Q1 is the voltage V ₀ transistor Q1
Clamped saturation voltage level, whereby the voltage V ₀
From rising before the trailing edge of pulse _VU4 .

The phase-modulated pulses V _U4 of FIG. 3, a are separated by periods which correspond to one another but have different lengths, and their phase modulation causes the instants t ₀ , t _{3 of} FIG. 3, b. ,
At times such as t ₆ and t ₉ , the lamp voltages V ₀ correspond to each other but exhibit different peak values.

The first ramping up portion of the voltage V ₀ occurs, for example, during periods t ₂ -t ₃ in FIG. 3, b. This first part starts a rising ramp from a predetermined constant level, which is the saturation voltage of the transistor Q1 in FIG. 2, without being affected by the phase modulation of the synchronization pulse 2V '. Thus, the first part of the rising ramp is, for example,
Figure 3, b such time as time t ₂ to start the rising ramp of.
Second portion falling ramp voltage V _0, for example the period t _O -t
Occurs in ₁ . The flat third portion occurs during the period t ₁ -t ₂ .

According to one aspect of the invention, the total value of the period corresponding to the second and third portions is a predetermined constant value that is not affected by the peak value of the voltage V ₀ which FIG 2 is there. For example, Figure 3, b, such as the period t ₀ -t _2, the period between the start point of the start point and the rising ramp of the falling ramp voltage V ₀ is affected by phase modulation of pulse 2V 'of FIG. 2 It is kept constant, for example.

The width of the synchronization pulse 2V 'generated by the timing unit 70 of FIG. 4 is, for example, the one-shot multivibrator U1' combined as shown by the dotted line in FIG.
Can be adjusted by

[0013] The lamp voltage V ₀ resistors 802, 804 and 806
DC biased and buffered by amplifier U5. The output of the amplifier U5 is supplied to a linearity correction circuit 808 generally indicated by reference numeral 808. The circuit 808 generates a linearity correction signal smoothed, the signal is described above with respect to the lamp voltage V ₀ which is added by the resistors 810, 812 to the signal generated at the output of amplifier U5 It has the same characteristics and form a ramp voltage V ₀ that linearity is corrected.

As shown in FIG. 1, the present invention also includes a switching vertical deflection circuit 100 controlled by the vertical control circuit 20 of the vertical scan generator 64. The operation of the deflection circuit 100 and the control circuit 20 is disclosed in detail in US Pat. No. 4,544,864. Control circuit 20 in accordance with the voltage V _D, for example, integrated transistor 18 and anti-parallel diode 19 and the illustrated pulse width to the switching element 21 modulated horizontal scanning frequency or the switching signal of the scan line frequency, such as to include Supply. Transistor 18 may include a power field effect transistor, in which case it is convenient when the horizontal frequency is higher than, for example, the horizontal frequency in a PAL scheme.

[0015] Such a high frequency is used, for example, in a computer monitor or a video display terminal. The switching element 21 is connected to a storage capacitor 26 via a winding 23 of a flyback transformer 24 connected in series to the storage coil 25.
Terminal 126. Terminal 126 of capacitor 26 is coupled to one end of vertical deflection winding 27. The other end of the vertical deflection winding 27 is connected to a power supply indicated by + V1. This + V1 power supply is the winding 30 of the flyback transformer 24,
It comprises a rectifier diode 31 and a filtering capacitor 32. This + V1 power supply is also used to supply power to other receiver circuits.

The horizontal output transistor 33 is switched at a horizontal deflection frequency by a signal supplied to the base from a horizontal oscillation and drive circuit 34. The collector of this transistor 33 is connected to the winding 35 of the flyback transformer 24.
To the power supply indicated by + V2. This transistor 33 has a horizontal deflection winding 36 and an S-shaped correction capacitor 38.
And the resonance retrace capacitor 37. Diode 40 between winding 30 and the collector of transistor 33 is connected in series with diode 31. By the switching operation of the transistor 33, the horizontal deflection current i _2H twice the frequency of the horizontal frequency f _H of the synchronizing signal of the baseband video signal V _{B B} to be described later is generated.

The operation of the vertical deflection circuit 100 is based on the storage capacitor 2
The storage capacitor 26 supplies a vertical deflection current i ₂₇ flowing through the winding 27, consisting of charging and discharging at a horizontal scanning frequency of 6. Switching at the horizontal scanning frequency is performed by the switching element 21.

At the beginning of a vertical trace, during each horizontal period, the transistor 18 of the switching element 21 conducts only for a very short period that occurs just before the horizontal retrace. As a result, the current i ₂₃ in the windings 23, flows in the direction opposite to the arrow shown, the capacitor 26 to a more positive voltage than the voltage + V1
Is charged. The voltage at the positive is terminal 126 and more than the voltage + V1 caused by this, deflection current i ₂₇ flows through the winding 27 in the opposite direction to the arrow. During vertical scanning, control circuit 20 ramps up the conduction period of transistor 18 that occurs in each horizontal trace. When transistor 18 conducts, capacitor 26 is discharged by an amount proportional to the conduction period of transistor 18. The gradual increase in the conduction period of transistor 18 causes the voltage across capacitor 26 to gradually decrease during the vertical trace. The tapering of the voltage across capacitor 26 is due to the fact that the charge taken by current i ₂₃ during the conduction period of transistor 18 during the corresponding horizontal trace period, rather than the charge applied to capacitor 26 during each horizontal retrace period. Because there are more. At the end of vertical trace, the voltage at terminal 126 is positive value less than the voltage + V1, deflection current i ₂₇ flows in the direction of the arrow. As a result, during the period from the beginning to the end of the vertical trace, the deflection current i ₂₇ rises and changes, and the polarity is inverted almost at the center of the vertical trace.

During vertical retrace, transistor 18 is non-conductive. As a result, the deflection winding 27 and the capacitor 26
Receives a half cycle of oscillation. The resulting vertical retrace voltage charges capacitor 26 to a voltage greater than voltage + V1, causing deflection current i ₂₇ to reverse its polarity.

According to one embodiment of the present invention, voltage V _D is
Is supplied to the non-inverting input terminal of the comparator 66. Waveform of the voltage V _D is, linearity, shaving, ignoring DC scale and DC level shifting can be expressed in the same way as the waveform of FIG. 3, b of V _0. Horizontal retrace pulses supplied through resistor 74 from the winding 28 to charge the capacitor 75, a horizontal ramp which is compared with the vertical sawtooth conductive V _D is obtained. The comparator 66 functions as a pulse width modulator. Comparator
The output of 66 base drives transistor 18.

Obviously, the current through resistor 22 is equal to deflection current i ₂₇ . Thus, the voltage developed across resistor 22 is proportional to current i ₂₇ , the vertical deflection current. The voltage generated between the both ends of the deflection current sampling resistor 22 is generated by the deflection current i ₂₇ , and gives a negative feedback to the vertical control circuit 20. The feedback for the vertical control circuit 20 provides information for generating a vertical deflection current i ₂₇ to drive the period in transistor 18 of an appropriate length of each horizontal period in the conductive state. Accordingly, the current i ₂₇ in the vertical trace interval is linearly proportional to sawtooth ramp voltage V _D.

[0022] At the time, such as immediately before FIG. 3, b at time t ₀ For example, when the leading edge of the pulse 2V 'i.e. V _U4 occurs, the second portion falling ramp voltage V _D is initiated. The start of the falling portion of the voltage V _D, deflection current i ₂₇ in the windings 27 of FIG. 2, begins a retrace portion that falling ramp its corresponding. When the trailing edge of pulse _VU4 in FIG.
A rising ramp of the deflection current i ₂₇ of the trace portion begins.

Voltage V _D controls the instantaneous level of deflection current i _{27 in} the vertical trace of deflection current i ₂₇ . As described above, during each vertical scan cycle, the pulse in FIG.
Voltage V _D when the edge occurs after the V _U4 is at the same level.

According to another aspect of the invention, because of the way of the occurrence of voltage V _D, FIG. 1, trace portion of the ramp in each deflection cycle of deflection current i ₂₇ both the voltage V _D of Figure 2, The pulse 2V 'is, for example, in phase with the corresponding leading edge 900 and follows its phase change.

As will be described later, proper superimposition of images is performed such that even fields overlap with even fields, odd fields overlap with odd fields, and pairs of even and odd fields are interlaced. The phase modulation of pulse 2V 'provides the exact timing needed to obtain the displayed image.

[0026] As a result of generating method has been the adoption of the waveform of the voltage V _D as shown in FIG. 3, b, from the end of vertical trace of a given deflection cycle of deflection current i ₂₇ in Figure 1 of the next deflection cycle It should be understood that the period up to the start of the vertical trace is also constant.

The DC component of the vertical sawtooth wave of FIG. 3, b voltage V ₀ which remains is left, it is desirable to transmit the deflection winding 27 in FIG. 2. Therefore, the sawtooth wave generation circuit, that is, the ramp generation circuit 500
It is desirable to use DC coupling not only between the vertical deflection winding 27 but also the vertical deflection circuit 100. The DC coupling is phase modulation of pulse 2V 'it is desirable because not change the level of deflection current i ₂₇ corresponding to a predetermined level of voltage V _O.

The features of the deflection current i ₂₇ as described above with various aspects of the present invention include, for example, the aforementioned US Pat. It is useful in the television receiver circuit shown in FIG. 4 which is similar to the circuit disclosed in application 857,375.

The receiver shown in FIG. 4 for generating the pulse 2V 'of FIGS. 1 and 2 includes a tuner 210, which has an input terminal 212 for connection to an antenna or other video input signal source. And an output terminal for supplying the baseband video output signal _VBB to the video processing unit 214 as described above. As an example, assume that the baseband video output signal is of the PAL type. But,
It should be appreciated that the principles of the present invention apply to other types of interlaced video signal formats.

The video processing unit 214 converts the input signal to Y,
Includes a PAL decoder that converts to the form of RY and BY components. This signal can be processed, if necessary, in the form of R, G, B components. In that case, the color difference signal (RY, BY)
Has a narrow bandwidth, but the R, G, B components each have the entire video bandwidth. Therefore, field storage for color difference signals can be realized with a smaller number of memory elements than in the case where processing is performed using R, G, and B components.

The Y, RY and BY component signals are filtered by the filter 21
6, analog and digital (A / D) converters 222, 2 for de-filtering by
Converted to digital form by 24 and 226. Filters 216, 218 and 220 minimize aliasing, and for the PAL input signal in the example shown, Y
Has a cutoff frequency of 2.8 MHz for the 7.5 MHz color difference signals RY and BY. In the case of NTSC signals, it is appropriate to set the cutoff frequency lower than the above.

The A / D converters 222, 224 and 226 use a sample clock CL phase-locked to a multiple of the horizontal synchronization signal to obtain a fixed number of samples for one horizontal line.
The low-pass filtered component is digitized to 8-bit resolution. After the A / D conversion, the digitized components are supplied to the memory 240 via the delay units 228, 230 and 232, respectively. As these delay units, variable delay units can be used, and are for equalizing the delay times of three input signal paths. Color difference signal components RY and BY
Are supplied to the memory 240 by a multiplex switch (MUX) 234 controlled by the horizontal frequency signal H. The switch 234 combines two 8-bit color difference signals into one 8-bit width color difference signal to reduce the storage capacity required of the memory 240.

8 multiplexed for one field
When the bit chrominance signal and the 8-bit luminance signal are stored in the memory 240, one previously stored field is read twice using the read clock signal 2CL having a frequency twice as high as the write clock CL. It is. This doubles the field frequency (100 Hz for PAL, 120 Hz for NTSC) so that flicker when a signal is displayed on the display unit 260 is less noticeable. A multiplexer 242 demultiplexes the chrominance signal and the luminance signal of twice the frequency, and a digital / analog (D / A) converter 244,
246 and 248 convert these signals back to analog form. The low-pass filters 250, 252, and 254 suppress the repeat spectrum after the D / A conversion. The cutoff frequency is suitably 13.5 MHz for a luminance signal and 6.75 MHz for a chrominance signal. Thereafter, they are supplied by a horizontal scan generator 62 and a vertical scan generator 64, respectively.
The double field frequency analog signal is converted to RGB format to supply the display 260 synchronized by the double speed horizontal deflection current i _2H and vertical deflection current i ₂₇ . Horizontal scanning generator 62 generates a deflection current i _2H of twice the frequency f _H of the horizontal synchronizing signal of the base over the scan band video output signal V _BB.

In the PAL system, one field is composed of 312.5 scanning lines. At twice the speed, this field and its repeated readout field must consist of 625 scan lines. This is achieved when one of the two fields consists of 312 scan lines and the other consists of 313 scan lines. FIG. 4 shows the memory 240
5. A timing signal which provides a field sequence as shown in FIG. In this sequence, 3/2 scan lines are generated in the first read cycle (field A or B),
In the second read cycle (field A 'or B'), 3
With the third scanning line left blank, 3/3 scanning lines are generated.

The vertical synchronizing pulse 2V 'having twice the field frequency required for the vertical scanning generator 64 has a pulse pattern shown by a solid line in FIG. 5B. For comparison, the dotted line shows the case of a vertical synchronization pulse having a period of 312.5 scanning lines and a double frequency at an equal interval. The solid pulse is repeated on a four-field basis in Figures 3 and
4 pulse signal 2V '. As shown, field A has 312 scan lines, repeated field A 'has 312.5 scan lines, and field B has 312.5 scan lines.
There are two scan lines and the repeated field B 'is 313.5
There are scan lines. Pulse 2V 'controls the switching type vertical deflection circuit 100 as described above, to produce a vertical scan waveforms of vertical deflection current i _27. The vertical trace portion of the vertical deflection current i ₂₇ is shown schematically in FIG. 5, (C). By the continuous scan current waveform of FIG. 5, (C), the first field (A, A ′) overlaps the first field, the second field (B, B ′) overlaps the second field, An interlace pattern shown in FIG. 5 (D) in which the pair of the first and second fields (AA ′, BB ′) is interlaced is generated. Figure for comparison
5, the scan lines that would occur if the sync pulse 2V 'in (B) were not shifted or phase modulated and therefore were equally spaced pulses are shown in FIG. .
To ensure that the displayed fields overlap correctly, the sawtooth voltage of FIG. 5, (C) generated by the ramp generator circuit 500 described above always starts from the same value and all retrace times (T ₀ -T ₀ ', T ₁ -T ₁ ', T ₂ -T ₂ ', etc.) are equal.

The timing signals for controlling the digital converter, memory, switches and scan generator are provided by the timing unit 70 of FIG. This timing unit 70, as described in the above-mentioned U.S. patent application Ser. No. 857,375, shows that when a signal at twice the field frequency is displayed, the even fields overlap the even fields and the odd fields overlap the odd fields. Pulses based on 2 and 4 fields for memory control and for generating scans of pulse 2V 'to ensure that the fields overlap and that the even and odd field pairs are interlaced. Generate a sequence.

If the ramp generation circuit 500 and the vertical oscillation circuit 501 of FIGS. 1 and 2 embodying one embodiment of the present invention do not operate, the vertical synchronization pulse 2V 'having a field frequency twice the irregular interval is obtained. 4 over successive fields, thus causing a variation in the phase of the trace portion of deflection current i ₂₇ with respect to corresponding pulse 2V '.

FIG. 6 shows a ramp generation circuit 500 'embodying another embodiment of the present invention. This performs a similar function as the circuit 500 of FIGS. FIGS. 7, a to 7 and c show corresponding waveforms associated with the circuit 500 'of FIG. 1, 2, 6, and 7, the same reference numerals and symbols indicate the same reference numerals and functions.

[0039] 'In, switch Q _1' circuit 500 of FIG. 6 (although thyristors in the figure, in may also be connected transistors in series with a diode) includes an inductor Lo 'and capacitor Co' connected in series It is connected between both ends of the resonance circuit. The vertical trace interval, the series circuit of an inductor Lo 'and capacitor Co' and is coupled to a current path of the emitter current i ₀ of the transistor Q2 'which operates as a current source.

When the leading edge 900 of pulse 2V 'occurs, the switch
Q ₁ ′ becomes conductive and starts retrace. When the switch Q ₁ ′ becomes conductive, a parallel relationship is established between the inductor Lo ′ and the capacitor Co ′. As a result, a half cycle of resonance oscillation occurs in the inductor Lo ′ and the capacitor Co ′, causing a retrace portion of the voltage V _O ′ in FIG. 7, b. In the remaining half cycle of this oscillation, switch Q ₁ ′ is shut off. The displacement of the pulse 2V 'required to correctly position the raster, ie the phase modulation, is only half of the displacement required in the case of FIGS. This is because the voltage V ₀ ′ in FIG. 6 has a mirror image relationship on both sides of the zero axis during the retrace period. For reference, the sawtooth wave generated from the equally-spaced synchronization pulses is shown by a dotted line in FIG. 7B.

For example, the retrace period, such as period t _a -t _b in FIG.
It is virtually unaffected by the voltage across Co ',
Rather, it is determined by the resonance frequency of the inductor Lo 'and the capacitor Co'.

According to another aspect of the invention, as in FIGS. 3 and b, the phase of the trace portion of the voltage V ₀ ′ of FIG. 7, b with respect to the phase of the corresponding pulse 2 V ′ of FIG. Is a pulse 2V '
Is substantially unaffected by the phase modulation.

According to the present invention, in each deflection cycle, for example, the start of the ramp portion of the drive signal is prevented from being substantially affected by changes in the amplitude of the drive signal, for example, changes in the peak amplitude. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a part of a vertical scanning generator including a sawtooth generator according to one embodiment of the present invention.

FIG. 2 is a circuit diagram of a remaining portion of the vertical scan generator.

FIG. 3 is a waveform chart for explaining the operation of the circuits shown in FIGS. 1 and 2.

FIG. 4 is a block diagram of a television receiver including the vertical scan generator shown in FIGS. 1 and 2.

FIG. 5 is a waveform chart showing an operation of the receiver of FIG. 4;

FIG. 6 is a circuit diagram of another embodiment of the present invention.

FIG. 7 is a circuit diagram for explaining the operation of the circuit in FIG. 6;

[Explanation of symbols]

 27 Deflection winding 100 Deflection current generator 500 Saw wave generator 501 Control signal generator

Continuing on the front page (72) Inventor Giovanni Michele Leonard Day Switzerland Türich Zue Ha 8048 Denlerstrasse 20 Ar

Claims (1)

[Claims] Means for generating a phase-modulated vertical control signal in response to a vertical synchronization input signal; and synchronizing with the phase-modulated vertical control signal in response to the phase-modulated vertical control signal. A sawtooth generator for generating a second signal having a sawtooth waveform, wherein the second signal is substantially opposite to the first direction in a predetermined deflection cycle. The second signal has the same period in each cycle between the end of each trace and the beginning of the next trace, and the phase of the vertical control signal A vertical deflection winding having a spacing unaffected by the modulation, and means for generating a vertical deflection current having a sawtooth waveform applied to the vertical deflection winding in response to the second signal. , The above vertical deviation The current has a trace portion corresponding to the trace portion of the second signal during a trace period, the trace portion being phase-modulated according to the vertical control signal, and the vertical deflection current has a phase of the vertical control signal. A television deflector configured to be maintained in phase with the phase modulated vertical control signal in each of the changing deflection cycles.