JP3009206B2 - Video camera equipment - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a video camera device that can be used for home use, broadcast, surveillance, industrial use such as medical care and inspection, and the like.

[Conventional technology]

Conventionally, the signal processing section of a video camera was an analog system. In recent years, with the rapid spread of VHS for general users and 8 mm VTRs, the development of small, lightweight, low-cost VTR integrated video camera devices has been promoted. Have been. As means for achieving these, digitization of a signal processing unit is being promoted.

FIG. 2 is a block diagram showing a basic configuration of a video camera in which a conventional analog signal processing unit is digitized.

In FIG. 2, when the sensor 1 receives the optical signal 11,
In each horizontal read scanning period, an analog pixel signal 12 composed of alternately different color signals is output in synchronization with a read clock frequency (hereinafter, referred to as a sensor clock fs). The operation of the sensor 1 is controlled by a control signal 18 from a sensor drive timing generation circuit (hereinafter referred to as TG) 5. The analog pixel signal 12 is converted into an analog signal by an analog / digital conversion circuit (hereinafter abbreviated as A / D) 2.
/ D converted into a digital pixel signal 13. When the digital signal processing circuit 3 is supplied with the digital pixel signal 13, the synchronizing signal 20 and the control signal 23 from the synchronizing signal generating circuit (hereinafter referred to as SSG) 8, and the control signal 18, the synchronizing signal is added. Luminance signal 14 and color signal 15 to which a synchronization signal is added.
Generate These signals 14 and 15 are converted from digital to analog by a digital / analog conversion circuit (hereinafter abbreviated as D / A) 4 and converted into an analog luminance signal 1 to which a synchronization signal is added.
6 and an analog color signal 17 to which a synchronization signal is added.

Hereinafter, the control signal 18 generated in the TG 5 and the synchronization signal 20 and the control signal 23 generated in the SSG 8 will be described. First, the SSG8 has an oscillation frequency of n fsc (n is an integer, fsc
When a signal of a frequency n fsc is supplied as a clock from an oscillator 61 having a frequency of a color subcarrier, a horizontal synchronizing signal (hereinafter, CHD) necessary to generate a signal for driving a sensor is supplied.
) And a vertical sync signal (hereinafter referred to as VD).
These two signals 19 are supplied to TG5. TG5 generates a sensor clock fs from the signal supplied from the oscillator 51 and CHD and VD. On the other hand, the SSG 8 uses a synchronization signal 20 such as a composite sync signal (hereinafter, referred to as CSYNC), a composite blanking signal (hereinafter, referred to as CBLK), a burst flag signal (hereinafter, referred to as BF), using n fsc as a clock. Occurs. The CSYNC signal is a horizontal and vertical decoding synchronization signal of the television, the CBLK signal is a signal indicating a horizontal and vertical blanking period of the video signal, and the BF signal is a modulation of the video signal in the television. This is a signal indicating a period in which a reference signal for demodulating a color signal is added to a video signal. Further, the SSG 8 generates a control signal 23 obtained by dividing the frequency of the signal of n fsc and outputs it to the digital signal processing circuit. The digital signal processing circuit 3 generates a luminance signal and a color difference signal using the sensor clock fs as a clock, adds a synchronization signal 20 to these two signals, outputs a luminance signal 14, and modulates the color difference signal by a control signal 23. do it,
The color signal 15 is output.

It should be noted that Japanese Patent Publication No. Sho 63-45153 discloses a device related to this type of device.

[Problems to be solved by the invention]

According to the above-mentioned prior art, in converting a signal processing unit of a video camera apparatus from an analog system to a digital system, a luminance signal is synchronized with a sensor clock fs, and a synchronization signal such as a composite sync (CSYNC) signal is synchronized with n fsc. are doing. n
fsc is a frequency that depends on the color television system used. Therefore, despite the fact that the sensor clocks fs and n fsc have different frequencies, no consideration has been given to synchronizing the luminance signal and the synchronization signal. FIG. 3 is a timing chart of CSYNC before being added to the sensor clock fs and the luminance signal. CSYNC is the horizontal and vertical decoding signal of the television and is generated from n fsc. CSYNC
If the rising edge 104 of the sensor clock fs and the falling edge 106 of the CYSNC have the same frequency, the CSYNC 102 is latched at the rising edge 104, and the signal is the same as CSYNC even after being added to the luminance signal. Signal. However, there are cases where the data is not latched at the rising edge 104 but is latched at the rising edge 105. As described above, when CSYNC is taken into the signal processing unit at the rising timing of fs, CS
If the timing of the phase change of YNC is near the rise of fs, it becomes unstable at which timing CSYNC is taken in at 104 or 105 every horizontal cycle. In this case, CS
The difference between the falling timings of YNC 102 and CSYNC 103 is 1 / fs. For example, if the number of pixels in the H direction of the sensor is 550, 1 / fs ≒ 1H / 550 = 115 ns. In the case of such a deviation, a jitter occurs in the output image that can be detected by human eyes.

Further, conventionally, since the horizontal read clock frequency of the sensor is fixed, it is not possible to cope with a sensor having a clock frequency different from that, and there is a problem that there is no versatility.

SUMMARY OF THE INVENTION An object of the present invention is to provide a video camera device capable of suppressing jitter generated when a synchronization signal synchronized with n fsc (n is an integer, fsc is the frequency of a chrominance subcarrier) is added to a luminance signal synchronized with a sensor clock. It is in.

[Means for solving the problem]

As means for preventing the jitter, first or second
The third means is adopted as a means for supporting the multi-sensor. The first means is that the frequency
Synchronization consisting of an n fsc unit that generates a horizontal synchronization signal and a vertical synchronization signal for the camera using the n fsc signal as a clock, and an fs unit that generates a synchronization signal for the television using the sensor clock fs generated by the TG as a clock That is, a signal generation circuit is provided.

The second means is a signal switching circuit for alternately supplying a luminance signal and a television synchronization signal to the D / A, and a clock having a frequency of n fsc and a sensor clock fs as the D / A clock. It is configured to include a clock switching circuit for alternately supplying clocks.

Next, a third means is a programmable means capable of changing the timing of a television synchronization signal generated in the fs section in order to be able to support various sensors without depending on the sensor clock fs. It is configured to include an SSG and a microcomputer for controlling the SSG.

[Action]

In the first means, when a clock having a frequency of n fsc is supplied, the n fsc unit performs a timing generation process using a counter or the like, and generates a horizontal synchronization signal (CHD) and a vertical synchronization signal (VD) for the camera. These two signals are supplied to the TG.
TG is the sensor clock fs by the signal synchronized with CHD
And supplies several kinds of control signals such as the sensor clock fs to the digital signal processing circuit and the fs section in the SSG.
The digital signal processing circuit performs signal processing using the sensor clock fs as a clock to generate a luminance signal and a color difference signal. On the other hand, the fs unit also generates a synchronizing signal such as a composite sync signal for television using the sensor clock fs as a clock. Therefore, since the luminance signal and the synchronization signal are synchronized with the sensor clock fs, the luminance signal and the synchronization signal are synchronized. Therefore, when adding a synchronization signal to a luminance signal in the digital signal processing circuit, no large timing shift occurs, and thus no jitter occurs.

In the second means, the signal switching circuit is switched to the synchronizing signal side at a point in time when the luminance signal level is constant (point A) before the horizontal blanking period and before entering the horizontal blanking period; Is switched to the n fsc side, a synchronization signal is input, and supplied to the D / A conversion circuit using n fsc as a clock to output an analog synchronization signal. Next, the luminance signal level during the horizontal blanking period and after leaving the horizontal blanking period is constant (B
Point), the signal switching circuit and the clock switching circuit are connected to opposite sides, and an analog luminance signal is output by the same processing as described above. Therefore, at the points A and B, even if the luminance signal and the synchronization signal are not synchronized, no jitter occurs because the luminance signal level is constant.

Next, in the third means, timing data from the microcomputer, control signals such as the sensor clock fs from the TG, n
When the vertical synchronizing signal is supplied from the fsc unit, the fs unit holds the timing data in the state holding circuit, and stores the value of the counter using the sensor clock fs as a clock and the timing data held in the state holding circuit. Processing is performed to generate a horizontal synchronizing signal, and a synchronizing signal is generated by synthesizing the horizontal synchronizing signal and the vertical synchronizing signal supplied from the n fsc unit. As described above, if the timing data supplied from the microcomputer to the fs unit is data conforming to the specifications of the sensor being used, a synchronization signal suitable for the sensor can be generated, so that multi-sensor compatibility can be realized.

〔Example〕

Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the basic configuration of the video sensor device according to the first embodiment. This consists of a sensor 1, an analog / digital conversion circuit (A / D) 2, a digital signal processing circuit 3, and a digital / analog conversion circuit (D / A)
4, a sensor drive timing generation circuit (TG) 5, an oscillation circuit 51, a synchronization signal generation circuit (SSG) 6, and an oscillation circuit 61.
Consisting of

Hereinafter, the operation of the video camera device having the above configuration will be described. When the sensor 1 receives the optical signal 11, the sensor 1 outputs an analog pixel signal 12 composed of alternating color signals alternately in synchronization with the sensor clock having the frequency fs every one horizontal scanning period. The operation of the sensor 1 is controlled by a control signal 18 from the TG 5.
Is controlled by Analog pixel signal 12 from sensor 1
The A / D 2 converts the analog pixel signal 12 into a digital pixel signal 13 and supplies the digital pixel signal 13 to the digital signal processing circuit 3. When the digital pixel signal 13 is supplied from the A / D 2, the control signal 18 is supplied from the TG 5, and the synchronizing signal 20 and the control signal 23 are supplied from the SSG 6, the digital signal processing circuit 3 outputs the luminance signal 14 to which the synchronizing signal is added.
And a color signal 15 to which a synchronization signal is added.
Signals 14 and 15 are supplied to D / A4. When the digital signal processing circuit 3 supplies the luminance signal 14 to which the synchronization signal is added and the color signal 15 to which the synchronization signal is added, the D / A 4
The signals 14 and 15 are converted into analog signals, and a luminance signal 16 to which an analog synchronization signal is added and a color signal 17 to which an analog synchronization signal is added are output. Note that the SSG 6 generates a synchronization signal 20 from the control signal 18 supplied from the TG 5. TG5 is the synchronous signal 19 supplied from SSG6 and the oscillation circuit 51.
The control signal 18 is generated from the reference signal 50 supplied from the control unit 20.

FIG. 4 is a block diagram more specifically showing the configuration of SSG6. In FIG. 4, SSG6 includes an n fsc section 62 and an fs section 63.
The n fsc unit 62 further includes a horizontal synchronizing signal generation circuit 621
And a vertical synchronizing signal generating circuit 622. The fs section includes a horizontal synchronizing signal generating circuit 633 and a synchronizing signal generating circuit 635. Hereinafter, the operation of SSG6 will be described. Note that the control signal 23 shown in FIG. 1 is generated by dividing the signal of the frequency n fsc generated in the n fsc section and is supplied to the digital signal processing circuit 3, but is not shown. did.

First, in the n fsc unit 62, the frequency nf
When the sc signal 60 is supplied, the horizontal synchronization signal generation circuit 621
Generates a horizontal synchronization signal 623 and supplies them to a vertical synchronization signal generation circuit 622. When the horizontal synchronization signal 623 is supplied from the horizontal synchronization signal generation circuit 621, the vertical synchronization signal generation circuit 6
22 generates a vertical synchronizing signal 625 and supplies these to a synchronizing signal generating circuit 635 in the fs section. Further, the n fsc unit includes a signal (CHD) 624 required to generate a signal for performing horizontal driving of the sensor 1 among the horizontal synchronization signals 623 and a vertical synchronization signal 62.
A signal (VD) 625 necessary for generating a signal for performing vertical driving of the sensor 1 among the five signals is supplied to the TG 5 as a control signal 19. When the control signal 19 is supplied from the SSG 6, the TG 5 receives the signal obtained by dividing the reference signal 50 supplied from the oscillation circuit 51 and the CHD
Are locked in phase, and the frequency is
Generates a control signal 18 for fs sensor lock, etc.
Is supplied to the fs unit 63 of SSG6. When the control signal 18 is supplied, the horizontal synchronization signal generation circuit 633 generates a horizontal synchronization signal 638 synchronized with the sensor lock fs, and supplies the horizontal synchronization signal 638 to the synchronization signal generation circuit 635. Vertical sync signal generator 6
When a vertical synchronizing signal 625 is supplied from 22 and a horizontal synchronizing signal 638 is supplied from a horizontal synchronizing signal generating circuit 633, the synchronizing signal generating circuit 6
35 generates a synchronization signal 20 (CSYNC, CBLK, BF) and supplies the synchronization signal 20 to the digital signal processing circuit 3. here,
Since the horizontal synchronization signal 638 and the vertical synchronization signal 625 are synchronized with the sensor clock fs, the synchronization signal 20 is also synchronized with the sensor clock fs.
It is synchronized with fs.

FIG. 5 is a block diagram showing the configuration of the digital signal processing circuit 3 more specifically. In FIG. 5, the digital signal processing circuit 3 includes a Y / C separation circuit 31, a Y process circuit 32, a C process circuit 33, a CSYNC addition circuit 34, a BF addition circuit 35, and a conversion circuit 36. Hereinafter, the operation of the digital signal processing circuit 3 will be described.

When digital pixel signal 13 is supplied from A / D2, Y / C
The separation circuit 31 includes a first pixel signal 301 and a second pixel signal 302.
And supplies these two signals to the Y process circuit 32 and the C process circuit 33, respectively. First from Y / C separation circuit 31
When the pixel signal 301 and the second pixel signal 302 are supplied,
The process circuit 32 generates a luminance signal 303 and supplies it to the CSYNC adding circuit 34. Further, when the first pixel signal 301 and the second pixel signal 302 are supplied from the Y / C separation circuit 31, the C process circuit 33 generates a color difference signal 304 and supplies this to the BF addition circuit 35. The Y / C separation circuit 31, the Y process circuit 3
2 and C process circuit 33 control signal 18 supplied from TG5.
And is synchronized with the sensor clock fs. Therefore, the luminance signal 303 and the color difference signal 304 are also synchronized with the sensor clock fs. SSG6
The sync signal 20 supplied from the SYNC is composed of a composite sync (CSYNC) signal 305 and a color burst (CBLK) signal 30
6 and a burst flag (BF) signal 307. The CSYNC signal is a horizontal and vertical decoding synchronization signal of the television, the CBLK signal is a signal indicating a horizontal and vertical blanking period of the video signal, and the BF signal is a modulation of the video signal in the television. This is a signal indicating a period in which a reference signal for demodulating a color signal is added to a video signal. When the luminance signal 303 is supplied from the Y process circuit 32 and the CSYNC 305 and CBLK 306 are supplied from the SSG 6, the CSYNC adding circuit
34 generates the luminance signal 14 to which the synchronization signal is added. On the other hand, the color difference signal 304 from the C process circuit 33
5 and the CBLK 306 are supplied, the BF adding circuit 35 generates a color difference signal 308 to which a synchronizing signal is added,
Supply to When the color difference signal 308 to which the synchronization signal is added from the BF addition circuit 35 and the control signal 23 are supplied from the SSG 6, the modulation circuit 36 generates the color signal 15 to which the synchronization signal is added. Then, the luminance signal 14 and the chrominance signal 15 to which the synchronization signal is added are added.
Are converted into analog signals by the D / A 4 to become analog luminance signals 16 and color signals 17.

As described above, according to the present embodiment, the signal processing is controlled by the sensor clock, and the synchronizing signal is also generated from the sensor clock. Therefore, the digital luminance signal and the synchronizing signal are synchronized, and the two signals are combined. This has the effect of preventing jitter.

Next, a second embodiment of the present invention will be described with reference to the drawings. The basic configuration of the video camera device of this embodiment is almost the first.
It is the same as the figure, except that the SSG 6 in FIG. 1 is replaced with a programmable SSG 65 and a microcomputer 7 for controlling it is provided. FIG. 6 shows the programmable SSG65
FIG. 2 is a block diagram more specifically showing the configuration of a microcomputer 7. The control signal 23 shown in FIG.
The signal is generated by dividing the frequency of the signal of the frequency n fsc generated in the fsc unit and supplied to the digital signal processing circuit 3, but is not shown. In FIG. 6, SSG65
Consists of an n fsc section 62 and an fs section 64, and the fs section 64 is a counter 631
, A latch circuit 632, a horizontal synchronization signal generation circuit 634, and a synchronization signal generation circuit 635. However, the configuration and operation of the n fsc unit 62 and the synchronization signal generation circuit 635 are the same as those of the SSG6.
FIG. 7 shows one of the configurations of each block in the fs unit 64.
It is a figure showing an example. In FIG. 7, a latch circuit 632 is provided.
Is composed of a latch circuit 632a and a latch circuit 632b, and the horizontal synchronizing signal generation circuit 634 includes a comparison circuit 634a and a pulse generation circuit 634b.
Consists of

Here, the signal 22 is timing data supplied from the microcomputer 7 and includes timing data 22a and an address 22b. The signal 639 and the signal 640 are output signals of the comparison circuit 634a, and the signal 638 is a horizontal synchronization signal. Also,
FIG. 8 is a timing chart in the process of generating the horizontal synchronization signal 638. Hereinafter, the operations of the SSG 65 and the microcomputer 7 will be described with reference to FIGS. 6, 7, and 8.

In FIG. 6, the microcomputer 7 supplies the first timing data 22 for generating a synchronization signal conforming to the specifications of the sensor 1 to the latch circuit 632, and causes the latch circuit 632 to hold the timing data 22a. However, which of the latch circuits 632a and 632b in FIG. 7 holds the timing data 22a is determined by the address 22b. Here, as an example, it is assumed that the latch circuit 632a holds the value a and the latch circuit 632b holds the value (a + b). When the control signal 18 is supplied from TG5, the counter 631
Counts using the sensor clock fs as a clock, and counts the counter value 636 as a comparison circuit in the horizontal synchronization signal generation circuit 634.
Supply to 634a. Timing data 6 from latch circuit 632
When supplied with 37a and 637b and the counter value 636 from the counter 631, the comparison circuit 634a checks whether the counter value 636 matches the timing data 637a or 637b. Is output. That is, the comparison circuit 634a outputs the signal 639 and the signal 640 in FIG. When the signals 639 and 640 are supplied, the pulse generation circuit 634b generates a horizontal synchronization signal 638 shown in FIG.
The horizontal synchronization signal 638 is supplied to a synchronization signal generation circuit 635. Then, the vertical synchronizing signal 625 from the vertical synchronizing signal generating circuit 622 and the horizontal synchronizing signal 63 from the horizontal synchronizing signal generating circuit 634.
8, the synchronization signal generation circuit 635 outputs the synchronization signal CSYN
C, CBLK and BF are generated, and these three synchronization signals 20 are supplied to the digital signal processing circuit 3. The subsequent operation is the same as that of the first embodiment.

As described above, in the second embodiment, only the configuration of the fs unit 64 shown in FIG. 7 is shown, but in fact, the configuration is the same as that of the latch circuit 632 and the horizontal synchronizing signal generation circuit 634 in FIG. By providing a plurality of such signals, a plurality of types of horizontal synchronization signals can be generated. Further, 632 is not limited to a latch circuit, but may have any function capable of holding a state.

As described above, according to the present embodiment, by providing the programmable SSG and the microcomputer for controlling the programmable SSG, the timing of the horizontal synchronization signal can be made variable, so that a synchronization signal adapted to the specifications of the sensor to be used can be generated, There is an effect corresponding to the sensor.

Next, a third embodiment of the present invention will be described. The basic configuration of the video camera device of this embodiment is substantially the same as the configuration shown in FIG. 1 except for the portion shown in FIG. 9, and the operation of each block is also the same. In FIG.
The video camera device according to the present embodiment includes a programmable TG 9 and a microcomputer 7 that controls the programmable TG 9. When the timing data 22 is supplied from the microcomputer 7 and the synchronization signal 19 is supplied from the SSG 6, the programmable TG 9 is required in the second embodiment using the same method as that performed by the fs unit 64 of the programmable SSG 65. The control signal is generated at the timing.

As described above, according to the present embodiment, there is an effect that the sensor drive pulse and the control signal of the signal processing can be changed according to the sensor and the system configuration.

Next, a fourth embodiment of the present invention will be described. FIG. 10 is a block diagram showing a basic configuration of the video camera device of the present embodiment. This includes the sensor 1, A / D2, digital signal processing circuit 3, D / A4, TG52, and programmable SSG66.
, A control circuit 10, and an oscillation circuit 51.

Hereinafter, the operation of the video camera device having the above configuration will be described. However, sensor 1, A / D2, digital signal processing circuit
Since the operations of 3, D / A4 are the same as those of the video camera device of the first embodiment, the operation of the circuits other than those described above will be particularly described here. First, the oscillation circuit 51 outputs the reference signal 50
Supply to TG52. When the reference signal 50 is supplied from the oscillation circuit 51, the TG 52 divides the reference signal 50 to generate a control signal 191 such as a sensor clock fs and a sensor drive signal 181 for driving the sensor 1, Each is supplied to the programmable SSG66 and the sensor 1. Programmable S
The SG66 has a circuit similar to the fs unit 64 in FIG.
Timing data 22 for generating a synchronization signal adapted to various sensors from outside the programmable SSG 66,
When the control signal 191 such as the sensor clock fs is supplied from the TG 52, the sensor clock is operated by the same operation as the fs unit 64.
A synchronization signal 20 synchronized with fs and a control signal 25 are generated and supplied to the digital signal processing circuit 3 and the control circuit 10, respectively. When the control signal 25 is supplied from the programmable SSG 66, the control circuit 10 supplies a control signal 26 such as a clock to the A / D 2 and a control signal 27 such as a sensor clock fs to the digital signal processing circuit 3. Thereafter, the video camera device of the present embodiment performs the same operation as the video camera device of the first embodiment again as described above, and outputs analog luminance signals and color signals to which a synchronization signal is added.

As described above, according to the present embodiment, the provision of the programmable SSG 66 capable of generating a synchronization signal at a different timing depending on externally supplied data provides an effect corresponding to a multi-sensor.

Next, a fifth embodiment of the present invention will be described. The basic configuration of the video camera device of this embodiment is the same as that of FIG. 10 except that the microcomputer 7 and the input terminal 71 for rewriting data are provided. In FIG. 10, the microcomputer 7 inputs data 72 from the input terminal 71, temporarily holds the data 72, further supplies the data 72 as timing data 22 to the programmable SSG 66, and stores the data 72 in the programmable SSG 66. The existing timing data. However, the data 72 is not limited to the timing data 22, and the microcomputer 7 is not limited to the above operation.
It is assumed that other circuits can be controlled from the data 72 as needed.

As a sixth embodiment, as shown in FIG. 13, the ROM 73 is provided in FIG. 10, so that the data 72 is stored in the ROM 73 and supplied to the microcomputer 7 from the ROM 73. You can also.

As described above, according to the fifth and sixth embodiments, the microcomputer 73 stores the data 73 supplied to the microcomputer 7 in the ROM 73.
The timing data 22 supplied to the programmable SSG 66 and the programmable SSG 66 controlled by the microcomputer 7 can generate a synchronization signal 20 adapted to the sensor 1,
There is an effect corresponding to the multi-sensor. Also, there is an effect that the setup at the time of starting the video camera device can be automatically performed.

As a seventh embodiment, the configuration shown in FIG. 13 is changed to the configuration shown in FIG. 14, and data similar to the data 72 is stored in the ROM 73, and a part of the data stored in the ROM 73 is used. Some timing data 22 is directly programmable SS
Even when the power is supplied to the G66, the same effects as those of the fifth and sixth embodiments can be obtained.

Next, an eighth embodiment of the present invention will be described with reference to the drawings. The basic configuration of the video camera device of this embodiment is almost the tenth.
It is similar to the figure, except for the points shown in FIG. Fifteenth
In the figure, the microcomputer 70 stores several types of timing data for each system, and the programmable ROM 74 stores codes and control data assigned to each system. The input terminal 76 also supplies system selection data 78 to the microcomputer 70 from outside. When the system selection data 78 is supplied, the microcomputer 70 is programmed.
The system data 77 including the code and the control data specified by the selection data 78 is read from the ROM 74, and the timing data 22 specified by the code is supplied to the programmable SSG 66 from various timing data stored in the microcomputer 70. Then, the control data is supplied to the control circuit 10. Other operations are the same as the operations of the video camera device of the fourth embodiment.

As described above, according to the present embodiment, the system selection data 78
Can be automatically set to a state in which the video camera device can operate normally only by supplying the signal from the input terminal 76, so that the working efficiency in the manufacturing process is improved.

Next, a ninth embodiment of the present invention will be described with reference to the drawings. The basic configuration of the video camera device of this embodiment is almost the second.
The figure is the same as that of the figure, and the digital signal processing circuit is the same as that of FIG. 5, but the luminance signal processing section in the portion 37 surrounded by the dotted line is different. FIG. 11 is a diagram showing a D / A converter of a luminance signal and a synchronizing signal of the video camera device of the ninth embodiment. The D / A converter includes a signal switch 371 and a clock switch 372. (FIG. 12 is a diagram showing a luminance signal to which a synchronizing signal is added.) The basic operation of the video camera device of this embodiment is the same as that of the conventional video camera shown in FIG. Since the operation of the video camera device is almost the same, only the operation of the D / A converter will be described below. First, in the section AB in FIG.
371 connects the terminal 374 to the terminal 375, supplies the synchronization signal 20 to the D / A4, and the clock switch 372 connects the terminal 377 to the terminal 378, and supplies the clock of the frequency n fsc to the clock 24 of the D / A4. . At this time, the D / A 4 converts the synchronization signal 20 into an analog signal using the n fsc clock as a clock and outputs the analog signal. Next, at time B in FIG.
Switches to the terminal 373, supplies the luminance data 303 to the D / A4, the clock switch 372 switches to the terminal 376, and outputs the sensor clock of the frequency fs, which is one of the control signals 18,
Supply to clock 24 of D / A4. At this time, the D / A 4 converts the luminance signal 303 into an analog signal using the sensor clock fs as a clock, and outputs the analog signal. This operation is continued in the section B-A 'until the next time A'. At the time A ',
The signal switch 371 and the clock switch 372 are respectively connected to the opposite terminals, and the same operation as in the AB section is performed. Thereafter, the above operation is repeated. In FIG.
Sections C, D, including switch switching points A, B, A ', B'
The luminance signal levels of C ′ and D ′ are all constant.

As described above, according to the present embodiment, the luminance signal and the synchronization signal
Since the D / A conversion is switched when the luminance signal level is constant on both sides of the horizontal blanking period, even if the luminance signal and the synchronization signal are not synchronized, the output is not affected and jitter is not affected. Does not occur.

As described above, the first to sixth embodiments are not limited to the NTSC system, and the PA
The effect can be realized in the entire color television system such as the L system and the SECAM system, and the timing chart is not limited to the described one.

〔The invention's effect〕

According to the present invention, a synchronization signal generation circuit is configured to generate a first synchronization signal using a signal having a frequency of an integral multiple of the color subcarrier as a clock, a read clock of the sensor as a clock, and a first synchronization signal. And a unit for generating a second synchronization signal to be added to the luminance signal and the color difference signal from
The luminance signal and the second synchronization signal are synchronized. Therefore, it is possible to prevent the jitter that occurs when digitizing the signal processing, and to obtain the effect of improving the image quality.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a first embodiment of a video camera device according to the present invention, FIG. 2 is a block diagram showing a basic configuration of a conventional video camera device, and FIG. 3 is a sensor clock and a composite circuit. Timing diagram of sync signal,
FIG. 4 is a block diagram showing a basic configuration of a synchronization signal generating circuit in FIG. 1, FIG. 5 is a block diagram showing a basic configuration of a digital signal processing circuit in FIG. 1, and FIG.
FIG. 7 is a block diagram showing an example of the fs section in FIG. 6, FIG. 8 is a timing diagram of the programmable sync signal generating circuit, and FIG. FIG. 10 is a block diagram showing the basic configuration of the fourth embodiment, FIG. 10 is a block diagram showing the basic configuration of the fourth embodiment, FIG. 11 is a block diagram showing the basic configuration of the ninth embodiment, and FIG. FIGS. 13 to 15 are diagrams showing a luminance signal to which a synchronization signal is added, and FIGS. 13 to 15 are block diagrams showing a part of the basic configuration of the sixth, seventh and eighth embodiments. 1 ... Sensor, 2 ... A / D conversion circuit, 3 ... Digital signal processing circuit, 4 ... D / A conversion circuit, 5,52 ... Sensor drive timing generation circuit, 6 ... Synchronization signal generation circuit, 65,66 Programmable synchronization signal generation circuit 7,70 Microcomputer 8 Synchronization signal generation circuit 9 Programmable sensor drive timing generation circuit 10 Control circuit 51,61 Oscillation circuit, 621, 633 horizontal synchronization signal generation circuit, 622 vertical synchronization signal generation circuit, 631 counter, 632 latch circuit, 634 pulse generation circuit, 635 synchronization signal generation circuit, 31 Y / C separation circuit, 32: Y process circuit, 33: C process circuit, 34: Composite sync signal addition circuit, 35: Burst flag signal addition circuit, 36: Modulation circuit, 632a, b ... … Latch circuit, 634a …… Comparison circuit, 634b …… Pulse Raw circuit, 371 ...... signal switch, 372 ...... clock switch, 73 ...... ROM, 74 ...... programmable ROM.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04N 5/232 Z H04N 5/067 H04N 7/18 E

Claims (2)

(57) [Claims] An image pickup device, a first oscillation circuit for generating a first reference signal whose frequency depends on a color television system to be used, and a first reference signal output from the first oscillation circuit A first synchronizing signal generating circuit for generating a first synchronizing signal based on the first and second oscillation signals; a second oscillating circuit for generating a second reference signal having a frequency different from the frequency of the first oscillating circuit; A timing generation circuit for generating a sensor clock for driving the image sensor by phase-locking a synchronization signal and a signal obtained by dividing the frequency of the second reference signal; and a second signal output from the first synchronization signal generation circuit. A second synchronizing signal generating circuit for generating a second synchronizing signal from the synchronizing signal and the sensor clock output from the timing generating circuit; and a luminance signal output from the image sensor and synchronized with the sensor clock. Video camera apparatus characterized by a signal processing circuit for adding a second synchronization signal output from the second synchronous signal generating circuit. 2. The first synchronizing signal generating circuit generates a first horizontal synchronizing signal and a first vertical synchronizing signal, and the second synchronizing signal generating circuit includes a sensor output from the timing generating circuit. A horizontal synchronizing signal generating circuit for generating a second horizontal synchronizing signal synchronized with a clock; a first vertical synchronizing signal generated from the first synchronizing signal generating circuit; and a horizontal synchronizing signal generating circuit generating the horizontal synchronizing signal. A synchronizing signal generating circuit that generates a composite synchronizing signal by synthesizing the second horizontal synchronizing signal, wherein the signal processing circuit adds the decoding synchronizing signal to the luminance signal. The video camera device according to claim 1.