JP2980036B2 - Video camera equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video camera apparatus which can be used for home use, broadcast, surveillance, industrial use such as medical care and inspection, and the like.

[0002]

2. Description of the Related Art Conventionally, a signal processing unit of a video camera is of an analog type.
With the rapid spread of millimeter VTRs, the development of small, lightweight, low-cost VTR-integrated video camera devices has been promoted. As means for achieving these, digitization of a signal processing unit is being promoted.

FIG. 2 is a block diagram showing a basic configuration of a video camera in which a conventional analog signal processing unit is digitized.

In FIG. 2, when a sensor 1 receives an optical signal 11, it is synchronized with a read clock frequency (hereinafter referred to as a sensor clock fs) every horizontal read scanning period, and an analog signal consisting of alternately different color signals is repeated. The pixel signal 12 is output. The operation of the sensor 1 is controlled by a control signal 18 from a sensor drive timing generation circuit (hereinafter referred to as TG) 5. The analog pixel signal 12 is supplied to an analog / digital conversion circuit (hereinafter, A / D conversion circuit).
A / D conversion is performed by 2) to obtain a digital pixel signal 13. The digital signal processing circuit 3 includes a digital pixel signal 13 and a synchronizing signal generation circuit (hereinafter, SS).
G), a synchronization signal 20 and a control signal 23 from 8),
When the control signal 18 is supplied, a luminance signal 14 to which a synchronization signal is added and a color signal 15 to which a synchronization signal is added are generated. These signals 14 and 15 are D / A converted by a digital / analog conversion circuit (hereinafter abbreviated as D / A) 4 and an analog luminance signal 16 to which a synchronization signal is added, and an analog color signal 16 to which a synchronization signal is added. It becomes signal 17.

Hereinafter, the control signal 18 generated in the TG 5, the synchronization signal 20 generated in the SSG 8 and the control signal 23 will be described. First, SSG8 has an oscillation frequency of nfsc (n is an integer, and fsc is the frequency of the color subcarrier).
When a signal having a frequency nfsc is supplied as a clock from the oscillator 61, a horizontal synchronizing signal (hereinafter referred to as CHD) and a vertical synchronizing signal (hereinafter referred to as VD) necessary for generating a signal for driving the sensor are provided. And these two signals 19
Is supplied to TG5. The TG 5 generates a sensor clock fs from the signal supplied from the oscillator 51 and CHD and VD. On the other hand, the SSG 8 uses a synchronization signal 20 such as a composite sync signal (hereinafter, referred to as CSYNC), a composite blanking signal (hereinafter, referred to as CBLK), a burst flag signal (hereinafter, referred to as BF), using nfsc as a clock. Occur. The digital signal processing circuit 3 generates a luminance signal and a color difference signal using the sensor clock fs as a clock, adds a synchronization signal 20 to the two signals, outputs a luminance signal 14, and modulates the color difference signal by a control signal 23. Then, the color signal 15 is output.

A device related to this type is, for example, Japanese Patent Publication No. 63-45153.

[0007]

In the above prior art, when converting the signal processing section of the video camera apparatus from an analog system to a digital system, a luminance signal is synchronized with a sensor clock fs, and a synchronization signal such as CSYNC is synchronized with nfsc. Despite the synchronization, when adding a synchronization signal to the luminance signal,
No consideration has been given to synchronizing the luminance signal and the synchronization signal. FIG. 3 is a timing chart of CSYNC before being added to the sensor clock fs and the luminance signal, and CSYNC after being added. 3, the rising edge 104 of the sensor clock 101 and the falling edge 10 of the CSYNC 102
In the case where 6 is the same, the CSYNC 102 is latched at the rising edge 104, and becomes a signal similar to the CSYNC 102 after being added to the luminance signal.
When the signal is not latched at 04 but is latched at the rising edge 105, the added CSYNC becomes the signal 103. In this case, the difference between the falling timings of CSYNC 102 and CSYNC 103 is 1 / fs. For example, if the number of pixels in the H direction of the sensor is 550, 1 / f
s ≒ 1H / 550 = 115 ns. In the case of such a deviation, a jitter occurs in the output image that can be detected by human eyes.

Furthermore, since the horizontal read clock frequency of the sensor is conventionally fixed, there is a problem that it is not possible to cope with a sensor having a clock frequency different from that, and there is no versatility.

An object of the present invention is to provide a digital signal processing circuit which does not cause jitter in an output image, further provide a programmable SSG, and control the microcomputer to make the timing of a synchronization signal variable so that a sensor of various specifications can be provided. Another object of the present invention is to provide a video camera device that can cope with the above.

[0010]

The first or second means is employed as means for preventing the above-mentioned jitter, and the third means is employed as means for supporting a multi-sensor.

The first means includes an nfsc section for generating a horizontal synchronizing signal and a vertical synchronizing signal for a camera using a signal having a frequency of nfsc as a clock, and a synchronizing signal for television using a sensor clock fs generated by a TG as a clock. A synchronizing signal generation circuit including an fs unit for generating a signal is provided.

The second means includes a signal switching circuit for alternately supplying a luminance signal and a television synchronization signal to the D / A, and a clock having a frequency of nfs as the D / A clock.
This configuration has a clock switching circuit for alternately supplying the clock c and the sensor clock fs.

Next, the third means is a sensor clock fs
A programmable SSG capable of changing the timing of a television synchronizing signal generated in the fs section, and a microcomputer controlling the same, in order to be able to support various sensors without depending on the fs. It is configured.

[0014]

In the first means, when a clock having a frequency of nfsc is supplied, the nfsc section performs timing generation processing by a counter or the like, and outputs a horizontal synchronizing signal (CHD) for the camera.
And a vertical synchronizing signal (VD).
To supply. The TG generates a sensor clock fs based on a signal synchronized with the CHD, and supplies several types of control signals such as the sensor clock fs to the digital signal processing circuit and the fs unit in the SSG. The digital signal processing circuit performs signal processing using the sensor clock fs as a clock to generate a luminance signal and a color difference signal. On the other hand, the fs section also generates a synchronization signal such as a composite sync signal for television using the sensor clock fs as a clock. Therefore, since the luminance signal and the synchronization signal are synchronized with the sensor clock fs, the luminance signal and the synchronization signal are synchronized. Therefore, when adding a synchronization signal to a luminance signal in the digital signal processing circuit, no large timing shift occurs, and thus no jitter occurs.

In the second means, the signal switching circuit is switched to the synchronizing signal side at a point in time when the luminance signal level is constant (point A) during the horizontal blanking period and before entering the horizontal blanking period, and The clock switching circuit is switched to the nfsc side, a synchronizing signal is input, and the clock is supplied to the D / A conversion circuit using nfsc as a clock to output an analog synchronizing signal. Next, at the same time (point B) during the horizontal blanking period and after the luminance signal level has passed from the horizontal blanking period, the signal switching circuit and the clock switching circuit are connected to opposite sides, An analog luminance signal is output by the same processing as in the above. Therefore, at the points A and B, even if the luminance signal and the synchronization signal are not synchronized, no jitter occurs because the luminance signal level is constant.

In the third means, when timing data is supplied from the microcomputer, a control signal such as a sensor clock fs is supplied from the TG, and a vertical synchronizing signal is supplied from the nfsc unit, the fs unit stores the timing data in a state holding circuit. And processes the value of the counter using the sensor clock fs as a clock and the timing data held in the state holding circuit to generate a horizontal synchronizing signal, which is supplied from the nfsc unit and the horizontal synchronizing signal. A synchronizing signal is generated by synthesizing the vertical synchronizing signals. As described above, if the timing data supplied from the microcomputer to the fs unit is data conforming to the specifications of the sensor being used, a synchronization signal suitable for the sensor can be generated, and multi-sensor compatibility can be realized.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the basic configuration of the video camera device according to the first embodiment. This is sensor 1
An analog / digital conversion circuit (A / D) 2, a digital signal processing circuit 3, a digital / analog conversion circuit (D / A) 4, a sensor drive timing generation circuit (TG) 5, an oscillation circuit 51, , Synchronization signal generation circuit (S
SG) 6 and an oscillation circuit 61.

Hereinafter, the operation of the video camera device having the above configuration will be described. When the sensor 1 receives the optical signal 11,
In each horizontal scanning period, an analog pixel signal 12 composed of alternately repeated different color signals is output in synchronization with the sensor clock having the frequency fs. The operation of the sensor 1 is TG
5 is controlled by a control signal 18. When the analog pixel signal 12 is supplied from the sensor 1, the A / D2
Converts the analog pixel signal 12 into a digital pixel signal 13 and supplies the digital pixel signal 13 to the digital signal processing circuit 3. When the digital signal 13 is supplied from the A / D 2, the control signal 18 is supplied from the TG 5, and the synchronization signal 20 and the control signal 23 are supplied from the SSG 6, the digital signal processing circuit 3 outputs the luminance signal 1 to which the synchronization signal is added.
4 and a color signal 15 to which a synchronization signal is added, and supplies these two signals 14 and 15 to the D / A 4. Luminance signal 1 to which a synchronization signal is added from digital signal processing circuit 3
4 and the chrominance signal 15 to which the synchronization signal is added, the D / A 4 converts the two signals 14 and 15 into analog signals, and outputs a luminance signal 16 to which an analog synchronization signal is added and an analog signal The color signal 17 to which the synchronization signal is added is output. Note that the SSG 6 generates a synchronization signal 20 from the control signal 18 supplied from the TG 5. The TG 5 generates the control signal 18 based on the synchronization signal 19 supplied from the SSG 6 and the reference signal 50 supplied from the oscillation circuit 51.

FIG. 4 is a block diagram showing the structure of the SSG 6 more specifically. In FIG. 4, SSG6 is nfs
The nfsc unit 62 includes a horizontal synchronizing signal generating circuit 621 and a vertical synchronizing signal generating circuit 622, and the fs unit includes a horizontal synchronizing signal generating circuit 6.
33 and a synchronization signal generation circuit 635. Below, SS
The operation of G6 will be described.

First, in the nfsc section 62, the oscillation circuit 6
When the signal 60 having the frequency nfsc is supplied from 1, the horizontal synchronization signal generation circuit 621 generates a horizontal synchronization signal 623,
These are supplied to the vertical synchronization signal generation circuit 622. When the horizontal synchronization signal 623 is supplied from the horizontal synchronization signal generation circuit 621, the vertical synchronization signal generation circuit 622 generates a vertical synchronization signal 625 and supplies these to the synchronization signal generation circuit 635 in the fs section. Further, the nfsc section includes a signal (CHD) 624 necessary for generating a signal for performing horizontal driving of the sensor 1 among the horizontal synchronization signals 623 and a vertical synchronization signal 6.
25, a signal (VD) 625 required to generate a signal for performing vertical driving of the sensor 1 is used as a control signal 19 as T
Supply to G5. When the control signal 19 is supplied from the SSG 6, the TG 5 locks the phase of the signal obtained by dividing the reference signal 50 supplied from the oscillation circuit 51 and the CHD, and further outputs a signal such as a sensor clock having a frequency fs from the reference signal 50. It generates the control signal 18 and supplies the control signal 18 to the fs unit 63 of the SSG 6. When the control signal 18 is supplied,
The horizontal synchronizing signal generation circuit 633 generates a horizontal synchronizing signal 638 synchronized with the sensor clock fs.
38 is supplied to the synchronization signal generation circuit 635. When the vertical synchronizing signal 625 is supplied from the vertical synchronizing signal generating circuit 622 and the horizontal synchronizing signal 638 is supplied from the horizontal synchronizing signal generating circuit 633, the synchronizing signal generating circuit 635 generates the synchronizing signal 20 (CSY).
NC, CBLK, BF) and supplies the synchronization signal 20 to the digital signal processing circuit 3. Here, since the horizontal synchronization signal 638 and the vertical synchronization signal 625 are synchronized with the sensor clock fs, the synchronization signal 20 is also synchronized with the sensor clock fs.

FIG. 5 is a block diagram showing the configuration of the digital signal processing circuit 3 more specifically. In FIG.
The digital signal processing circuit 3 includes a Y / C separation circuit 31,
Y process circuit 32, C process circuit 33, CSY
NC addition circuit 34, BF addition circuit 35, modulation circuit 3
Consists of six. Hereinafter, the operation of the digital signal processing circuit 3 will be described.

When the digital pixel signal 13 is supplied from the A / D 2, the Y / C separation circuit 31 outputs the first pixel signal 30.
1 and a second pixel signal 302 are generated, and the two signals are supplied to the Y process circuit 32 and the C process circuit 33, respectively. First pixel signal 301 from Y / C separation circuit 31
And the second pixel signal 302, the Y process circuit 32 generates a luminance signal 303 and supplies the luminance signal 303 to the CSYNC adding circuit 34. Further, when the first pixel signal 301 and the second pixel signal 302 are supplied from the Y / C separation circuit 31, the C process circuit 33 generates a color difference signal 304 and supplies this to the BF addition circuit 35. Note that Y / C
The separation circuit 31, the Y process circuit 32, and the C process circuit 33 are controlled by the control signal 18 supplied from the TG 5, and are synchronized with the sensor clock fs. Therefore, the luminance signal 303 and the color difference signal 304 are also synchronized with the sensor clock fs. SSG
6 is supplied from the CSYNC 305
, CBLK 306, and BF 307.
When the luminance signal 303 is supplied from the Y process circuit 32 and the CSYNC 305 and CBLK 306 are supplied from the SSG 6, the CSYNC adding circuit 34 generates the luminance signal 14 to which the synchronization signal is added. On the other hand, the color difference signal 304 from the C process circuit 33 is transmitted from the SSG 6 to the BF 305 and the CBL
When K306 is supplied, the BF adding circuit 35 generates a color difference signal 308 to which the synchronization signal is added, and supplies this to the modulation circuit 36. When the color difference signal 308 to which the synchronization signal is added from the BF addition circuit 35 and the control signal 23 are supplied from the SSG 6, the modulation circuit 36 generates the color signal 15 to which the synchronization signal is added. Then, the luminance signal 14 and the chrominance signal 15 to which the synchronizing signal has been added are converted into analog signals by the D / A 4 to become analog luminance signals 16 and chrominance signals 17.

As described above, according to this embodiment, the signal processing is controlled by the sensor clock, and the synchronizing signal is also generated from the sensor clock. Therefore, the digital luminance signal and the synchronizing signal are synchronized. Has the effect of preventing jitter when synthesizing.

Next, a second embodiment of the present invention will be described with reference to the drawings. The basic configuration of the video camera device of this embodiment is almost the same as that of FIG. 1, except that the SSG 6 in FIG. 1 is replaced by a programmable SSG 65 and a microcomputer 7 for controlling the SSG 6 is provided. FIG. 6 is a block diagram showing the configuration of the programmable SSG 65 and the microcomputer 7 more specifically. In FIG. 6, SSG6 is nfs
The fs unit 64 comprises a c unit 62 and an fs unit 64.
31, a latch circuit 632, and a horizontal synchronizing signal generation circuit 6.
34 and a synchronization signal generation circuit 635. Where n
The configuration and operation of the fsc unit 62 and the synchronization signal generation circuit 635 are the same as those of the SSG 6. FIG. 7 is a diagram showing an example of the configuration of each block in the fs unit 64. 7, a latch circuit 632 includes a latch circuit 632a and a latch circuit 632b, and a horizontal synchronizing signal generation circuit 634.
Comprises a comparison circuit 634a and a pulse generation circuit 634b.

Here, the signal 22 is timing data supplied from the microcomputer 7, and the timing data 22a
And an address 22b. A signal 639 and a signal 640 are output signals of the comparison circuit 634a.
8 is a horizontal synchronizing signal. FIG. 8 shows the horizontal synchronization signal 6.
FIG. 18 is a timing chart in the process of generating the information 38; Hereinafter, the operation of the SSG 65 and the microcomputer 7 will be described with reference to FIGS. 6, 7, and 8.

In FIG. 6, the microcomputer 7 supplies the first timing data 22 for generating a synchronization signal adapted to the specifications of the sensor 1 to the latch circuit 632, and the latch circuit 632 holds the timing data 22a. However, which of the latch circuits 632a and 632b in FIG. 7 holds the timing data 22a is determined by the address 22b. Here, as an example, the value a is held in the latch circuit 632a, and the value (a + b) is held in the latch circuit 632b. When the control signal 18 is supplied from the TG 5, the counter 631 counts using the sensor clock fs as a clock, and supplies a counter value 636 to the comparison circuit 634 a in the horizontal synchronization signal generation circuit 634. When the timing data 637a and 637b are supplied from the latch circuit 632 and the counter value 636 is supplied from the counter 631, the comparison circuit 634a converts the counter value 636 into the timing data 637a or 63.
Check if it matches 7b, and if it does not match, 1
, And outputs 0 if they match. That is, the comparison circuit 364
a outputs the signal 639 and the signal 640 in FIG. When the signals 639 and 640 are supplied, the pulse generation circuit 634b generates a horizontal synchronization signal 638 shown in FIG.
5 Then, the vertical synchronizing signal 625 from the vertical synchronizing signal generating circuit 622 is
When the horizontal synchronizing signal 638 is supplied from, the synchronizing signal generating circuit 635 generates synchronizing signals CSYNC, CBLK and BF, and supplies these three synchronizing signals 20 to the digital signal processing circuit 3. The subsequent operation is the same as that of the first embodiment.

As described above, in the second embodiment, the fs unit 64
Only the configuration shown in FIG. 7 is shown. However, in practice, a plurality of components having the same configuration as the latch circuit 632 and the horizontal synchronization signal generation circuit 634 in FIG. Can be generated. And 6
Reference numeral 32 is not limited to a latch circuit, but may be any as long as it has a function of holding a state.

As described above, according to the present embodiment, the timing of the horizontal synchronizing signal can be varied by providing the programmable SSG and the microcomputer for controlling the same, so that the synchronizing signal suitable for the specification of the sensor to be used is generated. It has the effect of supporting multiple sensors.

Next, a third embodiment of the present invention will be described.
The basic configuration of the video camera device of this embodiment is substantially the same as the configuration shown in FIG. 1 except for the portion shown in FIG. 9, and the operation of each block is also the same. In FIG. 9, the video camera device of this embodiment includes a programmable TG 9 and a microcomputer 7 that controls the programmable TG 9.
Is provided. Timing data 2 from microcomputer 7
When the synchronization signal 19 is supplied from the SSG 6, the programmable TG 9 uses the same method as that performed by the fs unit 64 of the programmable SSG 65 in the second embodiment to control the required timing. Occurs.

As described above, according to the present embodiment, there is an effect that the sensor drive pulse and the control signal for signal processing can be changed according to the sensor and system configuration.

Next, a fourth embodiment of the present invention will be described.
FIG. 10 is a block diagram showing a basic configuration of the video camera device of the present embodiment. This is the sensor 1, A / D2,
Digital signal processing circuit 3, D / A 4, TG 52
, A programmable SSG 66, a control circuit 10, and an oscillation circuit 51.

Hereinafter, the operation of the video camera device having the above configuration will be described. However, the operations of the sensor 1, the A / D2, the digital signal processing circuit 3, and the D / A4 are the same as those of the video camera device of the first embodiment. I do. First, the oscillation circuit 51 supplies the reference signal 50 to the TG 52. When the reference signal 50 is supplied from the oscillation circuit 51, the TG 52 divides the frequency of the reference signal 50 to generate the sensor clock f.
A control signal 191 such as s and a sensor drive signal 181 for driving the sensor 1 are generated and supplied to the programmable SSG 66 and the sensor 1, respectively. The programmable SSG 66 includes a circuit similar to the fs unit 64 in FIG. 6, and outputs timing data 22 for generating a synchronization signal adapted to various sensors from outside the programmable SSG 66 to a control signal such as a sensor clock fs from the TG 52. When 191 is supplied, the synchronizing signal 2 synchronized with the sensor clock fs is operated by the same operation as the fs unit 64.
0 and a control signal 25 are generated and supplied to the digital signal processing circuit 3 and the control circuit 10, respectively. When the control signal 25 is supplied from the programmable SSG 66, the control circuit 10 supplies a control signal 26 such as a clock to the A / D 2 and a control signal 27 such as a sensor clock fs to the digital signal processing circuit 3. Thereafter, the video camera device of the present embodiment performs the same operation as the video camera device of the first embodiment again as described above, and outputs analog luminance signals and color signals to which a synchronization signal is added.

As described above, according to the present embodiment, the provision of the programmable SSG 66 capable of generating synchronization signals at different timings depending on data supplied from the outside provides an effect corresponding to a multi-sensor.

Next, a fifth embodiment of the present invention will be described.
The basic configuration of the video camera device of this embodiment is the same as that of FIG. 10 in which the microcomputer 7 and the input terminal 71 for rewriting data are provided. In FIG. 10, the microcomputer 7 inputs data 72 from an input terminal 71, temporarily holds the data 72, supplies the data 72 as timing data 22 to the programmable SSG 66, and stores the data 72 in the programmable SSG 66. The existing timing data. However, the data 72 is not limited to the timing data 22, and the microcomputer 7 is not limited to the above-mentioned operation, and can control other circuits as needed based on the data 72.

As a sixth embodiment, as shown in FIG. 13, the ROM 72 is provided in FIG. 10 so that the data 72 is stored in the ROM 73. It can also be supplied.

As described above, according to the fifth and sixth embodiments, the microcomputer 7 and the ROM 73 for storing the data 72 supplied to the microcomputer 7 are provided.
And the programmable SSG 66 controlled by the microcomputer 7 can generate the synchronizing signal 20 adapted to the sensor 1, which has an effect corresponding to the multi-sensor. Also, there is an effect that the setup at the time of starting the video camera device can be automatically performed.

As a seventh embodiment, the configuration shown in FIG. 13 is changed to the configuration shown in FIG. 14, and data similar to the data 72 is stored in the ROM 73.
Data 22 which is a part of the data stored in
Is directly supplied to the programmable SSG 66, the same effect as in the fifth and sixth embodiments can be obtained.

Next, an eighth embodiment of the present invention will be described with reference to the drawings. The basic configuration of the video camera device of the present embodiment is almost the same as that of FIG. 10, except for the point shown in FIG. In FIG. 15, the microcomputer 70 stores several types of timing data for each system, and the programmable ROM 74 stores codes and control data assigned to each system. Also, the input terminal 76
Supplies the system selection data 78 to the microcomputer 70 from outside. When the system selection data 78 is supplied, the microcomputer 70 reads out the system data 77 including the code and the control data specified by the selection data 78 from the programmable ROM 74, and reads out the various timing data stored in the microcomputer 70 from among the various timing data. The timing data 22 specified by the code is stored in the programmable SSG6
6 and the control data is supplied to a control circuit 10. Other operations are the same as the operations of the video camera device of the fourth embodiment.

As described above, according to the present embodiment, the video camera apparatus can be automatically set to a state where it can operate normally only by supplying the system selection data 78 from the input terminal 76. There is an effect of improvement.

Next, a ninth embodiment of the present invention will be described with reference to the drawings. The basic configuration of the video camera device of this embodiment is almost the same as that of FIG.
21 except that the luminance signal processing unit in the portion 37 surrounded by the dotted line is different. FIG. 11 is a diagram showing a D / A converter for a luminance signal and a synchronizing signal of the video camera device of the ninth embodiment. The D / A converter includes a signal switch 371
And a clock switch 372. (Also, FIG.
FIG. 3 is a diagram showing a luminance signal to which a synchronization signal is added. The basic operation of the video camera device of this embodiment is substantially the same as the operation of the conventional video camera device shown in FIG. 2 except for the D / A conversion unit. Only the operation will be described. First, in the AB section in FIG. 12, the signal switch 371 connects the terminals 374 and 375, supplies the synchronization signal 20 to the D / A4, the clock switch 372 connects the terminals 377 and 378, and the frequency n
The fsc clock is supplied to the D / A4 clock 24.
At this time, the D / A 4 converts the synchronization signal 20 into an analog signal using the nfsc clock as a clock, and outputs the analog signal. Next, at time B in FIG.
1 is switched to the terminal 373 and the luminance data 303 is changed to D /
A4, the clock switch 372 switches to the terminal 376, and the frequency f, which is one of the control signals 18,
The s sensor clock is supplied to the clock 24 of the D / A 4. At this time, the D / A 4 converts the luminance signal 303 into an analog signal using the sensor clock fs as a clock, and outputs the analog signal. This operation is performed until B-A 'until the next time A'.
When the time A 'is reached, the signal switch 37
1 and the clock switch 372 are respectively connected to the opposite terminals, and the same operation as in the AB section is performed. Thereafter, the above operation is repeated. In FIG. 12, sections C, D, and C, which include switch switching points A, B, A ', and B', are shown.
The luminance signal levels of C 'and D' are all constant.

As described above, according to the present embodiment, the switching between the D / A conversion of the luminance signal and the synchronization signal is performed when the level of the luminance signal is constant on both sides of the horizontal blanking period. Even if the synchronizing signal is not synchronized, the output is not affected and no jitter occurs.

As described above, the effects of the first to sixth embodiments can be realized not only in the NTSC system but also in general color television systems such as the PAL system and the SECAM system.
Timing diagrams are not limited to those described.

[0044]

According to the present invention, the synchronization signal generating circuit
A section for generating a horizontal synchronizing signal and a vertical synchronizing signal by using a signal having a frequency of K (K is a number dependent on color television) of the color subcarrier, a luminance signal and a horizontal reading clock of the sensor as a clock. A configuration including a section that generates a synchronization signal to be added to the color difference signal, and a configuration in which the luminance signal before the addition of the synchronization signal is generated using the horizontal read clock of the sensor as a clock, enables synchronization with the luminance signal. Since the signals are synchronized, jitter generated by digitizing the signal processing can be prevented, and the effect of high image quality can be obtained.

Also, by providing a circuit for switching the D / A conversion between the luminance signal and the synchronizing signal when the luminance level is constant on the left and right sides of the horizontal blanking period, an image free of jitter can be obtained.

Further, by providing a programmable synchronizing signal generation circuit and a sensor drive timing generation circuit, and a microcomputer for controlling these circuits, it becomes possible to cope with multi-sensors, improve versatility, and reduce cost. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a first embodiment of a video camera device according to the present invention.

FIG. 2 is a block diagram showing a basic configuration of a conventional video camera device.

FIG. 3 is a timing chart of a sensor clock and a composite sync signal.

FIG. 4 is a block diagram showing a basic configuration of a synchronization signal generating circuit in FIG. 1;

FIG. 5 is a block diagram showing a basic configuration of the digital signal processing circuit in FIG. 1;

FIG. 6 is a basic configuration diagram of a programmable synchronization signal generation circuit according to a second embodiment.

FIG. 7 is a block diagram showing an example of an fs unit in FIG. 6;

FIG. 8 is a timing chart of the programmable synchronization signal generation circuit.

FIG. 9 is a block diagram showing a basic configuration of a third embodiment.

FIG. 10 is a block diagram showing a basic configuration of a fourth embodiment.

FIG. 11 is a block diagram showing a basic configuration of a ninth embodiment.

FIG. 12 is a diagram showing a luminance signal to which a synchronization signal is added.

FIG. 13 is a block diagram showing a part of the basic configuration of the sixth, seventh and eighth embodiments.

FIG. 14 is a block diagram showing a part of the basic configuration of the sixth, seventh, and eighth embodiments.

FIG. 15 is a block diagram showing a part of the basic configuration of the sixth, seventh and eighth embodiments.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Sensor, 2 ... A / D conversion circuit, 3 ... Digital signal processing circuit, 4 ... D / A conversion circuit, 5,52 ... Sensor drive timing generation circuit, 6 ... Synchronization signal generation circuit, 65,6
6: Programmable synchronization signal generation circuit, 7, 70: microcomputer, 8: synchronization signal generation circuit, 9: programmable sensor drive timing generation circuit, 10: control circuit, 51, 61: oscillation circuit, 621, 633: horizontal Synchronization signal generation circuit, 622... Vertical synchronization signal generation circuit, 6
31 counter, 632 latch circuit, 634 pulse generation circuit, 635 synchronization signal generation circuit, 31 Y / C separation circuit, 32 Y process circuit, 33 C process circuit, 34 composite sync signal addition circuit , 35 ...
Burst / flag signal addition circuit, 36 modulation circuit, 63
2a, b: latch circuit, 634a: comparison circuit, 634b
... Pulse generation circuit, 371 ... Signal switch, 372 ... Clock switch, 73 ... ROM, 74 ... Programmable ROM.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 5/232 H04N 5/067 H04N 5/335

Claims (7)

(57) [Claims] In a video camera device using a solid-state imaging device and digitized signal processing, a counter for inputting a clock synchronized with a horizontal read clock of the solid-state imaging device, and a timing of a phase change of a horizontal synchronization signal are provided. A latch circuit for holding timing data to be determined, and comparing the output of the counter and the output of the latch circuit,
Video camera device, characterized by chromatic <br/> a pulse generating circuit for generating a horizontal synchronizing signal obtained by changing the timing of the phase change, and a programmable synchronizing signal generator composed on the basis of the comparison result . 2. The video camera device according to claim 1, further comprising a microcomputer for controlling rewriting of the timing data held in the latch circuit. 3. A ROM for storing the timing data
When,  Inputting the timing data stored in the ROM
Input terminal for temporarily storing the timing data.
And the timing data is programmable.
Microcomputer to supply the synchronization signal generation circuit
AndThe video camera according to claim 1, wherein the video camera is provided.
Mela device. 4. The video camera device according to claim 1, further comprising a ROM that stores the timing data and supplies the timing data to the programmable synchronization signal generating circuit. 5. For several types of video camera systems
The timing data is stored in advance and the timing data is stored.
For supplying the data to the programmable synchronization signal generation circuit.
Icro ComputerWhen,  A code assigned to each video camera system;
A program that stores control data set for each system
Gramable ROMAndThe microcomputer is provided with the programmable R
Select the code and control data supplied from OM
Input terminal for externally supplying data for
2. The video camera according to claim 1, wherein
LA device. 6. A video camera apparatus using a solid-state imaging device and digitized signal processing, wherein a first clock whose frequency depends on a color television system to be used is input, and a first horizontal synchronizing signal and a first horizontal synchronizing signal are inputted. A first synchronization signal generator for generating a vertical synchronization signal, a counter synchronized with the horizontal synchronization signal and receiving a second clock synchronized with a horizontal read clock of the solid-state imaging device; A latch circuit that holds timing data indicating a timing of a phase change of a signal; a pulse generation circuit that compares an output of the counter with an output of the latch circuit and generates a second horizontal synchronization signal according to the comparison result; By synthesizing the vertical synchronizing signal generated from the first synchronizing signal generating section and the second horizontal synchronizing signal generated from the pulse generating circuit. A programmable synchronization signal generation circuit having a second synchronization signal generation section having a synchronization signal generation circuit for generating a composite synchronization signal, and a microcomputer controlling rewriting of timing data held in the latch circuit. A video camera device characterized by the above-mentioned. 7. A video camera apparatus using a solid-state imaging device and digitized signal processing, wherein a programmable synchronization signal generation circuit for generating a synchronization signal and a timing of the synchronization signal generated by the programmable synchronization signal generation circuit are controlled. A video camera device comprising: