KR960004005B1 - Television deflection apparatus - Google Patents

Abstract

No content.

Description

TV deflector

FIG. 1, comprising FIGS. 1A and 1B, illustrates a vertical scan generator including a sawtooth generator embodying features of the present invention.

2b to 2c are waveform diagrams useful for explaining the circuit operation of FIG.

3 is a block diagram of a television receiver comprising the sawtooth generator of FIG.

4A to 4D are waveform diagrams showing the television receiver operation of FIG.

5 is an alternative schematic diagram of a tooth generator embodying another feature of the invention of FIG.

6A to 6C are waveform diagrams useful for explaining the operation of the configuration of FIG.

* Explanation of symbols for main parts of the drawings

18: transistor 19: diode

20: Resin Control Circuit 64: Vertical Scan Generator

70: timing unit 100: vertical deflection circuit

240: Memory 244,246,248: D / A converter

250,252,254: low pass filter 260: display

501 vertical oscillation circuit 702 input terminal

704,706,708,720,802,804,806,810,812: resistance

712 capacitor

[Field of Invention]

TECHNICAL FIELD The present invention relates to television deflection systems, and more particularly to systems configured to increase the field rate (frequency) of a displayed image to reduce the visibility of flicker.

[Background of invention]

The limit for recognizing field flicker in a television display system is a function of the brightness and flicker frequency of the display. Over the years, the brightness of the display has been increased to a point where flicker is relatively noticeable in relatively high field rate systems (such as NTSC 60 Hz systems) and in low field rate systems (such as PAL 50 Hz systems). The solution to this problem is to double the field rate of the displayed image. In one prior art system, the video input signal is stored in the field memory, where each stored field is recovered from the field memory or " read " twice and scanned on the twice scanned line rate and the field rate of the input video signal. By doubling, the flicker frequency of the displayed image is doubled to reduce flicker visibility (i.e., the amount of flicker is reduced).

W. US Patent Application No. 857,375, a television display system having a flicker reduction processor of the name of the invention corresponding to Taiwan Patent Application No. 75-101655, filed November 1, 1986 to Den Hollander et al. A television display device is described. In an apparatus such as Hollander, an interlaced baseband television signal having a predetermined field rate is provided. The memory has first and second input periods for recovering a field previously stored twice during a recording period for applying a video output signal having a predetermined predetermined field rate, and a recording period for storing a field of an input signal. The output signal provides image information to be displayed on the display device. The timing unit responds to the video input signal, applies a read control signal having a pulse waveform repeated in two field units to the memory, and applies a vertical synchronization signal having a pulse waveform repeated in four field units to the display. do. The pulses of the vertical sync pulse waveform are phase modulated in units of fields at a frequency of twice the predetermined field rate. The vertical sync pulse waveform pattern is selected to provide an image displayed on the display where the even field is placed on the even field, the radix field is placed on the radix field, and the even and odd field pairs are interlaced scanned. Each pulse of the vertical sync signal starts at the corresponding vertical retrace interval. The pulses of the vertical sync pulse waveform result in a corresponding phase modulation of the vertical deflection current. The corresponding vertical scanning period is also changed in units of fields by the pulse and is repeated in units of four fields.

Conventional vertical deflection circuits may include a sawtooth generator synchronized to a synchronization signal generating a sawtooth waveform drive signal. During the retrace, the capacitor is discharged by the switch and during the trace it is charged by the current source. The drive signal is coupled to a switching circuit that generates a current of a corresponding sawtooth waveform. Since the drive signal includes a ramping portion corresponding to the vertical trace, the start time of the ramping portion corresponds to a deflection current causing a scan on top of the raster of the display.

For example, due to the phase modulation of the pulse waveform of the vertical synchronization signal, the peak amplitude of the driving signal at the end of the vertical trace may also change from field to field according to the pulse waveform shape due to the above-described configuration of the Hollander.

The start time of the ramping portion is different with respect to the corresponding pulse of the vertical synchronizing signal which affects the ramping portion by the different peak amplitude of the drive signal. The discharge time of the sawtooth generator capacitor may vary in other fields since it may vary depending on the peak amplitude of the drive signal. As a result, the trace portion phase of the deflection current may be changed not advantageously from the setting by the phase modulated vertical synchronization signal. Thus, the even field must be placed on the even field, the radix field must be placed on the radix field, and the even and radix field pairs must not fully meet the requirement that they be interlaced.

[Overview of invention]

Therefore, it is preferable that in each deflection period, for example, the start time of the ramp portion of the drive signal is hardly affected by a change in magnitude such as the peak amplitude of the drive signal.

According to one aspect of the invention, a television deflection device responsive to a synchronous input signal at a frequency associated with a deflection frequency generates a control signal at a frequency associated with the modulated phase and the input signal frequency. The sawtooth generator responsive to the control signal generates a second signal of the sawtooth waveform synchronized by the control signal. In a predetermined deflection period, the second signal is modulated in the control signal phase at the start time of the first ramp of the second signal when the second signal starts ramping in the first direction in each deflection period. It has a first ramping portion that changes in the first direction and a second ramping portion that changes in the same opposite direction so as to be at a predetermined level that is not affected by it. A deflection current having a sawtooth waveform according to the second signal is coupled to the deflection lead. The deflection current has a trace portion during a trace period corresponding to the first portion of the second signal.

The trace portion of the deflection current is phase modulated in accordance with the control signal. The trace part is maintained in phase according to the control signal in each deflection period when the control signal phase changes.

In FIG. 1B, a double frequency sync pulse 2V 'is coupled to the vertical oscillation circuit 501 of the vertical scan generator 64 embodying features of the present invention. The sync pulse 2V 'is applied to the input terminal 702 of the inverting amplifier U1 biased by the voltage formed between the resistor 704 and the resistor 706. The phase modulated pulse 2V 'is generated in a manner to be described later. Pulse 2V 'has a frequency of 2fv where fv is the vertical synchronization frequency of the baseband television signal, such as the NTSC or PAL standard. The pulse 2V 'is divided into corresponding intervals of different periods, and the nominal period is 1 / 2V. V represents 20 millisecond vertical scan interval in the PAL standard.

The transition from high to low of pulse U1a at the output terminal of amplifier U1 occurs when the leading edge 900 of pulse 2V 'occurs. The resistor 708 of pulse U1a is coupled in the form of pulse U1b to the corresponding non-inverting input terminal of amplifier U2 and amplifier U3 and the inverting input terminal of amplifier U4. Thus, amplifier U4 is in the form of pulse V _U4 at the output terminal. The pulse V _U4 has a waveform of the same width and polarity as the synchronous pulse 2V 'shown during the interval t ₀ -t ₂ of FIG. 2A.

Amplifiers U2 and U3 are combined in feedback mode to form a vertical oscillator. As a result of the positive feedback path formed by the resistor 720 of FIG. 1b, the resistance is coupled between the non-inverting input terminal and the output terminal of the amplifier U3, and the pulse U1b is pulsed for example during the interval t ₀ -t ₂ of FIG. 2a. Maintain a low level that keeps V _U4 at a high level. At the same time, the capacitor 712 is quickly discharged by the amplifier of FIG. When the inverting input terminal voltage of the amplifier U3 corresponding to the voltage across the capacitor 712 is lower than the corresponding level of the pulse U1b, the amplifier U3 stops conducting and the output voltage U3a goes high. In any case, pulse U1b remains low until the falling section 901 of pulse 2V 'occurs. Conversely, pulse V _U4 remains high over the interval between rising section 900 and falling sections 901 of pulse 2V '. In the case where pulse 2V 'is missing, pulse V _U4 is obtained from the output of amplifier U3 and derived from applied pulse U3a of amplifier U4 via resistor 720.

Pulse V _U4 is coupled to generate ramp voltage V _D of FIG. 2B and to control ramp generation circuit 500 embodying features of the present invention. The ramp generation circuit 500 includes a current source transistor Q2 biased with resistors R ₀ , R _1, R _2, and R ₃ to supply current to the current integration capacitor C ₀ coupled in parallel with the conduction path of transistor switch Q1. Generator 500 generates output ramp voltage V ₀ shown in a straight line in FIG. 2B. Capacitor C ₀ of FIG. 1B starts to discharge when the rising period 900 of pulse 2V occurs and discharges to the saturation voltage level of transistor Q1 before the falling period of each pulse V _U4 as before the time of FIG. 2B. Claim by one degree pulse V _U4 transistor Q1 is not to ramp up the voltage V _O to the previous falling edge of the clamp doemeurosseo voltage V _D to the saturation voltage level of the transistor Q1 the pulse V _U4.

The phase modulation of the FIG. 2a pulse V _U4 divided into the intervals having the corresponding different lengths results in different peak values of the ramp voltage V ₀ as at times t ₀ , T _3, t ₆ and t ₉ of FIG. 2b respectively. It becomes.

Up-ranging of the first voltage V ₀ portion occurs for a period equal to the interval t ₂ -t ₃ of FIG. 2b. The first voltage portion starts to ramp up from a predetermined constant level, which is the saturation voltage of transistor Q1 in FIG. 1b which is not affected by the phase modulation of synchronous pulse 2V '. Thus, upramping the first voltage portion starts to upramp at the same time as time t ₂ in FIG. 2b. Downramping of the second voltage V _D part occurs, for example, during the interval t ₀ -t ₂ . The flat third voltage portion occurs during the interval t ₁ -t ₂ .

According to one embodiment of the present invention, the sum of the intervals corresponding to the second and third portions is a predetermined constant that is not affected by the peak value of the first degree voltage V ₀ . As in the interval t _0- t ₂ of FIG. 2b, the interval between the start time of the upramping part and the start of the downramping part of voltage V ₀ can be maintained, which is influenced by the phase modulation of the first degree pulse 2V ′. It is constant not to receive.

The width of the sync pulse 2V 'generated by the timing unit 70 of FIG. 3 is adjusted by a coupled monostable multivibrator, for example, as shown by the dashed line in FIG.

Ramp voltage V ₀ is DC biased by resistors 802, 804, 806 and buffered by amplifier U5. The output of amplifier U5 is applied to a linear correction circuit, denoted 808, which generates a smooth linear correction signal, which correction signal forms a ramp voltage V _O having the characteristics described above for the linearly electrostatic ramp voltage V ₀ . Resistor 810,812 is added to the output signal of amplifier U5.

As shown in FIG. 1B, the present invention includes a switched vertical deflection circuit 100 controlled by the vertical control circuit 20 of the vertical scan generator 64. The operation of deflection circuit 100 and control circuit 20 is described in detail in US Pat. No. 4,544,864, entitled PE Switched Vertical Deflection Circuit with Bi-Directional Power Supply. The control circuit 20 provides the switching element 21 with a switching signal, line rate or horizontally modulated width, according to the voltage V _O , shown as having an integrated transistor 18 and an anti-parallel diode 19. Transistor 18 may be configured as a field effect transistor, which is advantageous when the horizontal rate is higher than the horizontal frequency, eg, the PAL standard. Such high frequencies may be used in computer monitors or video display terminals. The switching element 21 is coupled to the terminal of the storage capacitor 126 via the coil 23 of the coil 23 of the series of flyback transformers 24 coupled to the storage coil 25. The terminal 126 of the capacitor 26 is coupled to the vertical deflection coil 27. The other terminal of the vertical deflection coil 27 is coupled to the voltage source indicated by + V1. The + V1 supply is generated through the coil 30 of the flyback transformer 24, the rectifier diode 31 and the filter capacitor 32. The + V1 supply can also be used to power other receiving circuits.

The horizontal output transistor 33 is converted to the horizontal deflection rate by a signal applied to its base from the horizontal oscillator and drive circuit 34. The collector of transistor 33 is coupled to the voltage source, indicated by + V2, via coil 35 of flyback transformer 24. Transistor 33 is also coupled to horizontal deflection coil 36, S-shaping capacitor 38, and resonant retrace capacitor 37. The diode 40 is coupled in series with the diode 31 between the coil 30 and the collector of the transistor 33. The switching operation of the transistor 33 generates a horizontal deflection current i ₂₇ at a horizontal frequency f _H that is twice the synchronization signal of the baseband video signal V _BB described later.

The operation of the vertical deflection circuit 100 causes horizontal rate charging and discharging of the storage capacitor 26, and the capacitor 26 supplies a vertical deflection current i ₂₃ flowing to the coil 27. Horizontal rate switching is performed by element 21. During each horizontal period, at the beginning of the vertical trace, the transistor 18 of the switching element 21 conducts for a very short interval that occurs just before the horizontal retrace. Thus, the current i ₂₇ flowing in the coil 23 flows in the opposite direction to the arrow in which the capacitor 26 is charged with a voltage that is more positive than the voltage + V1. The negative deflection current i ₂₇ flows in the coil ₂₇ in the opposite direction to the arrow due to the combined voltage at the terminal 126 that is more positive than the voltage + V1. During the vertical scan, the control circuit 20 sequentially increases the conduction spacing of the transistors 18 occurring at each horizontal trace. When transistor 18 conducts, capacitor 26 is discharged by an amount proportional to the conduction time of transistor 18. As the conduction time of transistor 18 increases sequentially, the voltage across capacitor 26 decreases sequentially during the vertical trace. The voltage across capacitor 26 decreases more charge by current i ₂₃ during conduction of transistor 18, which occurs during the horizontal trace than is added during the corresponding horizontal retrace. At the end of the vertical trace, the terminal 126 voltage is a positive voltage less than + V1 and the deflection current flows in the direction of the arrow. It changes the deflection current i ₂₇ in an upramping manner from the beginning of the vertical trace to the end and reverses the polarity at almost the center of the vertical trace. During the vertical retrace, transistor 18 does not conduct and is thus oscillated in half cycle by deflection coil 27 and capacitor 26.

The capacitor 26 is charged to a voltage greater than the voltage + V1 by the final vertical retrace voltage, whereby the deflection current i ₂₇ reverses its polarity.

According to a feature of the invention, the voltage V _D is applied to the non-inverting input terminal of the comparator 66 of FIG. The waveform of voltage V _D is shown by the same waveform V ₀ in FIG. 2B ignoring linearity, shaping, DC range, and DC level shift. A horizontal retreat pulse from coil 28 is applied through resistor 74 and charges capacitor 75 to obtain a horizontal ramp compared to the vertical sawtooth wave of voltage V _D. Comparator 66 is used as a pulse width modulator. The output of comparator 66 provides basic drive to transistor 18.

It can be seen that the current through the resistor 22 is equal to the deflection current i ₂₇ . Therefore, the voltage generated across the resistor 22 is proportional to the current i ₂₇ , the vertical deflection current. The voltage generated across the deflection current sampling resistor 22 is generated by the deflection current i ₂₇ and provides negative feedback to the vertical control circuit 20.

This feedback provides information to the vertical control circuit 20, which causes the transistor 18 to conduct vertical deflection current i ₂₇ by conducting for an appropriate period of time in each horizontal interval. During the vertical trace the current i ₂₇ is linearly proportional to the tooth ramp voltage V _D.

When the rising period of the pulse 2V 'or V _U4 occurs, for example, just before the second b or time t ₀ , downramping of the second voltage portion V _D is started. At the beginning of the downramping portion of voltage V _D , the deflection current i ₂₇ in the coil ₂₇ of FIG. 1 starts its corresponding downramping retrace. When the falling section of FIG. 2a pulse V _U4 occurs, the upramping trace of deflection current i ₂₇ of FIG. 1 starts.

Voltage V _D controls the instantaneous level of deflection current i ₂₇ during the vertical trace portion of deflection current i _27. As described above, in each vertical scan period, the voltage V _D is at the same level as when the falling section of the second pulse _P V4 occurs.

According to another feature of the invention, since the anticorrosive voltage V _D is generated, the ramping trace portion is in-phase in each deflection period of the two voltages V _D and the deflection current i ₂₇ of FIG. It is accompanied by a phase change of the falling section 900.

As will be described later, the phase modulation of pulse 2V 'is such that an image is generated such that the even field is placed on the even field, the radix field is placed on the radix field, and the right and odd field pairs are interlaced. Provide the exact timing required.

As a result of generating the waveform of FIG. 2b voltage V _D , it can be seen that the interval from the vertical trace end of the predetermined deflection period of the deflection current i ₂₇ to the beginning of the vertical trace of the next deflection period is constant.

The DC component of the vertical sawtooth wave with respect to the voltage V ₀ of FIG. 2b is well preserved and transmitted to the deflection coil 27 of FIG. DC coupling is well used in the vertical deflection coil 27 as well as between the sawtooth or ramp generating circuit 500 and the vertical deflection circuit 100. It is preferable that the phase modulation of the pulse 2V 'does not change the level of the deflection current i ₂₇ corresponding to the voltage V ₀ of the predetermined level by DC coupling.

The above-mentioned features of the deflection current i ₂₇ embodying the features of the invention are useful, for example, in a television receiver circuit of FIG. 3 which is similar to the circuit described in the patent application by the above-mentioned denhollander et al. Phase and magnitude are modulated according to the modulated vertical synchronization signal.

The receiver of FIG. 3 generating pulse 2V 'of FIG. 1 has an input terminal 212 for connection to an antenna or other source of a video input signal and provides the baseband video output signal V _BB ' described above to the video processing unit 214. A tuner 210 of FIG. 3 having an output that applies. For purposes of illustration it is assumed that the baseband video output signal is the PAL standard. However, the principles of the present invention are applicable to other standard interlaced scan video signal formats. Video processor 214 includes a PAL decoder that converts the input signal into Y, RY, and BY component forms.

If desired, the signal can be processed in the form of R, G, B components, but each of the R, G, B components has a full video bandwidth, with the color difference signals R-Y, B-Y having lower bandwidths. Therefore, field storage for the color difference signal can be realized with fewer memory elements than when the processing is performed using the R, G, and B components.

The Y, R-Y and B-Y component signals are low pass filtered by filters 216, 218 and 220 and converted to digital form by analog-to-digital (A / D) converters 222, 224 and 226 for storage in memory 240. Filters 216, 218, and 220 minimize aliasing and have a cutoff frequency of 7.5 MHz for Y in the PAL input signal and 2.8 MHz for the color difference signals R-Y and B-Y. Lower cutoff frequencies are appropriate for NTSC standard signals.

The A / D converters 222, 224 and 226 digitize the low band filtered components at 8-bit resolution using a sample clock CL that is phase locked to multiple horizontal syncs to obtain a constant number of samples per horizontal line. After A / D conversion, the digital component is applied to the memory 240 through each delay unit 228, 230, 232. The delay unit may be variable and included to equal the delay time of the three input signal paths. The color difference components R-Y and B-Y are applied to the memory 240 through a multiplex switch (MUX) 234 controlled by the horizontal line rate signal H. Multiplex switch 234 combines the two 8-bit color differences into a single 8-bit wide signal to minimize the memory requirements of memory 240.

When a multiplexed 8-bit color difference signal and one field of the 8-bit brightness signal are stored in the memory 240, the pre-stored field is read twice using the read clock signal 2CL twice the write clock CL frequency. . This doubles the field rate (100 ms for PAL and 120 ms for NTSC) and displays a signal on which the perception of flicker is reduced on the display unit 260.

Multiplex switch 242 demultiplexes the color difference signal with twice the field rate brightness signal and is converted back to analog form by digital-to-analog converters 244, 246, 248. The low pass filters 250, 252 and 254 suppress the repetitive spectrum after the D / A conversion and have a cutoff frequency of 6.75 MHz for chromaticity and 13.5 MHz for brightness. The double field rate analog signal is converted into RGB form to be applied to the display 260 synchronized by the double speed horizontal deflection current i _2H means provided by each horizontal scan generator 62 and vertical scan generator 64. Generator 62 generates deflection current i ₂₇ at twice the frequency f _H relative to the horizontal signal of baseband video output signal V _BB .

The field consists of 312.5 lines in the PAL standard. With a repetition of 312.5 lines at double speed, the field shall consist of 625 lines. This can be realized when one of the two fields consists of 312 lines and the other consists of 313 lines. The memory 240 of FIG. 3 is supplied as a timing signal from the timing unit 70 to provide the field sequence shown in FIG. 4A, where 312 lines are generated in the first read period (field A or B) and 313 lines. Is generated during the second memory read period (field A 'or B') with the 313th line blanked.

The double field-rate vertical sync pulse 2V 'required by the vertical scan generator 64 is shaped like a pulse shown in a straight line in FIG. 4B. For comparison, a pulse is indicated by a dotted line, which represents a double vertical sync pulse of equal distance with a duration of 312.5 lines. The linear pulse represents the pulse signal 2V 'of FIG. 2 periodically in four field units. As shown, there are 312 lines in field A, 312.5 lines in repeating field A ', 312 lines in field B and 313.5 lines in repeating field. The pulse 2V 'controls the switched oscillation deflection circuit 100 to generate a vertical scan waveform of the vertical deflection current i ₂₇ , as described above. The vertical trace part of the current i ₂₇ is shown schematically in FIG. 4C. The scanning current waveform sequence of FIG. 4C shows that the first field A, A 'is placed on the first field, the second field is placed on the second field B, B', and the first and second field pairs AA ', BB') becomes the interlaced pattern (interlace) shown in FIG. 4D. For comparison, the dashed line in FIG. 4d shows the scan line, which occurs if the sync pulse 2V 'in FIG. 4b is shifted or equidistant other than phase modulation. In order to ensure proper registration of the indicated field, the sawtooth voltage of FIG. 4C described above is applied by the ramp generation circuit 500 and always starts with a simultaneous value and starts all retrace times (TO-TO ', T1-). T1 ', T2-T2', etc. are the same.

Timing signals for controlling the digital converter, memory switch and scan generator are provided by the timing unit 70 of FIG. As described in the above-described Den Hollander patent application, unit 70 causes the interrate even and odd pair fields and the even field to lie above the even field when the double field rate signal is indicated, and the odd field to be odd. Two field and four field pulse sequences are generated for the generation of the scan of pulse 2V 'and over the memory control to lie on the field.

In the absence of the operation of the vertical oscillation circuit 501 and the ramp generation circuit 500 of FIG. 1 embodying the features of the present invention, double field-rate vertical sync pulses 2V 'spaced at irregular intervals correspond via the several field sequences. Phase change of the trace portion of the deflection current i ₂₇ associated with the pulse 2V '.

5 illustrates a ramp generation circuit 500 'embodying another feature of the present invention, and performs a similar function as the circuit 500 of FIG. 6C-6C show corresponding waveforms associated with the circuit 500 'of FIG.

Similar numbers and symbols indicate similar items and functions in FIGS. 1, 5 and 6c to 6c.

In circuit 500 'of FIG. 5, switch Q1' may be a thyristor as shown, or alternatively may be a transistor in series with a diode, inductor Lc 'and capacitor Lc' and capacitor Cc connected in series. The series configuration of is coupled while the vertical trace acts as a current source in the current path of transistor Q2 emitter current ic.

When the rising section of pulse 2V 'occurs, switch Q1' is inverted to initiate retrace. The switch Q1 'combines the conductor Lc and the capacitor in parallel. Thus generated in the half-period resonant oscillation claim 2b, the voltage V ₀ 'in Li inductor for generating trace portion Lc' and the capacitor C ₀ 'of. In the second half period of the oscillation, the switch Q1 'is cut off. The phase modulation or shift of the pulse 2V 'required to generate the correct raster position is only half of the shift needed in the case of FIG. This is because the fifth in-state voltage V ₀ ′ is reflected around the zero-axis during retrace. For reference, the sawtooth wave from the equidistant sync pulse is shown in dashed lines in FIG. 6B.

The retrace interval, such as during the interval ta-tb of FIG. 6b, is hardly affected by the voltage across capacitor C ₀ 'of FIG. 5 at the end of the vertical retrace, but rather on the resonant frequencies of inductor L ₀ ' and capacitor C ₀ '. Is determined by

According to another aspect of the invention, as in the case of FIG. 2b voltage V ₀ , the trace phase of FIG. 6b voltage V ₀ ′ for that of corresponding pulse 2V ′ in FIG. 6a is dependent on the phase modulation of pulse 2V ′. It is hardly affected by it.

Claims (21)

A television deflection device responsive to a synchronous input signal (2V ') at a frequency associated with a deflection frequency, said television deflection device comprising: means for generating a control signal (V _U4) in phase modulated with a frequency associated with a frequency of said input signal in response to said input signal; 501, a sawtooth wave generator 500 which is generated as a sawtooth waveform second signal V ₀ synchronized with the control signal V _U4 in response to the control signal V _U4 , and a deflection coil 27. And means for generating a deflection current i ₂₇ having a sawtooth waveform coupled to the deflection coil 27 in response to the control signal V _U4 , wherein the second signal V ₀ is a predetermined value. In a deflection period of, when the second signal V ₀ starts ramping in the first direction, the second signal V ₀ at the start time of the first ramping portion of the second signal V ₀ is Even if the predetermined level is not affected by the phase modulation of the control signal , A has a ramping second portion that varies in a first ramping portion that varies in a first direction to the first direction and the opposite direction, the deflection current (i ₂₇₎ are in phase in accordance with said control signal (V _U4) modulated periodic respective deflection in, when the phase of the control signal (V _U4) variable is maintained by the control signal (V _U4) and common for said second signal (V ₀₎ of the first ramping portion and the corresponding trace (trace) interval for the A television deflecting device having a trace portion. The television deflection apparatus according to claim 1, wherein said second signal (V ₀ ) is a vertical deflection frequency. The television deflection apparatus according to claim 1, wherein the trace interval is generated by the first ramping portion of the second signal (V ₀ ) and the retrace interval is generated by the second ramping portion. The television deflection apparatus according to claim 1, wherein said second signal (V ₀ ) has an amplitude which varies according to said phase modulation of said control signal (V _U4 ). 5. The method of claim 4, wherein said predetermined level of said second signal (V ₀ ) at said start time of said first ramping portion is proportional to said phase of said control signal (V _U4 ) of said deflection current (i ₂₇ ). And the same in each deflection period so as to prevent a change in amplitude of the second signal (V ₀ ) caused by phase modulation of the control signal (V _U4 ) according to the phase variation of the trace portion. The method of claim 1, wherein said second signal (V ₀₎ and the second ramped portion period, and varies according to the phase modulation of the control signal (V _U4), the second signal (V ₀₎ of the ramp third portion The interval equal to the sum of the second ramping portion and the third ramping portion, which divides between the first ramping portion of a predetermined deflection period and the first ramping portion of a next period, is equal to each other in the deflection period. TV deflection device, characterized in that it has a). 7. A television deflection apparatus according to claim 6, wherein the length of the interval is equal to the sum of the second and third ramping portions that are not affected by the phase modulation of the control signal (V _U4 ). 2. The second signal generator of claim 1, wherein the sawtooth wave generator 500 includes a capacitor Co and a current source Q2 coupled to the capacitor Co. The second signal ramps at the capacitor Co during the trace interval. Generates the first ramping portion of Vo, and responds to the control signal V _U4 to generate the second ramping portion of the second signal Vo in the capacitor Co and to the capacitor Co. A television deflection device having a coupled switch (Q1). 9. A television deflection apparatus according to claim 8, wherein said switch (Q1) clamps said second signal (Vo) at said predetermined level over an interval determined by said control signal (V _U4 ). 9. The television optical device according to claim 8, wherein the control signal (V _U4 ) causes the switch (Q1) to be conducted over intervals having the same length in each deflection period. The switch Q1 is conducted by the control signal generating means 501 until the capacitor Co is completely discharged to the predetermined level having the same value in each deflection period. TV deflection device made with. The current source (+) according to claim 1, wherein the means (100) for generating a deflection current (i ₂₇ ) comprises a capacitor (26) and an inductor and a current source (+) connected to the capacitor (26) to generate a ramping signal during the trace interval. V1), and a switch (21) for coupling said capacitor (26) to said inductor to form a resonant circuit with said inductor (25) during said retrace interval. 13. A television deflection apparatus according to claim 12, wherein the switch is a thyristor (Q1 '). 13. A television deflection apparatus according to claim 12, wherein said switch (Q1 ') couples said inductor (Lo') in parallel with said capacitor (Co ') during said retrace interval. 13. A television deflection apparatus according to claim 12, wherein the current source comprises a transistor having a collector electrode coupled to the capacitor such that the current flowing in the collector is hardly affected by the second signal (Vo). 2. The control signal V _U4 according to claim 1, wherein the control signal V _U4 is at the same frequency as the vertical rate, and the deflection current generating means 100 generates the deflection current i ₂₇ at the vertical rate and at a frequency related to the horizontal rate. And a switchable vertical deflection circuit responsive to the current i ₂₃ . The television deflection apparatus according to claim 1, wherein said second signal (Vo) is DC-coupled to said deflection coil (27). A television deflection device responsive to a synchronous input signal 2V 'at a frequency associated with a deflection frequency, the television deflection device comprising: generating a control signal V _{U4 at} a phase modulated with a frequency associated with the frequency of the input signal 2V'. Means 501 for responding to the synchronous input signal 2V ', and in a predetermined period the second signal Vo is a sawtooth waveform comprising a first ramping portion corresponding to the trace interval and a second ramping portion corresponding to the retrace interval. In response to the control signal V _U4 to generate the second signal Vo, an end time of the first ramping portion in a predetermined period of the second signal Vo and a start time of the first ramping portion in a next cycle A sawtooth wave generator 500, a deflection coil 47, and a deflection coil, each of which has a period in which each period has the same period and is not affected by the phase modulation of the control signal V _U4 . nose And a trace scan current in the deflection coil 72 when the first ramp is generated in response to the second signal Vo, and a retrace scan current when the second ramp is generated. A television deflection device comprising means (100). The method of claim 18, wherein the sawtooth wave generator 500 is a current source (Q2) coupled to the capacitor (Co) for charging the capacitor to generate a capacitor (Co), the first portion of the second signal (Vo), And a switch (Q1) coupled to said capacitor (Co) for discharging said capacitor to generate said second portion of said second signal (Vo). A television deflection device responsive to a synchronous input signal 2V 'at a frequency associated with a vertical deflection frequency, the television deflection device comprising: generating the control signal V _U4 in phase modulated with a frequency associated with the vertical deflection frequency; ) in the section 501 and the control signal (V _U4) sawtooth generator (500) responsive to the control signal (V _U4) so as to generate a second signal (Vo) of the synchronized sawtooth waveform by responding to the, the second signal (Vo) is the control signal when the phase of the control signal variable at the time that the phase of the control signal (V _U4) change is phase modulated according to the control signal (V _U4), each vertical deflection cycle The sawtooth wave generator having a vertical trace portion which maintains in phase with V _U4 , a vertical deflection coil 27, and the vertical deflection coil ₂₇ to supply a vertical deflection current i ₂₇ to the vertical deflection coil 27. Generates a voltage coupled to The energy storage means 25 and 26, the horizontal deflection rate energy source 23, and the second signal Vo, coupled to the energy storage means 25 and 26 to provide a predetermined horizontal deflection interval. Apply a predetermined amount of the horizontal deflection rate energy from the horizontal deflection rate energy source 23 to the energy storage means 25, 26 during one portion and the predetermined amount of energy in the energy storage means during the second portion of the predetermined horizontal interval. Means for removing an amount of energy, the first portion being variable in proportion to the second portion in accordance with the second signal Vo generated by the energy storage means 25, 26; A television deflection device, characterized in that the second voltage is varied to generate the vertical deflection current i ₂₇ with a sawtooth waveform maintained during each trace interval in phase with the control signal V _U4 . . 2. The method of claim 1, wherein in each deflection period, when the second signal Vo starts to ramp in the first direction, the second signal is at the start time of the first portion of the second signal Vo. A television deflection device, characterized in that it is at a predetermined level unaffected by the modulation of the control signal (V _U4 ).

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