JPS62254573A - Television deflector - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a television deflection system, and particularly to a method for increasing the field frequency of a displayed image to reduce the visibility of flicker. Regarding the method.

[Background of the invention]

Field-free method in television display method (
For example, it is conspicuous even in NTSC 60Hz system, especially in low field frequency systems (for example, P
In the AL50Hz method), the frequency has been increased to such an extent that it is felt to be unpleasant. One solution to this problem is to double the field frequency of the displayed image. In the conventional approach, the video input signal is stored in field memory. Each stored field is recovered or read from memory twice and displayed on a display scanned at twice the line frequency and twice the field frequency of the incoming video signal. This doubles the flicker frequency of the displayed image and reduces the visibility of flickering.

The name of the invention is [Television Display System Equipped with Flicker Reduction Processing Device]
System with Flicker Red
uction Processor) J,
The inventor is W, den Hollander.
No. 857.375 (corresponding to Republic of China Patent Application No. 75-101655), et al., discloses a television display device that reduces flicker. In this device.

An interlaced baseband television input signal having a predetermined field frequency is provided.

The method has a write cycle for storing one field of an input signal, and first and second read cycles for reading and comparing the previously stored one field twice during one write cycle, and A memory is used that produces a video output signal having a field frequency twice the predetermined field frequency. This output signal provides image information for display on a display device. A timing unit responsive to the video input signal provides a readout control signal having a pulse waveform repeating on a two-field basis to the memory and a vertical synchronization signal having a pulse waveform repeating on a four-field basis to the display device. The pulse of this vertical synchronization pulse waveform is based on one field, and a display image in which a phase even a field and an odd field are interlaced at a normal frequency that is twice the predetermined field frequency is displayed on the display device. selected so that Each pulse of the vertical sync signal initiates a corresponding vertical retrace scan period. The pulses of the vertical synchronization pulse waveform cause a corresponding phase modulation in the vertical deflection current.

Furthermore, these pulses cause the duration of the corresponding vertical scan cycle to vary on a one field basis and repeat on a four field basis.

A typical vertical deflection circuit includes a sawtooth generator that generates a drive signal having a sawtooth waveform that is synchronized to a synchronization signal. During the retrace period, the capacitor is discharged by the switch and during the trace period, the capacitor is charged by the current source. The drive signal is coupled to a switching circuit that generates a deflection current having a corresponding sawtooth waveform. The drive signal includes a ramp portion that corresponds to a vertical trace such that its starting point corresponds to a deflection current scanning the top of the raster of the display.

For example, in the apparatus of the above-mentioned U.S. patent application Ser. Therefore, it may change based on one field.

If the peak amplitude of this drive signal changes, the start point of the ramp section will change relative to the corresponding pulse of the vertical synchronization signal that causes this ramp section. This is because the discharging time of the capacitor of the sawtooth generator changes according to the peak amplitude of the different drive signals as the field changes.

As a result, the phase of the deflection current trace will be different from the phase set by the phase modulated vertical synchronization signal. Therefore, it is no longer possible to completely satisfy the requirement that even fields should overlap with even fields, odd fields should overlap with odd fields, and pairs of odd and even fields should be interlaced. Put it away.

[Summary of the invention]

Therefore, it is desirable to prevent, for example, the start of the ramp portion of the drive signal from being substantially affected by changes in the amplitude of the drive signal, such as changes in peak amplitude, in each deflection cycle.

According to one aspect of the invention, a television deflection device responsive to a synchronization input signal at a frequency related to a deflection frequency comprises:
A control signal is generated having a frequency related to the frequency of the synchronization input signal and a modulated phase. A sawtooth generator responsive to the control signal generates a sawtooth-shaped second signal synchronized by the control signal. The second signal has, in a given deflection cycle, a first portion that ramps in a first direction (changes at a constant rate) and a second portion that ramps in the opposite direction. and in each deflection cycle, when the second signal begins ramping in the first direction at the beginning of its first portion, the second signal has a predetermined value that is not affected by the modulation of the phase of the control signal. . a deflection current having a sawtooth waveform according to the second signal;
Supplied to the deflection winding. The deflection current has a trace portion corresponding to the first portion of the second signal during the trace period. This deflection current trace portion is phase modulated according to the control signal. This trace portion remains in phase with the control signal during each deflection cycle, even though the phase of the control signal changes.

[Detailed explanation]

In FIG. 1b, in accordance with one aspect of the invention, vertical oscillator circuit 501 of vertical scan generator 64 is provided with a double frequency synchronization pulse 2 V'. This synchronizing pulse 2V' is supplied to the input terminal 702 of the inverting amplifier U1. This inverting amplifier U1 is biased by a voltage formed between resistors 704 and 706. The pulse 2 V/ is phase modulated and is generated in a manner described below. The normal frequency of pulse 2V' is 2fv. However, fvci is the frequency of a vertical synchronization signal in a baseband television signal such as the NTSC or PAL standard system. The pulses 2 V/ are separated by corresponding periods of different duration. The normal length of this duration is -2v, where ■ represents, for example, a 20 millisecond vertical scanning period in the PAL system.

When the leading edge of pulse 2 V' rises, the pulse Ula generated at the output terminal of the amplifier Ul transitions from high to low level. Pulse Ula is provided by resistor 708, along with pulse Ulb, to the corresponding non-inverting input terminals of amplifiers U2 and U3 and to the inverting input terminal of amplifier U4. As a result, amplifier U4 forms a pulse vU4 at its output terminal. For example, the pulse vU4 is as shown in Fig. 2a.
period t. It has a waveform with the same polarity and width as the synchronizing pulse 2 V/ as shown between -t2.

Amplifiers U2 and U3 are coupled in feedback mode;
It forms a vertical excavator. resistor 72 of FIG. 1b coupled between the output terminal and the non-inverting input terminal of amplifier U3;
Since a positive feedback path is formed by 0, for example during the period to -t2 of FIG. 2a, pulse Ulb is kept low, keeping pulse vU4 high. At the same time, capacitor 712 is rapidly discharged by amplifier U2 of FIG. 1b. When the voltage at the inverting input terminal of amplifier U3, which corresponds to the voltage across this capacitor 712, is also lower than the corresponding level of pulse Ulb.

Amplifier U3 stops conducting and output voltage U3a goes to a high level. However, pulse Ulb remains at a low level until the trailing edge 901 of pulse 2 V/pulse 2 V
If / is gone, pulse vU4 is extracted from pulse U3a, which is obtained from the output of amplifier U3 and is fed through resistor 720 to amplifier U4.

Pulse vU4 is supplied to control a lamp generation circuit 500 embodying an aspect of the invention, which generates lamp voltage vo as shown in FIG. This lamp generation circuit 5
00 comprises a current source transistor supplying current to a current integrating capacitor CO biased by resistors RO1R1, R2 and R3 and connected in parallel to the conductive path of transistor switch Q1. This ramp generation circuit 500 generates an output ramp voltage Vo as shown by the solid line in FIG. Capacitor Co in FIG. 1b begins to discharge when the leading edge 900 of pulse 2V'occurs;
At a time before the trailing edge of each pulse VU4, for example before time t2 shown in FIG. 2, transistor Q1 is discharged to the saturation voltage level. Pulse vU4 of FIG. 1b causes transistor Q1 to clamp voltage Vo to the saturation voltage level of transistor Q1, thereby causing voltage Vo
is prevented from ramping up before the trailing edge of pulse VU4.

The phase modulated pulses vU4 of FIG. 2a are separated by periods of mutually corresponding but different lengths, whose phase modulation causes the time t of FIG. ,t3,t
6, the lamp voltage V at a time such as t9.

correspond to each other but exhibit different peak values.

Voltage V. The first part that ramps up is e.g.
This occurs during a period such as the period t2-t3 in the figure. This first
The section begins its upward ramp from a predetermined constant level, which is the saturation voltage of transistor Q1 of FIG. 1b, in a manner that is unaffected by the phase modulation of the synchronization pulse 2 V'. Thus, the first part that ramps up starts ramping up at a time such as, for example, time t2 in FIG. A second downward ramping portion of voltage Vo occurs, for example, during period 10-t□. A third flat portion occurs during period t□-L2.

According to one aspect of the invention, the sum of the periods corresponding to the second and third portions is the voltage V of FIG. 1b.

The predetermined period, which is unaffected by the peak value of V, is kept constant, for example, so as not to be influenced by the phase modulation of pulse 2 V' in FIG. 1b.

The width of the synchronizing pulse 2V' generated by the timing unit 70 in FIG.
’ can be adjusted.

Lamp voltage V. is DC biased by resistors 802, 804 and 806 and buffered by amplifier U5. The output of this amplifier U5 is 80 as a whole.
The signal is supplied to a linearity correction circuit 808 shown at 8. This circuit 808 produces a smoothed linearity correction signal that is connected to the signal produced at the output of amplifier U5 by resistor 81.
0.812 is added to the lamp voltage V. A lamp voltage VD is formed which has the same characteristics as described above in connection with , and whose linearity has been corrected.

As shown in FIG. 1a, the present invention utilizes a vertical scan generator 6
It also includes a switched vertical deflection circuit 100 that is controlled by vertical control circuit 20 of No. 4. This deflection circuit 100 and control circuit 20
The operation of is disclosed in detail in US Pat. No. 4,544,864. Control circuit 20 provides a width modulated horizontal or line frequency switching signal to switching element 21, illustrated as including, for example, integrated transistor 18 and anti-parallel diode 19, in accordance with voltage VD. transistor 18
may include power field effect transistors, in which case it is advantageous when the horizontal frequency is higher than that in, for example, PAL systems.

Such high frequencies are used, for example, in computer monitors or video display terminals. Switching element 21 is coupled to terminal 126 of storage capacitor 26 via winding 23 of flyback transformer 24 connected in series with storage coil 25 . Terminal 1 of capacitor 26
26 is coupled to one end of a vertical deflection winding 27. The other end of this vertical deflection winding 27 is coupled to a power supply designated +v1. This +V1 power supply is connected to winding 30. of flyback transformer 24. It is composed of a rectifier diode 31 and a filtering capacitor 32. This +v1 power supply is
It is also used to power other receiver circuits.

Horizontal output transistor 33 is switched at the horizontal deflection frequency by a signal supplied to its base from horizontal oscillation and drive circuit 34. This transistor 33
The collector of is coupled via winding 35 of flyback transformer 24 to a power supply designated +v2. This transistor 33 is also coupled to a horizontal deflection winding 36, a figure-eight correction capacitor 38, and a resonant IJ) race capacitor 37. A diode 4o between the winding 3o and the collector of the transistor 33 is connected in series with the diode 31. Due to the switching operation of the transistor 33, a horizontal deflection current 12H having a frequency twice the horizontal frequency fH of a synchronization signal of a baseband video signal vBB, which will be described later, is generated.
occurs.

Vertical deflection circuit 100 operates to charge and discharge storage capacitor 26, which provides vertical deflection current 12□ flowing through winding 27, at a horizontal frequency. Switching at the horizontal frequency is performed by the switching element 21.

At the beginning of the vertical trace, during each horizontal period, the transistor 18 of the switching element 21 is conductive for a very short period that occurs just before its horizontal retrace.

As a result, the current 123 in the first winding 23 flows in the direction opposite to the illustrated arrow, and the capacitor 26 is charged to a voltage more positive than the voltage +v1. The resulting voltage at terminal 126, which is also more positive than V1, causes a deflection current 12□ to flow through winding 27 in the direction opposite to the arrow. During vertical scanning, control circuit 20 gradually increases the conduction period of tractor resistor 18 that occurs in each horizontal trace. When the transistor conducts, capacitor 26 is discharged by an amount proportional to the period of conduction of transistor 18. Transistor 1
By increasing the conduction period by 8, the voltage across capacitor 26 decreases by 1 during the vertical trace. The voltage across capacitor 26 tapers off because the charge picked up by DC 123 during the conduction of transistor 18 that occurs during the corresponding horizontal trace period is less than the charge added to capacitor 26 during each horizontal retrace period. This is because there are many.

At the end of the vertical trace, the voltage at terminal 126 is the voltage +v
With a positive value smaller than 1, the deflection current 127 flows in the direction of the arrow. As a result, from the beginning to the end of the vertical trace, the deflection current 12□ ramps upward and reverses polarity approximately at the center of the vertical trace.

During vertical retrace, transistor 18 is non-conducting. As a result, the deflection winding 'a27 and the capacitor 26 receive a half cycle of one oscillation. The resulting vertical retrace voltage charges capacitor 26 to a voltage much higher than voltage V1, causing deflection current 127 to reverse its polarity.

According to one aspect of the invention, the voltage V. is applied to the non-inverting input terminal of comparator 66 of FIG. 1a. The waveform of voltage vo, ignoring linearity, shaving, DC scale and DC level shift, is V in Figure 2b. can be expressed in the same way as the waveform of A horizontal IJ) race pulse supplied from winding 28 through resistor 74 charges capacitor 75, resulting in a horizontal ramp that is compared to vertical deflection current VD. Comparator 66 functions as a pulse width modulator. The output of comparator 66 base drives transistor 18.

It is clear that the current flowing through resistor 22 is equal to the deflection current 12□. Therefore, the voltage developed across resistor 22 is proportional to the current 12□, ie, the vertical deflection current. The voltage generated across this deflection current sampling resistor 22 is caused by the deflection current '27 and provides negative feedback to the vertical control circuit 2°. This feedback is sent to the vertical control circuit 2o. A. Kyu-IV Army (Company) Yami Komoto Attack and Admission provides information for driving the second resistor 18 into a conductive state and generating the vertical deflection current 127. Therefore, the current 12□ during the vertical trace is linearly proportional to the sawtooth ramp voltage 5.

For example, time t in FIG. The occurrence of pulse 2V', the leading edge of vU4, at a time such as just before , initiates the second part of the falling voltage D. This voltage VD
The beginning of the down-ramp portion of FIG. 1b causes the deflection current 12□ in winding 27 of FIG. 1b to begin its corresponding down-ramp trace portion. When the trailing edge of pulse vU4 of FIG. 2a occurs, the upward ramping trace portion of deflection current 127 of FIG. 1b begins.

Voltage V falls on the vertical trace of deflection current 127 and controls the instantaneous level of deflection current 12□. As previously mentioned, during each vertical scan cycle, voltage VD is at the same level when the trailing edge of pulse vU4 of FIG. 2a occurs.

In accordance with another aspect of the invention, because of the manner in which voltage VD is generated, the ramping trace portion in each deflection cycle of both voltage v0 and deflection current 1/lFF in FIG. It is in phase with the corresponding leading edge 900 and follows its phase change.

As explained later, even fields overlap with even fields, odd fields overlap with odd fields,
The precise timing required to obtain a displayed image with proper image overlay such that even and odd field pairs are interlaced.
A phase modulation of pulse 2 V' provides.

As a result of adopting the method of generating the voltage V waveforms as shown in Figure 2, the deflection current 12 of Figure 1a starts from the end of the vertical trace of a given deflection cycle to the vertical trace of the next deflection cycle. It should be understood that the period up to the starting point is also constant.

Voltage V in Figure 2. It is desirable to leave the DC component of the vertical sawtooth waveform and transmit it to the deflection winding 27 in FIG. 1b.

Therefore, the vertical deflection circuit 100 is of course connected between the sawtooth wave generating circuit, that is, the ramp generating circuit 500, and the vertical deflection winding 27.
It is also desirable to use DC coupling between the two. This DC coupling results in a phase modulation of the pulse 2 V/voltage V. This is desirable because it does not change the level of the deflection current 127 corresponding to the predetermined level of .

Deflection current 12. as described above with various aspects of the invention. The features are, for example, similar to the circuit disclosed in the aforementioned U.S. Pat. This is useful in the television receiver circuit shown in FIG.

The receiver shown in FIG. 3 for generating pulses 2 V' of FIG. 1 includes a tuner 210 having an input terminal 212 for connection to an antenna or other video input signal source, and It has an output terminal for supplying the baseband video output signal vBB to the video processing unit 214.

- As an example, assume that the baseband video output signal is of PAL format. However, it should be recognized that the principles of the invention apply to other types of interlaced video signal formats.

Video processing unit 214 includes a PAL decoder that converts the input signal into Y%RY and BY components. This signal can also be processed in the form of RlG and B components, if necessary. In that case, the color difference signal (R-Y
%B-Y) has a narrow bandwidth, whereas the R, G%B components each have the full video bandwidth. Therefore, field storage for color difference signals can be realized with fewer memory elements than when processing using R, G%B components.

The Y%R-Y and B-Y component signals are filtered to filter 216.
218 and 220;
Analog U80 Tal (A/D) to store at 0
It is converted to digital form by converters 222, 224 and 226. Filters 216, 218 and 22
0 minimizes aliasing, and for the PAL input signal in the example shown, 7,5 for Y.
MHz, 2,8 for color difference signals XR-Y and B-Y
It has a cutoff frequency of MHz. In the case of an NTSC signal, it is appropriate to lower the cut-off frequency even lower than the above.

The A/D converters 222, 224 and 226 convert the low-pass filtered component into 8-pits using a sample clock CL phase-locked to a multiple of the horizontal sync signal to obtain a constant number of samples per %1 horizontal line. Digitize to resolution. After A/D conversion, each digitized component is provided to memory 240 via delay units 228, 230 and 232, respectively. These delay units may be variable delay units, and are intended to equalize the delay times of the three input signal paths. The color difference signal components R-Y and B-Y are connected to a multiplex switch (MUX) 2 controlled by a horizontal line frequency signal H.
34 to memory 240. switch 23
4 combines two 8-bit wide color difference signals to create one 8-bit wide color difference signal.
By using a pit width color difference signal, the storage capacity required for the memory 240 is reduced.

When the multiplexed 8-pit color difference signal and 8-pit luminance signal for one field are stored in the memo 240, the first field stored has a frequency twice the write clock CL. It is read twice using the read clock signal 2CL that it has. This doubles the field frequency (100 Hz%N for PAL)
In the case of TSC, the frequency is set to 120 Hz), so that the flicker when the signal is displayed on the display unit (260) is less noticeable.

A multiplexer 242 demultiplexes the color difference signal and the double frequency luminance signal, and digital-to-analog (D/A) converters 244, 246 and 248 convert these signals back to analog form. Low pass filters 250, 252 and 254 suppress repeat spectra after D/A conversion.

Its cutoff frequency is 13.5ME (
z.

6.75 MHz is suitable for chrominance signals. Thereafter, to supply the display device 260, which is synchronized by double-rate horizontal deflection current 12H and vertical deflection current '27 provided by horizontal scan generator 62 and vertical scan generator 64, respectively. The double field frequency analog signal is converted to RGB format. Horizontal scan generator 62 generates a baseband video output signal vB
A deflection current 12H having a frequency twice the frequency f of the horizontal synchronizing signal B is generated.

In the PAL system, one field consists of 312.5 scanning lines. For double speed, this field and its repeated readout fields must consist of 625 scan lines. This is achieved when one of the two fields consists of 312 scan lines and the other consists of 313 scan lines. Memory 2 in Figure 3
40, a timing unit 7o receives a timing signal which provides a field sequence as shown in FIG. 4A.
Supplied from. In this sequence, 3/2 scan lines are generated in the first read cycle (field A or B), and 3/3 scan lines are generated in the second read cycle (field A' or B'). 3/3 scan lines are generated as blanks.

The double field frequency vertical synchronization pulse 2V' required by the vertical scan generator 64 has the pulse pattern shown in solid lines in FIG. 4B. For comparison, the case of equally spaced double frequency vertical synchronizing pulses having a period of 312.5 scanning lines is shown by dotted lines in the figure. The solid line pulses represent the pulse signal 2V' of FIGS. 2 and 3 repeated on a four-field basis. As shown, field A has 312 scan lines, repeated field A' has 312.5 scan lines, and field B has 312 scan lines. There are 313.5 scan lines in repeated field B'. Pulse 2 V' is connected to switching type vertical deflection circuit 1 as described above.
00 to generate a vertical scanning waveform with a vertical deflection current of 12□. The vertical trace portion of the vertical deflection current '27 is shown schematically in Figure 4C. The successive scanning current waveforms of FIG. 4c cause the first field (A, A/) to overlap the first field, and the second field (B, B
An interlaced pattern 7 as shown in FIG. 4D is produced in which the first and second field pairs (A A', BB') are interlaced, with the second field overlapping the second field. For comparison, the synchronization pulse 2 V' in FIG. 4B is not shifted or phase modulated and therefore
Evenly spaced Noharusu dangerous salt 1b t7 Sho 1- Z Chitasu ^
It is shown by the dotted line on the Totai-Bamboo 4D map. To ensure that the displayed fields overlap correctly, the sawtooth voltages of FIG. T□-T□', T2-T2', etc.) are equal.

Timing signals to control the digital converters, memory, switches and scan generator are provided by timing unit 70 in FIG.

This timing unit 70, as described in the specification of the aforementioned U.S. Patent Application No. 857,375,
When a double field frequency signal is displayed, even fields overlap with even fields and odd fields overlap with odd fields to ensure that even and odd field pairs are interlaced. A pulse sequence based on 2 fields and 4 fields is generated for memory control and for scanning generation of pulses 2V'.

If there is no operation of the lamp hammer main circuit 500 and the vertical excavation circuit 501 of the Chiku IM that implements one feature of this invention, the vertical synchronization pulse 2 with twice the field frequency of the irregular interval will be generated.
V/ causes a variation in the phase of the deflection current 12□ trace for the corresponding pulse 2V' over four consecutive fields.

FIG. 5 shows a ramp generation circuit 500' embodying another aspect of the invention. This performs a similar function to circuit 500 of FIG. The circuit 500 of FIG. 5 is shown in FIGS. 6a to 6c.
′ and the corresponding waveforms are shown. Figure 1.

Like numbers and symbols in FIGS. 5 and 6 indicate similar elements and functions.

In the circuit 500′ of FIG. 5, the switch Q□′C is a thyristor, but may also be a transistor connected in series with a diode) is a resonant circuit including an inductor Lo′ and a capacitor Co′ connected in series. connected between both ends. During the vertical trace period, the inductor L
The series circuit of o' and capacitor Co' generates an emitter current i of transistor Q2' which operates as a current source. is coupled to the current path of

When the leading edge 900 of pulse 2 V/ occurs, switch Q becomes conductive and begins retrace.

When switch Q1' is conductive, it is in a parallel relationship with inductor Lo' and capacitor Co'. As a result, a half cycle of resonant oscillation occurs in the inductor Lo' and the capacitor Co', and the voltage V in FIG. ′ is generated. During the remaining half cycle of this oscillation, switch Q
1' is blocked. The displacement of the pulse 2V', ie the phase modulation, required to correctly position the raster is only half the displacement required in the case of FIG. This is the voltage ■ in Figure 5. ' is in a mirror image relationship on both sides of the zero axis during the retrace period. For reference, the sawtooth wave resulting from equally spaced synchronization pulses is shown in dotted lines in FIG.

For example, trace periods such as periods t and tb in FIG.
is not substantially influenced by the voltage across ', but rather is determined by the resonant frequency of inductor Lo' and capacitor Co'.

According to another aspect of the invention, as in FIG.
The voltage V in the figure. The phase of the trace part of ′ is pulse 2
Virtually unaffected by phase modulation of V'.

[Brief explanation of drawings]

FIG. 1a is a circuit diagram of a part of a vertical scanning generator including a sawtooth generator which is one embodiment of the present invention, FIG. 1b is a circuit diagram of the remaining part of the vertical scanning generator, and FIG. Figure 1a and 1
Waveform diagram for explaining the operation of the circuit shown in Fig. 3.
The figure is a block diagram of a television receiver including the vertical scanning generator shown in Figures 1a and 1b, Figure 4 is a waveform diagram showing the operation of the receiver of Figure 3, and Figure 5 is a block diagram of a television receiver including the vertical scanning generator shown in Figures 1a and 1b. Another embodiment of the circuit, FIG. 6, is a circuit diagram for explaining the operation of the circuit of FIG. 5. 27... Deflection winding, 100... Deflection current generating means,
500... sawtooth wave generator, 501... control signal generator.

Claims (1)

[Claims] (1) means for generating a control signal having a frequency and a modulated phase related to the frequency of the input signal in response to a synchronization input signal of a frequency related to the deflection frequency;
A sawtooth generator for generating, in response to the control signal, a second signal having a sawtooth waveform synchronized with the control signal,
the second signal has a ramping first portion that varies in a first direction and a ramping second portion that varies in a direction substantially opposite to the first direction in a predetermined deflection cycle; In each deflection cycle, when the second signal begins ramping in the first direction at the beginning of the first portion, the second signal reaches a predetermined level that is not affected by the modulation of the phase of the control signal. a deflection current having a sawtooth waveform applied to the deflection winding in response to the second signal; , the first signal of the second signal
means for generating said deflection current having a trace portion corresponding to a portion of said control signal that is phase modulated in accordance with said control signal and that remains in phase with said control signal as the phase of said control signal changes in each deflection cycle. A television deflection device comprising: