JPH0476271B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a television composite video signal waveform processing device used, for example, when reading a composite video signal from a disk memory in an electronic still camera and displaying it on a television.

[Prior Art] The standard television format is 1/2 interlaced scanning. For example, in the NTSC system, 1
The horizontal scanning line of the field is 262.5H (1H is one horizontal synchronization period), and 1 frame = 2 fields, which is 525H. Therefore, when playing back a rotating disk of an electronic still camera where 1 field = 262.5H is recorded in 1 rotation, horizontal synchronization is not possible at the recording joint (starting point or ending point).
This results in a shift of 0.5H, that is, 1/2 of the horizontal synchronization period, which causes screen distortion on a normal television receiver, making normal display impossible. For this reason, it is necessary to generate a continuous horizontally synchronized reproduction signal from the recording seam by passing the reproduction signal from the disk through a 0.5H delay circuit every other field repetition period. In other words, a in Fig. 2 shows the reproduction signal from the disk, which is reproduced once every field repetition period.
b in Figure 2 by delaying 0.5H every third time.
It is necessary to create a playback signal as shown in the figure below. In addition,
In the figure, V _S is a vertical synchronization signal, and H _S is a horizontal synchronization signal, and in this case, both signals are delayed every other signal.

For example, FIG. 3 is a circuit block diagram showing a conventional example. In this circuit, a reproduction signal read from a disk by a head 1 is supplied to a demodulation circuit 4 via an amplifier 2 and a high-pass filter 3.
The playback signal output from the PNP is supplied to the 0.5H delay circuit 5 and connected to the PNP
It is supplied to the base of a type transistor Tr31.
The reproduced signal delayed by 0.5H by the delay circuit 5 is passed through a level correction circuit 8 consisting of a balanced modulation circuit 6 and an adder 7, and further via a capacitor C32.
It is supplied to the base of the PNP transistor Tr32. The sync chip level of the reproduced signal output to the emitters of both the transistors Tr31 and Tr32 is controlled by the diodes D31 and D32 and the capacitor C3.
The signal is detected by sync chip level detection circuits 9 and 10 consisting of resistors R31 and R32, and is supplied to a differential amplifier 11. The differential amplifier 11 detects the difference between the sync chip level of the undelayed reproduced signal and the sync chip level of the delayed reproduced signal, and supplies the difference to the balanced modulation circuit 6 as an error voltage. The balanced modulation circuit 6 outputs a signal with a gain corresponding to the level of the error voltage, and the adder 7 outputs a delayed reproduction signal whose level has been corrected in accordance with the level of the undelayed reproduction signal. . and each of the transistors Tr
31, the undelayed reproduction signal and the delayed reproduction signal are alternately taken out from the emitter of the Tr 32 via the analog switch 12 which alternately switches its contact point every field repetition period, and the output amplifier 13
is supplied to. In addition, the analog switch 1
A synchronous separation circuit 14 is provided between the output amplifier 13 and the synchronous separation circuit 14, and the synchronous separation circuit 14 outputs a pulse that is generated only during the pedestal period of the reproduced signal.The pulse turns on the switch 15 during the pedestal period, causing the capacitor C35 to The pedestal level of the reproduced signal is maintained. The pedestal level held in this capacitor C35 is supplied to a pedestal clamp circuit 16, and the output of the pedestal clamp circuit 16 is connected to each of the transistors Tr31 and Tr through resistors R33 and R34, respectively.
32 bases, respectively, so that the pedestal level of the undelayed reproduction signal and the pedestal level of the delayed reproduction signal are made to match.

By the way, the synchronization separation circuit used in such a device is equipped with an integrating circuit to integrate the input synchronization pulse in order to match the phase of the synchronization pulse with the color signal and to stabilize it against noise. It slices at the slice level to obtain a new synchronization pulse and outputs it.

[Problems to be Solved by the Invention] Since the 0.5H delay circuit used in such a device is constituted by a charge-coupled device, there is a problem in that the amplitude characteristics and frequency characteristics are likely to be distorted. When such distortion exists, there is a problem in that the above-mentioned synchronization separation circuit cannot match the phase of the non-delayed synchronization pulse with the phase of the delayed synchronization pulse.

For example, a charge-coupled device has nonlinear distortion,
Therefore, if the amplitude of the synchronization pulse of the reproduced signal delayed by 0.5H becomes small, the synchronization separation circuit 1
The phase of the horizontal sync pulse separated by operation 4 is
A problem arises in which the reproduced signal delayed by 0.5H and the reproduced signal not delayed are out of sync. To explain this problem with FIG. 4, let S ₁ be the amplitude of the horizontal synchronizing pulse a of the undelayed reproduced signal, and S ₂ be the amplitude of the horizontal synchronizing pulse b of the reproduced signal delayed by 0.5H.
The waveforms obtained by integrating each of these horizontal synchronizing pulses in the synchronization separation circuit are waveform a' indicated by a dotted line in the figure and waveform b' indicated by a dashed line in the figure. When this is sliced at level X-X' by the comparator of the synchronization separation circuit, the synchronization phase of the horizontal synchronization pulse that is not delayed becomes point _P1 , but the synchronization phase of the horizontal synchronization pulse that is delayed becomes point _P2 . Become. By performing such synchronization pulse processing, the synchronization phase P ₂ of the delayed horizontal synchronization pulse is delayed from the synchronization phase P ₁ of the non-delayed horizontal synchronization pulse. This results in the horizontal synchronizing pulse being delayed with respect to the video signal. If horizontal scanning is performed using this delayed horizontal synchronizing pulse, the image will shift to the left. Since such a phenomenon occurs at each field repetition period, the image appears as a phenomenon in which the image oscillates from side to side. This phenomenon also occurs when the frequency characteristics of the 0.5H delay circuit are poor.

This invention has been made in view of the above circumstances, and it is possible to make the synchronization phase of the horizontal synchronization pulse the same in the undelayed case and in the delayed case, and eliminates the possibility that the image may be shaken from side to side. It is an object of the present invention to provide a television composite video signal waveform processing device that is free from noise.

[Means for Solving the Problems] The present invention provides a method for extracting a composite video signal for displaying one frame of image using a 1/2 interlaced scanning method from a video signal storage medium that stores one field of repeated playback signals. A demodulation circuit that outputs a reproduced signal, a 0.5H delay circuit consisting of a charge-coupled device, etc. that delays the reproduced signal from this demodulation circuit by 1/2 the horizontal synchronization period, and a reproduction signal output from this delay circuit. circuit switching means for passing the signal and the reproduced signal outputted from the demodulation circuit as they are, alternately at each field repetition period; An integrator circuit is provided that alternately inputs the signals and switches the integral constant for each field repetition period so that the synchronization phases match when the horizontal synchronization pulses of both reproduction signals are sliced. a synchronous separation circuit that separates the signal and outputs a pulse signal corresponding to the pedestal period of the reproduced signal; and a pedestal of the reproduced signal that receives the pulse signal corresponding to the pedestal period from the synchronous separation circuit and passes through the circuit switching means. A pedestal level control means that detects and holds the level and controls the pedestal levels of the reproduced signal output from the delay circuit and the intact reproduced signal output from the demodulation circuit to match each other, and a synchronization pulse from the synchronization separation circuit. sync chip level setting means for setting the sync chip level of the reproduction signal outputted from the delay circuit passing through the circuit switching means and the reproduction signal outputted as is from the demodulation circuit to a preset fixed potential in response to the circuit switching means. It was established.

[Operation] By having the above-mentioned configuration, this invention has the following features:
The synchronization separation circuit passes the delayed horizontal synchronization pulse and the undelayed horizontal synchronization pulse through an integration circuit with different integration constants, thereby determining the synchronization phase of both horizontal synchronization pulses when the horizontal synchronization pulse is sliced at a certain level. The horizontal synchronizing pulses whose phases match are separated and output. Pedestal level control and sync chip setting control can be performed using the phase-matched horizontal synchronizing pulses.

[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

In Fig. 1, 21 is a head, and this head 2
1 reads out a playback signal from a disk, which is a video signal storage medium, which stores a composite video signal for displaying one frame of image using a 1/2 interlace scanning method as a repeat playback signal of one field. The reproduced signal read by this head 21 is supplied to a demodulation circuit 24 via an amplifier 22 and a high-pass filter 23. The demodulation circuit 2
4 has the function of outputting a reproduction signal and a synchronization signal, and supplies the reproduction signal to a 0.5H delay circuit 25 composed of a charge-coupled device (CCD) and connects it to the base of a PNP transistor _Tr1 via a capacitor C1. is supplied to.

The delay circuit 25 delays the input reproduction signal by 1/2 time of the horizontal synchronization period, and supplies this delayed reproduction signal to the input terminal of the balanced modulation circuit 26 and the adder 27 constituting the peak level correction means. are doing. The balanced modulation circuit 26 inputs a reference voltage obtained by a voltage dividing circuit of resistors R ₁ and R ₂ to its input terminal B, and also inputs an error voltage from a peak level difference detection means to be described later to its input terminal C. The input reproduced signal is processed with a gain according to the magnitude of the error voltage, a positive or negative polarity signal is output from the output terminal O, and the signal is sent to the adder 2.
7. The adder 27 superimposes the signal from the balanced modulation circuit 26 on the reproduction signal from the delay circuit 25, corrects the level, and outputs the level-corrected delayed reproduction signal via the capacitor _C2.
It is supplied to the base of PNP type transistor Tr2.

The collector of the transistor Tr1 is grounded,
Its emitter is connected to one fixed contact 281 of _the analog switch 28 constituting the circuit switching means, and is connected in the forward direction through a diode _D1 , and further through a resistor _R3 to a resistor _R4 whose one end is grounded and a capacitor. It is connected to the other end of the parallel circuit with _C3 and to the base of the emitter follower NPN transistor Tr3. Further, the transistor Tr2
The collector of is grounded, the emitter thereof is connected to the other fixed contact ₂₈₂ of the analog switch 28, and is connected in the forward direction through a diode _D2 ,
A resistor R ₅ whose one end is grounded via a further resistor R ₅
The other end of the parallel circuit with the capacitor _C4 and the base of the NPN type transistor Tr4 of the emitter follower is connected. The diode D ₁ , the resistor R ₃ ,
A circuit consisting of a parallel circuit of resistor _R4 and capacitor _C3 and a transistor Tr3 constitutes a peak level detection circuit that detects the peak level of the video signal in the undelayed reproduced signal, and a diode
A circuit consisting of D ₂ , resistor R ₅ , a parallel circuit of resistor R ₆ and capacitor C ₄ , and transistor Tr 4 constitutes a peak level detection circuit that detects the peak level of the video signal in the delayed reproduction signal. Each of the transistors Tr3 and Tr4 has its collector connected to the + power supply terminal, and its emitter grounded via a resistor. Note that in this circuit, if the capacitances of capacitors C ₃ and C ₄ are made relatively large, even if the peak level of the video signal has a waveform, the average value of the peak levels can be detected as the peak level.

The emitter output of the transistor Tr3 is supplied to one input terminal (+) of a differential amplifier 30 via an operational amplifier 29 of a voltage follower. Further, the emitter output of the transistor Tr4 is connected to the other input terminal (-) of the differential amplifier 30.
is supplied to. The differential amplifier 30 receives the peak level of the undelayed video signal and the peak level of the delayed video signal inputted through the transistors Tr3 and Tr4, detects the level difference, and uses the difference as an error voltage. The signal is outputted as , and is supplied to the input terminal C of the balanced modulation circuit 26 via a resistor.

The common contact ₂₈₃ of the analog switch 28 is connected to the resistor ₇ connected between the + power supply terminal and ground, the resistor of the series circuit consisting of the switch 31 and the capacitor _C5 .
Connected to the connection point between R ₇ and switch 31, and connected to the output amplifier 32 through resistors R ₈ and R ₉ in series.
is connected to the input terminal of Said capacitor _C5
The voltage across the terminals of the pedestal clamp circuit 33 is supplied to the input terminal of the pedestal clamp circuit 33. The output of this pedestal clamp circuit 33 is supplied to the base of the transistor Tr1 via a resistor R10, and the resistor R
11 to the base of the transistor Tr2. The resistors R ₇ , R ₁₀ , R ₁₁ , switch 31, capacitor C ₅ and pedestal clamp circuit 33 constitute pedestal level control means.

Further, the undelayed reproduction signal and synchronization signal from the demodulation circuit 24 and the delayed reproduction signal and synchronization signal from the adder 27 are input to the synchronization separation circuit 34 . The synchronous separation circuit 34 includes a pair of capacitors C ₅ and C ₇ and a pair of diodes D ₃ ,
It consists of a sync clamp circuit 35 consisting of _D4 , an integrating circuit 37 consisting of resistors R12 and R13, a capacitor _C8 , and an analog switch 36 that performs a circuit switching operation in synchronization with the analog switch 28, and a comparator 38.
The undelayed reproduction signal and synchronization signal from the adder ₂₇ are input to one end of the capacitor C6, and the delayed reproduction signal and synchronization signal from the adder 27 are input to one end of the capacitor _C7 . The diodes D ₃ and D ₄ are connected between the other ends of the capacitors C ₅ and C ₇ and the +V _S power supply terminal, respectively.
Note that each diode D ₃ and D ₄ has its anode connected to +
Connected to the V _S power supply terminal. Said capacitor C ₆
The other end is also connected to one fixed contact 36 ₁ of the analog switch 36 via the resistor R12. The other end of the capacitor C ₇ is also directly connected to the other fixed contact 36 ₂ of the analog switch 36 . The analog switch 36
The common contact ₃₆₃ of is grounded via the resistor R13 and capacitor _C8 . The connection point between the resistor R13 and the capacitor _C8 is connected to the input terminal of the comparator 38. The comparator 38 compares the input signal level with a preset slice level, detects it as a pedestal period of the reproduced signal only when the signal level is below the slice level, generates a horizontal synchronizing pulse during that period, and switches the switch 31. is turned on and its horizontal synchronizing pulse is output from the output terminal.

The output terminal of the synchronization separation circuit 34, that is, the output terminal of the comparator 38, is connected via a resistor R14 to the base of an NPN transistor Tr5 constituting a sync chip level setting means. The transistor Tr5 has its collector connected to the resistor.
Connect to the connection point between _R8 and _R9 , and ground its emitter through capacitor _C9 , and also connect resistor R15 and variable resistor between the + power terminal and ground.
VR is connected to the movable terminal of the variable resistor VR in the series voltage divider circuit of resistor R16. Note that a resistor R17 is connected between the base and emitter of the transistor Tr5.

In the apparatus according to the present invention configured as described above, the reproduced signal read out from the disk by the head 21 is passed through the amplifier 22 and the high-pass filter 23.
and is outputted via the demodulation circuit 24. The reproduced signal from the demodulation circuit 24 is delayed by a delay circuit 25 by 1/2 time of the horizontal synchronization period, that is, 0.5H. This delayed reproduction signal is transmitted to the balanced modulation circuit 26.
and is supplied to the adder 27. and adder 27
The output from the balanced modulation circuit 27 is superimposed on the reproduced signal delayed as it is, and the level is corrected, and the level-corrected reproduced signal is supplied to the base of the transistor _Tr2 via the capacitor C2.
On the other hand, the undelayed reproduced signal outputted from the demodulation circuit 24 is supplied to the base of the transistor _Tr1 via the capacitor C1. Therefore, the reproduced signal that is not delayed is output to the emitter of the transistor Tr1, and the transistor Tr
A delayed reproduction signal is output to the second emitter.

The peak level of the video signal in the reproduced signal output to the transistor Tr1 is determined by the diode D ₁ ,
It is detected by a circuit consisting of a resistor R ₃ , a resistor R ₄ , a capacitor C ₃ and a transistor Tr3, and is supplied to one input terminal (+) of a differential amplifier 30 via an operational amplifier 29.
_The peak level of _the video signal in the _reproduced signal _output to −). Therefore, the differential amplifier 3
1, the peak level of the video signal in the undelayed reproduced signal and the peak level of the video signal in the delayed reproduced signal are compared, and an error voltage corresponding to the difference is output. This error voltage is input to terminal C of the balanced modulation circuit 26. However,
The balanced modulation circuit 26 processes the input reproduced signal with a gain corresponding to the error voltage obtained by comparing the peak level of the video signal in the undelayed reproduced signal and the peak level of the video signal in the delayed reproduced signal. become. Therefore, the level-corrected playback signal output from the adder 27 which superimposes the output of the balanced modulation circuit 26 on the delayed playback signal is a video signal in which the peak level of the video signal is not delayed. It is corrected to match the peak level of .

Further, the pedestal level of the reproduced signal obtained via the analog switch 28 is held in the capacitor _C5 by the on/off operation of the switch 31. This holding voltage is determined by the pedestal clamp circuit 33.
through the transistor R10, and further through the resistor R10.
Supplied to the base of Tr1 and resistor R11
is supplied to the base of transistor Tr2 via
The operation of each of the transistors Tr1 and Tr2 is controlled so that the pedestal level of the undelayed reproduction signal and the pedestal level of the delayed reproduction signal match. Therefore, analog switch 2
The reproduced signal obtained through 8 is a signal in which the peak level and pedestal level of the video signal of the delayed signal and the undelayed signal are the same.

Furthermore, the horizontal synchronization pulse from the synchronization separation circuit 34 turns on the transistor Tr5, which causes a variable resistor VR to be set at the connection point between the resistors _R8 and _R9 , and held in the capacitor _C5. voltage appears. This voltage is set at a level that sets the sync chip level of the reproduced signal, so that the sync chip levels of the undelayed reproduced signal and the delayed reproduced signal are fixed at the set level. Therefore, the reproduced signal S _V finally output from the output amplifier 33 is a signal in which the peak level, pedestal level, and sync chip level of the video signal are the same for the undelayed signal and the delayed signal. becomes. Therefore, if the reproduced signal S _V output from the output amplifier 32 is displayed on a television receiver as a composite video signal,
No flicker appears on the screen, and you can get a clear screen without flickering.

Furthermore, in the synchronization separation circuit 34, when an undelayed horizontal synchronization pulse is input, the common contact ₃₆₃ of the analog switch 36 is connected to one fixed contact ₃₆₁ .
The integral constant of 7 is determined by the total resistance value of resistors R12 and R13 and the capacitance of capacitor _C8 , and when a delayed horizontal synchronization pulse is generated, the common contact ₃₆₃ of the analog switch 36 is connected to the other fixed contact _362. Therefore, the integral constant of the integrating circuit 37 at that time is determined by the resistance value of the resistor R13 and the capacitance of the capacitor _C8 . This switching of the integral constant can be done, for example, by changing the synchronization phase point of the delayed horizontal synchronization pulse when sliced by the comparator 38 from point _P2 to _P1 in FIG.
Move to a point. Therefore, the synchronization phase points of the undelayed horizontal synchronization pulse and the delayed horizontal synchronization pulse coincide at point _P1 . This eliminates the problem of the synchronization pulse being delayed with respect to the video signal, and the phenomenon that the image wavers from side to side does not occur.

Therefore, if the composite video signal obtained by this device is used, the receiver will be able to obtain a clear image without flickering due to flicker or horizontal fluctuation due to synchronization phase shift.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to match the synchronization phase of the horizontal synchronization pulse in the case where it is not delayed and in the case where it is delayed. Accordingly, it is possible to provide a television composite video signal waveform processing device that is free from problems.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of this invention, Fig. 2 is a circuit diagram showing an embodiment of the present invention;
FIG. 3 is a waveform diagram showing delay control of a reproduced signal by a delay circuit, FIG. 3 is a circuit diagram showing a conventional example, and FIG. 4 is a waveform diagram for explaining problems with synchronous separation. 21...Head, 24...Demodulation circuit, 25...
0.5H delay circuit, 28, 36...Analog switch, 31...Switch, 33...Pedestal clamp circuit, 34...Synchronization separation circuit, 37...Integrator circuit, 38...Comparator, R12, R13...
…Resistance, C ₅ , C ₈ , C ₉ … Capacitor, Tr1, Tr
2, Tr5...transistor.

Claims (1)

[Claims] 1. A demodulation circuit that outputs the playback signal taken out from a video signal storage medium that stores a composite video signal for displaying one frame of image in the 1 1/2 interlaced scanning method as a repeat playback signal of one field; A 0.5H delay circuit consisting of a charge-coupled device etc. that delays the reproduction signal from the demodulation circuit by 1/2 time of the horizontal synchronization period, and a reproduction signal output from this delay circuit and the same output from the demodulation circuit. circuit switching means for passing the reproduced signal alternately in every field repetition period; and a circuit switching means for alternately inputting the reproduction signal output from the delay circuit and the intact reproduction signal output from the demodulation circuit in each field repetition period; An integrating circuit is provided that switches the integral constant for each field repetition period so that the synchronization phases match when the horizontal synchronization pulses of both reproduction signals are sliced, and the circuit separates the synchronization pulse from the input reproduction signal and also separates the pedestal of the reproduction signal. A synchronization separation circuit outputs a pulse signal corresponding to a period, and a pulse signal corresponding to a pedestal period is inputted from the synchronization separation circuit, and a pedestal level of a reproduced signal passing through the circuit switching means is detected and held. , a pedestal level control means for controlling the pedestal levels of the reproduced signal outputted from the delay circuit and the intact reproduced signal outputted from the demodulation circuit to match each other, and responsive to a synchronization pulse from the synchronization separation circuit, sync chip level setting means for setting the sync chip level of the reproduced signal outputted from the delay circuit passing through the circuit switching means and the reproduced signal outputted as is from the demodulation circuit to a preset fixed potential; A television composite video signal waveform processing device characterized by: