JPH0476269B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a television composite video signal waveform processing device that is used, for example, when reading a composite video signal from a disk memory in an electronic still camera and displaying it on a television.

[Prior art and its problems] The standard television format is 1/2 interlaced scanning. For example, in the NTSC system, 1
The horizontal scanning line of the field is 262.5H (1H is one horizontal synchronization period), and 1 frame = 2 fields, which is 525H. Therefore, when playing back a rotating disk of an electronic still camera where 1 field = 262.5H is recorded in 1 rotation, horizontal synchronization is not possible at the recording joint (starting point or ending point).
This results in a shift of 0.5H, that is, 1/2 of the horizontal synchronization period, which causes screen distortion on a normal television receiver, making normal display impossible. For this reason, it is necessary to generate a continuous horizontally synchronized playback signal by passing the playback signal from the disk through a 0.5H delay circuit every other field in every cycle of repeating the field from the recording joint. That is, a in FIG. 6 shows the reproduced signal from the disk, but by delaying this by 0.5H every other field repetition period, a reproduced signal as shown in b in FIG. 6 can be obtained. I need to make one. Note that in the figure, V _S is a vertical synchronization signal, and H _S is a horizontal synchronization signal, and in this case, both signals are delayed every other signal.

However, when a 0.5H delay circuit is configured with a charge-coupled device such as a CCD element, the signal level changes due to loss fluctuations within the circuit, and this results in a difference between the non-delayed composite video signal level for each field and the delayed composite video signal level for each field. It appears as a difference with the signal level,
This level difference appears on the screen of the receiver as a change in brightness and darkness at the frame frequency, causing the problem that the screen flickers. For example, FIG. 7 is a circuit block diagram showing a conventional example.
This circuit supplies the reproduction signal read from the disk by the head 1 to the demodulation circuit 4 via the amplifier 2 and the high-pass filter 3, and supplies the reproduction signal output from the demodulation circuit 4 to the 0.5H delay circuit 5, and also supplies the reproduction signal output from the demodulation circuit 4 to the 0.5H delay circuit 5. It is supplied to the base of the PNP transistor Tr1 via _C1 . The reproduced signal delayed by 0.5H by the delay circuit 5 is sent to the balanced modulation circuit 6.
via a level correction circuit 8 consisting of an adder 7,
Furthermore, it is supplied to the base of the PNP transistor _Tr2 via the capacitor C2. The sync chip level of the reproduced signal output to the emitters of both transistors Tr1 and Tr2 is connected to diodes D ₁ , D ₂ ,
The signal is detected by sink chip level detection circuits 9 and 10 consisting of capacitors C ₃ and C ₄ and resistors R ₁ and R ₂ , and is supplied to a differential amplifier 11 . The differential amplifier 11 detects the difference between the sync chip level of the undelayed reproduced signal and the sync chip level of the delayed reproduced signal, and supplies the difference to the balanced modulation circuit 6 as an error voltage. The balanced modulation circuit 6 outputs a signal with a gain corresponding to the level of the error voltage, and the adder 7 outputs a delayed reproduction signal whose level has been corrected to match the level of the undelayed reproduction signal. . and each of the transistors Tr
A non-delayed reproduction signal and a delayed reproduction signal are alternately taken out from the emitter of Tr 1 and Tr 2 through an analog switch 12 which alternately switches its contacts every field repetition period, and are supplied to an output amplifier 13. Further, a synchronous separation circuit 14 is provided between the analog switch 12 and the output amplifier 13, and a pulse generated only during the pedestal period of the reproduced signal is output from the synchronous separation circuit 14, and the switch 15 is turned on during the pedestal period by the pulse. so that capacitor _C5 holds the pedestal level of the reproduced signal. This capacitor _C5
The pedestal level held at is supplied to a pedestal clamp circuit 16, and the output of the pedestal clamp circuit 16 is supplied to the bases of the transistors Tr1 and Tr2 via resistors _R3 and _R4 , respectively, to generate a reproduction signal that is not delayed. The pedestal level of the delayed reproduction signal is made to match the pedestal level of the delayed reproduction signal.

Therefore, in conventional circuits, the pedestal levels of the undelayed reproduced signal and the delayed reproduced signal are matched, and the level of the reproduced signal is corrected according to the difference in the sync chip level after the pedestal levels are matched. Output amplifier 1 for the subsequent reproduction signal
3, it is output as a composite video signal S _V. Therefore, in the conventional example, as shown in FIG.
The difference between the pedestal level L ₂ of the reproduced signal delayed by 0.5H and the sync level L ₁ is b ₂ , and the difference between the pedestal level L ₂ and the peak level L ₃ of the reproduced signal is a ₂ ,
Also, the pedestal level of the playback signal without delay
The difference between L ₂ ′ (=L ₂ ) and sink chip level L ₁ ′ is b ₁
If the difference between the pedestal level L ₂ ′ and the peak level L ₃ ′ of the video signal is a ₁ , then if the delay circuit 5 has no nonlinear distortion and the gain loss due to the signal level is constant, then a ₁ The relationship /b ₁ = a ₂ /b ₂ holds,
Even if the levels of the sync chips are compared and the levels are corrected, the video signal levels can be almost matched and there is no problem. If we use something consisting of a ₁ /b ₁ ≠
a ₂ /b ₂ , and as a result, comparing the sync chip levels and performing level correction could not match the video signal levels, which caused the problem of flickering due to bright and dark flickering on the screen. . This is particularly noticeable on bright screens that are easily noticeable to the eye (corresponding to the peak level of the video signal), and even if the peak level of the video signal is 1.
There was a problem in which flickering appeared even when the temperature changed by a certain percentage.

This invention was devised to solve this problem, and it performs waveform processing so that the level of the video signal in the delayed playback signal always matches the level of the video signal in the non-delayed playback signal. An object of the present invention is to provide a television composite video signal waveform processing device capable of obtaining a composite video signal without flickering caused by flickering.

Further, according to the present invention, the error voltage obtained by comparing the peak levels of the delayed video signal and the non-delayed video signal can be sufficiently converted into DC and supplied to the peak level correction means, and highly accurate peak level correction can be performed. An object of the present invention is to provide a television composite video signal waveform processing device.

Furthermore, this invention is a 0.5H device composed of CCD elements.
To provide a television composite video signal waveform processing device which uses a delay circuit, can compensate for waveform distortion of a delayed reproduction signal, can prevent flicker caused by this waveform distortion, and can more reliably prevent flickering. The purpose is to

[Means for Solving the Problems] The present invention provides a method for extracting a composite video signal for displaying one frame of image using a 1/2 interlaced scanning method from a video signal storage medium that stores one field of repeated playback signals. A demodulation circuit that outputs a reproduced signal, a 0.5H delay circuit consisting of a charge-coupled device such as a CCD element that delays the reproduction signal from this demodulation circuit by 1/2 the horizontal synchronization period, and a 0.5H delay circuit that outputs a reproduced signal from this demodulation circuit. circuit switching means for alternately passing the reproduced signal to be output and the reproduced signal as it is output from the demodulation circuit at each field repetition period; and a pulse that separates a synchronization pulse from the reproduced signal and corresponds to the pedestal period of the reproduced signal. A synchronous separation circuit outputs a signal, and a pulse signal corresponding to the pedestal period is inputted from this synchronous separation circuit, and the pedestal level of the reproduced signal passing through the circuit switching means is detected and held, and the pedestal level is output from the delay circuit. pedestal level control means for controlling the pedestal levels of the reproduced signal outputted from the delay circuit and the reproduced signal outputted as-is from the demodulation circuit to match each other; A pair of peak level detection means each detecting the peak level of the video signal, and a peak level detection means that compares the peak levels of the video signal detected by each of the peak level detection means, detects the difference, and outputs the difference as an error voltage. Level difference detection means, and the peak level of the video signal in the playback signal output from the delay circuit in response to the output level from the peak level difference detection means, and the peak level of the video signal in the playback signal output as is from the demodulation circuit. A peak level correction means corrects the peak level to match the peak level and supplies it to the circuit switching means, and a reproduction signal output from a delay circuit that responds to the synchronization pulse from the synchronization separation circuit and passes through the circuit switching means, and output from the demodulation circuit. A sync chip level setting means is provided for setting the sync chip level of the reproduced signal as it is to a preset fixed potential, thereby obtaining a television composite video signal for image display.

Further, in the present invention, the output voltage from the peak level difference detection means is integrated via an integrating circuit and is supplied to the peak level correction means.

Further, in the present invention, a 0.5H delay circuit is constructed of CCD elements, and a waveform compensation circuit comprising a resistor and a capacitor is provided on the input side or output side of the delay circuit.

[Function] With the above-described configuration, the present invention compares the peak level of the video signal in the delayed reproduced signal with the peak level of the video signal in the undelayed reproduced signal, and calculates the error voltage from the difference.
Based on the error voltage, the level of the delayed playback signal is made to match the level of the undelayed video signal,
Further, the pedestal level control means matches the pedestal level of the delayed reproduction signal with the pedestal level of the undelayed reproduction signal, and the sync chip setting means makes the sync chip level of the delayed reproduction signal match the sync chip level of the undelayed reproduction signal. By setting the level to a fixed potential, the peak level, pedestal level, and sync chip level of the video signal in the delayed reproduction signal and the non-delayed reproduction signal are made to match, respectively.

Further, the error voltage from the peak level difference detection means is converted into a sufficient DC voltage by an integrating circuit and is supplied to the peak level correction means.

Further, the waveform distortion of the reproduced signal delayed by 0.5H by the delay circuit is compensated for by the waveform compensation circuit to obtain a delayed reproduced signal without distortion.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

Reference numeral 21 denotes a head, and this head 21 receives a playback signal from a disk, which is a video signal storage medium, which stores a composite video signal for displaying a 1-frame image using the 1/2 interlace scanning method as a 1-field repeated playback signal. I'm trying to read it out. The reproduced signal read by this head 21 is sent to an amplifier 22.
and a demodulation circuit 24 via a high-pass filter 23
is supplied to. The demodulation circuit 24 has the function of outputting a reproduction signal and a synchronization signal, and outputs the reproduction signal by a charge-coupled device such as a CCD element.
It is supplied to the 0.5H delay circuit 25 and also to the base of the PNP transistor _Tr1 via the capacitor C1. Note that the synchronization signal is supplied to a synchronization separation circuit (not shown) and is synchronously separated. The delay circuit 25 delays the input reproduction signal by 1/2 time of the horizontal synchronization period, and supplies this delayed reproduction signal to the input terminal of the balanced modulation circuit 26 and the adder 27 constituting the peak level correction means. are doing. The balanced modulation circuit 26 inputs a reference voltage obtained by a voltage dividing circuit of resistors R ₁ and R ₂ to its input terminal B, and also inputs an error voltage from a peak level difference detection means to be described later to its input terminal C. The input reproduction signal is processed with a gain according to the magnitude of the error voltage, a positive or negative polarity signal is output from the output terminal O, and the signal is supplied to the adder 27. The adder 27 superimposes the signal from the balanced modulation circuit 26 on the reproduction signal from the delay circuit 25, corrects the level, and sends the level-corrected delayed reproduction signal to the PNP transistor _Tr2 via the capacitor C2. Supplied to the base. The collector of the transistor Tr1 is grounded, and its emitter is connected to one fixed contact 28 of an analog switch 28 constituting circuit switching means.
The other end of a parallel circuit consisting of a resistor _R4 and a capacitor _C3 , one end of which is grounded through a diode _D1 in the forward direction and a resistor _R3 , and an emitter follower NPN transistor Tr3.
connected to the base of. Further, the collector of the transistor Tr2 is grounded, and its emitter is connected to the other fixed contact 2 of the analog switch 28.
The other end of a parallel circuit consisting of a resistor _R5 and a capacitor _C4 , one end of which is connected to 82 in the forward direction through a diode _D2 and one end of which is grounded through a resistor _R5 , and an emitter follower NPN type transistor Tr.
Connected to the base of 4. the diode
D ₁ , resistor R ₃ , a parallel circuit of resistor R ₄ and capacitor C ₃ , and transistor Tr 3 constitute a peak level detection means for detecting the peak level of the video signal in the undelayed reproduced signal, and the diode D ₂ , resistor R ₅ , resistor R ₆ and capacitor C ₄
A circuit consisting of the parallel circuit and the transistor Tr4 constitutes peak level detection means for detecting the peak level of the video signal in the delayed reproduction signal. Each of the transistors Tr3 and Tr4 has its collector connected to the + power supply terminal, and its emitter grounded via a resistor. Note that in this circuit, if the capacitances of capacitors C ₃ and C ₄ are made relatively large, even if the peak level of the video signal has a waveform, the average value of the peak levels can be detected as the peak level. the transistor
The emitter output of Tr3 is passed through the operational amplifier 29 of the voltage follower to one input terminal (+) of the differential amplifier 30 that constitutes the peak level difference detection means.
is supplied to. Further, the transistor Tr4
The emitter output of the differential amplifier 30 is supplied to the other input terminal (-) of the differential amplifier 30. The differential amplifier 3
0 inputs the peak level of the undelayed video signal and the peak level of the delayed video signal inputted through each transistor Tr3 and Tr4, detects the level difference, and outputs the difference as an error voltage; The signal is supplied to the input terminal C of the balanced modulation circuit 26 via a resistor.

The common contact 283 of the analog switch 28 is connected to the resistor ₇ connected between the + power supply terminal and ground, the resistor of the series circuit consisting of the switch 31 and the capacitor _C5 .
It is connected to the connection point between R ₇ and the switch 31 and the input terminal of the synchronous separation circuit 32, and the resistor R ₈ ,
It is connected to the input terminal of the output amplifier 33 via _R9 in series. The synchronization separation circuit 32 outputs a pulse and a synchronization pulse that are generated only during the pedestal period of the reproduced signal, turns on the switch 31 for the pedestal period with the pulse generated during the pedestal period, and outputs the synchronization pulse to the sync chip level setting means. It is supplied to the base of the constituent NPN transistor Tr5. The voltage across the terminals of the capacitor C ₅ is supplied to the input terminal of the pedestal clamp circuit 34 . The output of this pedestal clamp circuit 34 is connected to the transistor Tr via a resistor R10.
It is supplied to the base of the transistor Tr2 and also to the base of the transistor Tr2 via the resistor R11. The resistors R10 and R11, the switch 31, the capacitor _C5 , and the pedestal clamp circuit 34 constitute a pedestal level control circuit. The emitter of the transistor Tr5 is grounded via a capacitor _C5 , and a resistor R12, a variable resistor VR, and a resistor R1 are connected between the + power supply terminal and the ground.
It is connected to the variable terminal of the variable resistor VR in the series voltage divider circuit No. 3. The collector of the transistor Tr5 is connected to the connection point between the resistors _R8 and _R9 . Note that the base of the transistor Tr5,
A resistor R14 is connected between the emitters.

In the apparatus according to the present invention configured as described above, the reproduced signal read out from the disk by the head 21 is passed through the amplifier 22 and the high-pass filter 23.
and is outputted via the demodulation circuit 24. The reproduction signal from the demodulation circuit 24 is delayed by a delay circuit 25 by 1/2 time of the horizontal synchronization period, that is, 0.5H. This delayed reproduction signal is transmitted to the balanced modulation circuit 26.
and is supplied to the adder 27. and adder 27
The output from the balanced modulation circuit 27 is superimposed on the reproduced signal delayed as it is, and the level is corrected, and the level-corrected reproduced signal is supplied to the base of the transistor _Tr2 via the capacitor C2.
On the other hand, the undelayed reproduced signal outputted from the demodulation circuit 24 is supplied to the base of the transistor _Tr1 via the capacitor C1. Therefore, the reproduced signal that is not delayed is output to the emitter of the transistor Tr1, and the transistor Tr
A delayed reproduction signal is output to the second emitter.

The peak level of the video signal in the reproduced signal output to the transistor Tr1 is determined by the diode D ₁ ,
It is detected by a circuit consisting of a resistor R ₃ , a resistor R ₄ , a capacitor C ₃ and a transistor Tr3, and is supplied to one input terminal (+) of a differential amplifier 30 via an operational amplifier 29.
_The peak level of _the video signal in the _reproduced signal _output to −). Therefore, the differential amplifier 3
0, the peak level of the video signal in the undelayed reproduced signal and the peak level of the video signal in the delayed reproduced signal are compared, and an error voltage corresponding to the difference is output. Therefore, the balanced modulation circuit 26 receives the input reproduction signal with a gain corresponding to the error voltage obtained by comparing the peak level of the video signal in the undelayed reproduction signal and the peak level of the video signal in the delayed reproduction signal. It will be processed. Therefore, this balanced modulation circuit 26
The level-corrected playback signal output from the adder 27, which superimposes the output of It will be corrected.

Further, the pedestal level of the reproduced signal obtained via the analog switch 28 is held in the capacitor _C5 by the on/off operation of the switch 31. This holding voltage is determined by the pedestal clamp circuit 34.
through the transistor R10, and further through the resistor R10.
Supplied to the base of Tr1 and resistor R11
is supplied to the base of transistor Tr2 via
The operation of each of the transistors Tr1 and Tr2 is controlled so that the pedestal level of the undelayed reproduction signal and the pedestal level of the delayed reproduction signal match. Therefore, analog switch 2
The reproduced signal obtained through 8 is a signal in which the peak level and pedestal level of the video signal of the delayed signal and the undelayed signal are the same.

Furthermore, the transistor Tr5 is turned on by the synchronization pulse from the synchronization separation circuit 32, which causes a variable resistor VR to be set at the connection point between the resistors _R8 and _R9 , and held in the capacitor _C5. A voltage appears. This voltage is set at a level that sets the sync chip level of the reproduced signal, so that the sync chip levels of the undelayed reproduced signal and the delayed reproduced signal are fixed at the set level. Therefore, the reproduced signal finally output from the output amplifier 33 is a signal in which the three levels of the peak level, pedestal level, and sync chip level of the video signal match between the undelayed signal and the delayed signal. . Therefore, the output amplifier 3
If the reproduced signal outputted from 3 is displayed on a television receiver as a composite video signal, flicker due to level changes will not appear on the screen, and a clear screen without flickering will be obtained.

In addition, in the peak level detection means, resistors R ₃ and R ₅ are connected in series with the diodes D ₁ and D ₂ , respectively, which prevents the influence of noise transiently superimposed on the video signal and stabilizes the peak level. It can be detected.

Next, another embodiment of the invention will be described with reference to the drawings. Note that the same parts as in the above embodiment are given the same reference numerals, and detailed explanations will be omitted.

First, Figure 2 shows the circuit configuration of the main part, in which the emitter of the transistor Tr3 is connected to the input terminal (+) of the differential amplifier 30 via the resistor R15, and the emitter of the transistor Tr4 is connected to the input terminal (+) of the differential amplifier 30. It is connected to the input terminal (+) of the operational amplifier 35 of the voltage follower via the resistor R16, and an integrating capacitor _C7 is connected between the input terminal (-) and the output terminal of the differential amplifier 30. are doing.
A bias circuit formed by connecting a resistor R17, a variable resistor VR ₁ and a resistor R18 in series is connected between the input terminal (+) of the differential amplifier 30 and the input terminal (+) of the operational amplifier 35. The differential amplifier 30
The output terminal of is connected to the connection point between resistors R19 and R20 via a diode limiter _D3 . One end of the resistor R19 is connected to the + power supply terminal, and one end of the resistor R20 is grounded. The voltage appearing at the connection point between the resistors R19 and R20 is supplied to the integrating circuit 36. This integrating circuit 36
is a capacitor _C8 with one end connected to the + power supply terminal.
and a capacitor _C9 whose one end is grounded, and the connection point of this series circuit and the resistors R19 and R19.
20 connection points and a resistor R21 connected between the two connection points. The output of the integration circuit 36 is then supplied to the input terminal C of the balanced modulation circuit 26.

In such a configuration, noise can be removed by cutting out unnecessary alternating current components by the action of capacitor _C7 . Further, since the unbalance of the signals output from each transistor Tr3 and Tr4 is amplified by the differential amplifier 30, the offset voltage becomes a problem. Therefore, in this circuit, a bias circuit is used to cause the levels at the input terminal (+) of the differential amplifier 30 and the input terminal (+) of the operational amplifier 35 to change in opposite directions as the variable resistor VR ₂ changes. The offset voltage is corrected by applying a DC voltage. In this case, if the unbalance of the signals output from each of the transistors Tr3 and Tr4 is particularly biased to one side, a bias circuit may be used that applies a DC voltage to only one side.

Furthermore, since the operational amplifier 35 is inserted in the path of the signal obtained by detecting the peak level of the delayed video signal, it becomes easier to balance the signals output from the transistors Tr3 and Tr4. Furthermore, since the output of the differential amplifier 30 is integrated by the integrating circuit 36 with a large time constant, the balanced modulation circuit 30
The voltage supplied to 6 is sufficiently converted into direct current, and the peak level can be corrected more reliably. Also, this integrating circuit 36 uses two capacitors C ₈ and C ₉ , one of which is connected to the + power supply terminal, and the other is connected, so when the power is turned on, the capacitance ratio of both capacitors is Charging is performed, and therefore, even when the power is turned on, a voltage close to normal DC voltage can be obtained in a short time, and the transient time can be shortened.

Furthermore, when the video signal is switched when the reproduced signal is extracted from the disk, noise and the like are added at that moment, causing a temporary unbalanced state in the detected outputs from the respective transistors Tr3 and Tr4. This unbalance is amplified by the differential amplifier 30, thereby generating a large voltage in the amplifier 30. As a countermeasure to the case where this voltage is biased in the positive direction, a circuit including a diode D ₃ and resistors R19 and R20 is provided to limit the voltage. That is, even if the output voltage of the amplifier 30 rises above the voltage divided by the resistors R19 and R20, that high voltage will not be supplied to the integrating circuit 36 due to the action of the diode _D3 . Therefore, it is possible to prevent a phenomenon in which a large transient voltage is applied to the integrating circuit and cause the operating point to fluctuate, and it is also possible to prevent flicker from occurring during switching transients.

In addition, the circuit shown in FIG. 3 is replaced with the diode D ₃ and resistors R19 and R20 in FIG.
An anti-parallel circuit of diodes D ₄ and D ₅ is used, and one end of the circuit is connected to a differential amplifier 30 via a resistor R22.
and the input terminal of the integrating circuit 36, and the other end of the circuit is connected to the output terminal of the integrating circuit 36.
10 and is connected to a resistor connection point of a series voltage divider circuit consisting of a resistor R23 whose one end is connected to the + power supply terminal and a resistor R24 whose one end is grounded.

Thereby, even if the output of the differential amplifier 30 fluctuates greatly in both positive and negative directions, it is possible to limit it and reliably prevent fluctuations in the operating point of the integrating circuit 36.

In this circuit, instead of the balanced modulation circuit 26, a variable amplifier 3 is constructed of transistors Tr6 and Tr7 and an incandescent light bulb Lm as a variable resistance element whose resistance value changes depending on the magnitude of the DC voltage or current.
8 is used.

The variable amplifier 38 supplies the emitter output of the emitter follower transistor Tr6 to the base of the transistor Tr7 via a resistor, and applies the emitter DC voltage of the transistor Tr7 to the incandescent light bulb Lm. Further, the delayed reproduction signal is passed through the capacitor C11 to the transistor
It is supplied to the base of Tr7. In this circuit, when the emitter voltage of the transistor Tr6 increases, the emitter voltage of the transistor Tr7 also increases, and the internal resistance value of the incandescent light bulb Lm increases. This causes the amplification degree of transistor Tr7 to decrease. Therefore, such a circuit can also achieve the same effect as the balanced modulation circuit 26 described above.
Note that in this case, a positive characteristic thermistor, a negative characteristic thermistor, or the like may be used instead of the incandescent light bulb.

In this way, a variable amplifier using a variable resistance element can be used instead of the balanced modulation circuit, so the circuit can be simplified and the cost can be reduced.

Furthermore, the one shown in Fig. 4 is the 0.5H delay circuit 2.
5 is composed of a CCD element, and a waveform compensation circuit 39 is inserted on the input side of the delay circuit 25. The waveform compensation circuit 39 is a series circuit of an NPN transistor Tr8 and an emitter resistor R25,
A series circuit of resistors R26 and R27, the emitter of the transistor Tr8, and the resistors R26 and R27
It consists of a series circuit of a resistor R28 and a capacitor C12 connected between the connection point of the resistor R28 and a parallel circuit of a resistor R29. In addition, R28≫R29,
C12/R28>>H (horizontal synchronization period) is set.

If such a circuit is used, even if a delay circuit consisting of a CCD element is used, an integral waveform distortion will occur within the horizontal synchronization period as shown by the dotted line in Figure 5, and the original white image V will be distorted. Even if a fluctuation in .DELTA.V occurs, the waveform is compensated by the action of resistor R28 and capacitor C12, and can be returned to a flat waveform as shown by the solid line in FIG. In this regard, if this waveform compensation circuit is not used, the right side of the screen will be bright and the left side will be dark due to the fluctuation of ΔV shown by the dotted line in the figure, causing flicker on the left and right sides of the screen.

Note that the same effect can be obtained even if this waveform compensation circuit is inserted on the output side of the delay circuit 25.

[Effects of the Invention] As detailed above, according to the present invention, waveform processing is performed so that the video signal level of the delayed playback signal always matches the video signal level of the non-delayed playback signal, thereby eliminating flicker on the screen. It is possible to provide a television composite video signal waveform processing device that can obtain a composite video signal without flickering.

Further, according to the present invention, the error voltage obtained by comparing the peak levels of the delayed video signal and the non-delayed video signal can be sufficiently converted into DC and supplied to the peak level correction means, allowing highly accurate peak level correction. Accordingly, it is possible to provide a television composite video signal waveform processing device that can perform the following operations.

Furthermore, according to the present invention, in a device using a 0.5H delay circuit composed of a CCD element, it is possible to compensate for waveform distortion of the delayed reproduction signal, and flicker due to this waveform distortion can be prevented, making flickering more reliable. Therefore, it is possible to provide a television composite video signal waveform processing device that can prevent such problems from occurring.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram showing one embodiment of this invention, FIGS. 2, 3, and 4 are main circuit diagrams showing other embodiments of this invention, and FIG. A waveform diagram to explain the operation of the circuit, Fig. 6 is a waveform diagram showing delay control of the reproduced signal by the delay circuit, Fig. 7 is a circuit block diagram showing a conventional example, and Fig. 8 shows the level of the reproduced signal in the conventional example. FIG. 21...Head, 24...Demodulation circuit, 25...
0.5H delay circuit, 26...Balanced modulation circuit, 27...
...Adder, 28...Analog switch, 30...
Differential amplifier, 31... Switch, 32... Synchronous separation circuit, 34... Pedestal clamp circuit, 36
... Integration circuit, 38 ... Variable amplifier, 39 ... Waveform compensation circuit, D ₁ , D ₂ ... Diode, R ₃ , R ₄ ,
R ₅ , R ₆ , R12, R13...Resistance, C ₃ , C ₄ , C ₅ ,
C ₆ ... Capacitor, Tr1, Tr2, Tr3, Tr4,
Tr5...transistor, VR...variable resistor.

Claims (1)

[Claims] Output the above-mentioned reproduction signal taken out from a video signal storage medium that stores a composite video signal for displaying one frame of image in a 1 1/2 interlaced scanning method as a one-field repetitive reproduction signal. A 0.5H delay circuit consisting of a charge-coupled device such as a CCD element that delays the reproduction signal from this demodulation circuit by 1/2 the horizontal synchronization period, and the reproduction signal output from this delay circuit and circuit switching means for alternately passing the reproduced signal outputted from the demodulation circuit as it is for each field repetition period; and separating a synchronization pulse from the reproduction signal and outputting a pulse signal corresponding to a pedestal period of the reproduced signal. a synchronous separation circuit; a pulse signal corresponding to a pedestal period is inputted from the synchronous separation circuit; the pedestal level of the reproduction signal passing through the circuit switching means is detected and held; and the reproduction signal is output from the delay circuit; pedestal level control means for controlling the pedestal levels of the signal and the reproduced signal as it is outputted from the demodulation circuit to match each other; and the reproduction signal outputted from the delay circuit and the reproduction signal as it is outputted from the demodulation circuit. a pair of peak level detection means for respectively detecting the peak level of the video signal at , and comparing the peak level of the video signal detected by each of the peak level detection means,
peak level difference detection means for detecting the difference and outputting it as an error voltage; and demodulating the peak level of the video signal in the reproduced signal output from the delay circuit in response to the output level from the peak level difference detection means. peak level correction means for correcting the reproduced signal outputted from the circuit as it is to match the peak level of the video signal and supplying the corrected signal to the circuit switching means; and a peak level correction means for supplying the corrected signal to the circuit switching means; sync chip level setting means for setting the sync chip level of the reproduced signal outputted from the delay circuit and the reproduced signal output as is from the demodulation circuit to a preset fixed potential;
A television composite video signal waveform processing device characterized in that it obtains a television composite video signal for image display. 2. The pair of peak level detection means includes a diode for peak detection, a resistor connected in series with the diode, a parallel circuit of a capacitor and a resistor connected between this resistor and ground, and a parallel circuit consisting of a resistor and a capacitor connected between the resistor and the ground, and a 2. The television composite video signal waveform processing device according to claim 1, further comprising an emitter follower circuit of transistors that responds to an inter-voltage voltage. 3. The peak level difference detection means uses a differential amplifier consisting of an operational amplifier, and superimposes DC voltages whose levels change in opposite directions due to changes in a variable resistor on both input terminals of the differential amplifier. A television composite video signal waveform processing device according to claim 1 or 2, characterized in that the offset voltage is corrected. 4. The peak level difference detection means uses a differential amplifier consisting of an operational amplifier, and corrects the offset voltage by superimposing a variable DC voltage on one of the input terminals of the differential amplifier using a variable resistor. A television composite video signal waveform processing device as claimed in claim 1 or 2. 5. The peak level correction means includes a balanced modulation circuit that outputs a signal with a gain corresponding to the magnitude of the output level from the peak level difference detection means, and an output signal from the balanced modulation circuit to the reproduced signal from the 0.5H delay circuit. A television composite video signal waveform processing apparatus according to claim 1, 2, 3, or 4, characterized in that it comprises means for superimposing levels. 6. The peak level correction means uses a transistor and a variable resistance element whose resistance value changes depending on the magnitude of the DC voltage or DC current, and has a gain of 0.5 according to the magnitude of the output level from the peak level difference detection means. A television composite video signal waveform processing apparatus according to claim 1, 2, 3, or 4, characterized in that the apparatus comprises means for variably amplifying the reproduced signal from the H delay circuit. . 7. A demodulation circuit for outputting the above-mentioned reproduction signal taken out from a video signal storage medium storing a composite video signal for displaying one frame of image in the 7 1/2 interlace scanning method as a one-field repetitive reproduction signal; A 0.5H delay circuit consisting of a charge-coupled device such as a CCD element that delays the reproduction signal from the demodulation circuit by 1/2 time of the horizontal synchronization period, and the reproduction signal output from this delay circuit and the reproduction signal output from the demodulation circuit. circuit switching means for alternately passing the reproduced signal as it is for each field repetition period; a synchronization separation circuit for separating a synchronization pulse from the reproduction signal and outputting a pulse signal corresponding to the pedestal period of the reproduction signal; A pulse signal corresponding to the pedestal period is inputted from the synchronization separation circuit, the pedestal level of the reproduced signal passing through the circuit switching means is detected and held, and the reproduced signal outputted from the delay circuit and the demodulation circuit are a pedestal level control means for controlling the pedestal levels of the reproduced signals output as they are to match each other; and a peak level of the video signal in the reproduced signal outputted from the delay circuit and the reproduced signal outputted as is from the demodulation circuit. a pair of peak level detection means each detecting the peak level of the video signal detected by each of the peak level detection means,
A peak level difference detection means for detecting the difference and outputting it as an error voltage, an integrating circuit for integrating the output voltage from the peak level difference detecting means, and an output from the delay circuit in response to the output level of the integrating circuit. peak level correction means for correcting the peak level of the video signal in the reproduced signal to match the peak level of the video signal in the reproduced signal directly output from the demodulation circuit and supplying the corrected signal to the circuit switching means; In response to a synchronization pulse from the separation circuit, the sync chip level of the reproduction signal output from the delay circuit passing through the circuit switching means and the reproduction signal output as is from the demodulation circuit is set to a preset fixed potential. and a sync chip level setting means for setting,
A television composite video signal waveform processing device characterized in that it obtains a television composite video signal for image display. 8 The integrating circuit consists of a resistor and two capacitors connected in series, one end of the resistor is connected to the connection point of each of the capacitors, and the non-connection point side of one capacitor is grounded, and the other end is connected to the connection point of each capacitor. 8. The television composite video signal waveform processing device according to claim 7, wherein the non-connection point side of the capacitor is connected to a power supply terminal. 9. A demodulation circuit for outputting the above-mentioned reproduction signal taken out from a video signal storage medium storing a composite video signal for displaying one frame of image in the 1/2 interlaced scanning method as a one-field repetitive reproduction signal; Consists of a CCD element that delays the reproduced signal from the demodulation circuit by 1/2 the horizontal synchronization period.
A 0.5H delay circuit, a waveform compensation circuit consisting of a resistor and a capacitor inserted on the input side or output side of this delay circuit, and a reproduced signal outputted via the delay circuit and waveform compensation circuit and from the demodulation circuit. circuit switching means for alternately passing the reproduced signal as it is output at each field repetition period; and a synchronization separation circuit for separating a synchronization pulse from the reproduction signal and outputting a pulse signal corresponding to a pedestal period of the reproduction signal. A pulse signal corresponding to the pedestal period is inputted from the synchronization separation circuit, the pedestal level of the reproduced signal passing through the circuit switching means is detected and held, and the pulse signal is outputted via the delay circuit and the waveform compensation circuit. pedestal level control means for controlling the pedestal levels of the reproduced signal outputted from the demodulation circuit and the reproduced signal outputted from the demodulation circuit as they are, and the reproduction signal outputted via the delay circuit and the waveform compensation circuit and the demodulation circuit; A pair of peak level detection means each detecting the peak level of the video signal in the playback signal as it is outputted from the device, and the peak level of the video signal detected by each of the peak level detection means is compared, and the difference is determined. a peak level difference detection means for detecting and outputting it as an error voltage; and a peak level of the video signal in the reproduced signal outputted via the delay circuit and the waveform compensation circuit in response to the output level from the peak level difference detection means. peak level correction means for correcting the signal to match the peak level of the video signal in the reproduced signal outputted from the demodulation circuit as it is and supplying the corrected signal to the circuit switching means; a sync chip that sets a sync chip level of a reproduced signal outputted via the delay circuit and waveform compensation circuit that passes through the circuit switching means and a reproduced signal output as is from the demodulation circuit to a preset fixed potential; What is claimed is: 1. A television composite video signal waveform processing device comprising a level setting means to obtain a television composite video signal for image display.