JPS6394787A - Field/frame conversion system - Google Patents

Abstract

PURPOSE:To prevent the production of a V jitter by generating a correction pulse retarding the front edge of a vertical synchronizing signal by a prescribed quantity based on the vertical synchronizing signal detected by a demodulation output and adding the said correction pulse to the demodulation signal. CONSTITUTION:A composite synchronizing signal outputted from a synchronizing separation circuit 28 is integrated, amplified and outputted from a collector of a transistor (TR) Q2. On the other hand, the composite synchronizing signal outputted from the emitter of a TR Q1 is ANDed with the output signal outputted from the collector of the TR Q2 via a diode D2. An output signal of a V synchronizing separation circuit 304 outputted to the base of a TR Q6 is an inverted signal, the TR Q6 is conductive by a switching pulse SWP (c) and inverted at the output via the TR Q6. The signal is ANDed with a signal outputted via diodes D2, D3 to obtain the correction pulse 116.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a field/frame conversion method in magnetic recording, and particularly to
The present invention relates to a field/frame conversion method that aims to prevent the occurrence of jitter.

[Background of the invention]

It is well known that when constructing television images, so-called interlaced scanning is employed for horizontal scanning in order to reduce flickering to the eyes. In the case of the NTSC system, this interlaced scanning is a [2:1] interlaced scanning system. [2:1] In the interlaced scanning method, one screen (frame) is constructed by superimposing two coarse screens (fields) formed by one vertical scan. Thus, the number of frame repetitions is 30 times per second and the number of field repetitions is 60 times per second. Further, between the odd field and the even field, the horizontal scanning amount (II) is shifted by 0.5H.

By the way, when recording video signals on a recording medium such as a magnetic tape or a magnetic disk, various recording methods are employed. Among these recording methods, a method has been proposed in which, for example, a video signal is separated into a luminance signal and a chroma signal, and each signal is subjected to certain signal processing and then subjected to FM modulation before being recorded on a magnetic recording medium or the like. There is.

In playback using this type of recording method, a frame signal is created from one type of field signal by scanning the same recorded portion twice, making use of the strong vertical correlation of the video signal.
A so-called field/frame conversion method is adopted. In this field/frame conversion method, it is not possible to convert the field signal into odd and even fields by simply repeating the same field signal, so a field signal delayed by 0.5H and a signal not delayed ( A through system) is formed and these are switched every vertical scanning period to obtain an odd field and an even field.

Now, in the case of the above field/frame conversion method, 0
．． 0.5 field signal using 5H delay line
A signal delayed by H time was obtained, and a CCD was used for this 0.5H delay line.

A delay line using a CCD does not have a very good signal-to-noise ratio and does not have a wide frequency characteristic, so it has been necessary to separate a luminance signal and a chroma signal and convert them into frame signals. For this reason, two different delay lines (
Since a glass delay line and a CCD delay line are used, there is a problem in that due to the difference in the characteristics of these delay lines, there is a large difference in delay time between a luminance signal and a chroma signal, resulting in color shift.

Furthermore, instead of using two different types of delay lines as described above, it is conceivable to use a CCD delay line as a delay line for the luminance signal and chroma signal, and to apply a time delay of 0.5H to at least the luminance signal after demodulation.

However, in this case, a slight level difference occurs between the through luminance signal and the luminance signal delayed by 0.5H, resulting in flicker of 30 Hz. There is a problem in that the circuit configuration becomes complicated in order to prevent the occurrence of flicker.

Therefore, by using a glass delay line with broadband frequency characteristics and performing the 0 and 5H delay operation described above for the field signal in the FM state, the field/
A method of frame conversion has been proposed. According to this method, the above-mentioned S/N reduction, color shift, and flicker can be prevented from occurring.

However, by alternately selecting a signal obtained by delaying the field signal by 0.5H and a signal without delaying it for each vertical scanning period, the field/field signal is converted into a frame signal.
When field/frame conversion is performed using the frame conversion method, jitter occurs in the image reproduced on the television screen.This V jitter refers to one horizontal scanning line (IH ) width in the vertical direction (■ direction) of the image. That is, the television image in this case fluctuates up and down in 18 widths every field period (1/60 second).

By the way, it has been found that this jitter can be prevented from occurring by delaying the leading edge of the vertical synchronization signal included in the luminance signal by a period of 0.25H.

[Purpose of the invention]

The present invention has been made based on the above-mentioned new findings, and an object thereof is to provide a field/frame conversion method that prevents the occurrence of jitter.

[Summary of the invention]

In order to achieve the above object, the present invention repeatedly reproduces an FM-modulated field signal recorded on a magnetic recording medium, passes the reproduced FM field signal through a delay circuit whose delay time is two horizontal scanning periods, A frame signal is obtained by alternately selecting an FM field signal delayed by two horizontal scanning periods and an FM field signal not delayed by switching a switch every vertical scanning period, and then demodulating the output signal of the switch. In the field/frame conversion method, a vertical synchronization signal is detected from the demodulated output, a correction pulse is created based on the vertical synchronization signal to delay the leading edge of the vertical synchronization signal by a predetermined amount, and the correction pulse is It is characterized in that it is added to the demodulated signal.

[Embodiments of the invention]

Hereinafter, preferred embodiments of the field/frame conversion method according to the present invention will be described with reference to the accompanying drawings. 1st
The figure shows the configuration of a reproducing system of a magnetic recording and reproducing apparatus to which the present invention is applied. In the figure, a field signal repeatedly reproduced from a magnetic recording medium (not shown) by a magnetic head 10 is amplified by an amplifier 12 and then filtered by a filter 14.
．． 16, the signal is separated into an FM luminance signal Y□ and an FM color signal CFM. Here, the color signal reproduction system is not directly related to the gist of the present invention, so its explanation will be omitted.The FM luminance signal YF, which has amplitude fluctuations removed by the limiter 18, is directly or directly connected to the 0.5H delay line. The signal is input to the analog switch 22 via 20. The analog switch 22 is controlled to switch between contacts a and b by a control signal 50 having the timing shown in FIG. 2(C). That is, the through FM luminance signal 100 and 0 .
1) Period 51 in which the FM luminance signal 102 delayed by 5Hil is selected and the FM luminance signal 102 delayed by 0.5H is selected, from the front equalization pulse section to the hack equalization pulse section. The analog switch 22 is controlled so that the through FM luminance signal 100 is selected during the period 52 (FIGS. 2(a), (b), (C)
)).

Note that the second line indicating the switching timing of the analog switch 22
For convenience of explanation, the time axis in Figure (C) is shown reduced compared to other signals. For example, period 52 in Figure (C)
．． 53 corresponds to the period 60.61 in the FM luminance signal 102 shown in FIG.

Now, the frame signal 104 (or 106) obtained by switching this analog switch 22 (Fig.
d) and (e)) are demodulated by the FM demodulator 24 and output to the adder circuit 26 and the synchronization separation circuit 28. A composite synchronization signal is extracted from the FM demodulation output input to the synchronization separation circuit 28 and output to the correction pulse generation circuit 30. Correction pulse creation circuit 30 is 0.5H
This circuit creates a correction pulse necessary to delay the leading edge of the vertical synchronization signal in the delayed FM luminance signal by a predetermined amount, for example, 0.258.

The correction pulse created by the correction pulse creation circuit 30 is added to the luminance signal output from the FM demodulator 24 by an adder 26, and the leading edge of the vertical synchronization signal from the adder 26 is delayed by 0.25H. The brightness signal of the base hunt is output.

Next, the configuration of the correction pulse generation circuit 30 is shown in 3M. In the figure, the correction pulse generation circuit 30 is the synchronization separation circuit 28.
■ Synchronization separation/delay circuit 302 that separates the vertical synchronization signal from the composite synchronization signal 110 (112) outputted from the composite synchronization signal 110 (112) and delays the vertical synchronization signal by a predetermined value N (for example, 0.25H), and the composite synchronization signal Separate the vertical sync signal from
It consists of a synchronization separation circuit 304, and an arithmetic circuit 306 consisting of an AND gate 308, 310 and an analog switch 312 whose switching is controlled by a switching pulse SWP (C) output from a control circuit (not shown).

In the above configuration, the composite synchronization signal output from the synchronization separation circuit 28 is a composite synchronization signal 110 obtained from the through demodulated luminance signal and a composite synchronization signal 110 obtained from the through demodulated luminance signal as shown in FIGS.
There is a composite synchronization signal 112 obtained from the demodulated luminance signal delayed by 5H. These composite synchronization signals 110.1
12, during the vertical retrace period T from the front equalization pulse to the hack equalization pulse, the field/
Since the through FM luminance signal is selected during frame conversion, the output timings of the horizontal synchronization signal, equivalent pulse, and vertical synchronization signal are exactly the same.

■The synchronization separation/delay circuit 302 separates the vertical synchronization signal from the composite synchronization signal 110 (or 112), inverts the vertical synchronization signal, and delays it by a predetermined amount, for example, 0°25H, to one input of the AND gate 308. output at the end (Fig. 4(C)). (2) The output signal of the synchronization separation/delay circuit 302 and the composite synchronization signal 110 (or 112) are ANDed by an AND gate 308;
The output signal (Fig. 4 (g), (h)) of AND gate 3
It is output to one input terminal of 10.

Also, the synchronization separation circuit 304 separates the vertical synchronization signal from the composite synchronization signal 110 (or 112), and the AND gate 31
0 to the other input terminal (FIG. 4(d)). In the AND gate 310, the output signal of the AND gate I-308 and V
An AND with the vertical synchronization signal output from the synchronization separation circuit 304 is performed (FIG. 4(i)). This anime game) 3
The pulse signal obtained as the No. 10 output signal is output at a period of 1.times., that is, every time the field signal delayed by 0.5H and the through field signal are alternately output.

However, what is required as the correction pulse is only the pulse signal output from the AND gate 310 during the period in which the field signal delayed by 0.58 is output.

Therefore, the analog switch 312, which is switched and controlled by the switching pulse swp<c> outputted at the timing shown in FIG. AND gate 310 during the period in which the field signal delayed by 5H is output.
The pulse signal output from the correction pulse 116
is output to the adder 26. Here analog switch 3
12 is switched to the contact a side during a period in which a field signal delayed by 0.5H for each IV is output, and to the contact side in a period in which a through field signal is output. In addition, the switching pulse SWP shown in FIG.
For convenience of explanation, the time axis of (C) is shown reduced compared to other signals, and the same time axis as the other signals is shown in (f) of the same figure.
It becomes as shown in .

The correction pulse 116 is added to the demodulated luminance signal output from the FM demodulator 24 by the adder 26, and the leading edge of the vertical synchronization signal ends up being the pulse width of the correction pulse (the shaded part in FIG. 4(j)). A baseband luminance signal delayed by 0°25H, which corresponds to , is obtained ((j) in the same figure).

Next, a specific circuit configuration example of the correction pulse generation circuit 30 is shown in FIG. In the same figure, ■ synchronous separation/delay circuit 302
are resistors R3, R4, variable resistor VR1 and capacitor C1
, C2, and C3, and an amplification stage including a transistor Q2 and a resistor R5. The variable resistor VRI is configured to be able to adjust the delay amount of the vertical synchronization signal, and for example, the delay amount is set to a time corresponding to 0.25H as described above.

Also, the synchronous separation circuit 304 includes a diode D1, capacitors C5, C6, resistors R8, R9, RIO1Rll, R1
2. Consists of a variable resistor VR2, transistors Q4 and C5, and the arithmetic circuit 306 includes diodes D2 and D3.
, D4, resistors R13 and R14, and a transistor Q6. Here, diodes D2 and D3 are connected to AND gate 308, and transistor Q6 is connected to AND gate 308.
10 and analog switch 312 (Fig. 3)
. An emitter follower is configured by transistor Q1 and resistors R1 and R2, and transistor Q3 and resistors R6 and R7
and transistor Q3 constitute an amplification stage.

In the above configuration, the composite synchronization signal output from the synchronization separation circuit 28 is transmitted through the resistor R3 via the emitter follower described above.
, R4, variable resistor ■R1 and capacitors C1, C2, C
3, is integrated by the integrating circuit, is further amplified by the transistor Q2, and is output from the collector of the transistor Q2 (Fig. 4 (C)).
.

On the other hand, the composite synchronization signal (Fig. 4(a), (b)) output from the emitter of transistor Q1 is ANDed with the output signal output from the collector of transistor Q2 via diode D2 via diode D3. (Fig. 4 (g), (h)).

In addition, the composite synchronization signal inputted to the synchronization separation circuit 304 via the transistor Q3 of the amplification stage is integrated by an integrating circuit (with a small time constant) consisting of a diode D1 and a capacitor C5, and a signal almost synchronized with the vertical synchronization signal is obtained. The signal is extracted and output to the base of transistor Q6 via transistors Q4 and Q5 of the amplification stage. This transistor Q6
The output signal of the synchronization separation circuit 304, which is output to the base of the transistor Q6, is an inverted signal of the signal shown in FIG.
becomes conductive, and when it is outputted through the transistor Q6, it is inverted and becomes the same signal as shown in FIG. 4(d). This signal is logically ANDed with the signal output via diodes D2 and D3, and a correction pulse 116 is obtained.

〔Effect of the invention〕

As explained above, in the present invention, the FM field signal delayed by two horizontal scanning periods and the FM field signal not delayed are alternately selected every vertical scanning period to obtain a frame signal, and then the frame signal is obtained. In a field/frame conversion method for demodulating a signal, detecting a vertical synchronizing signal from the demodulated output, and creating a correction pulse that delays the leading edge of the vertical signal by a predetermined amount based on the vertical signal,
Since the correction pulse is added to the demodulated signal, according to the present invention, it is possible to prevent the occurrence of jitter caused by field/frame conversion.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a reproducing system of a magnetic recording/reproducing apparatus to which the present invention is applied, FIG. 2 is a timing chart showing the operation of the reproducing system shown in FIG. 1, and FIG. 3 is a diagram similar to that shown in FIG. A configuration diagram showing a schematic configuration of a correction pulse generation circuit in
FIG. 4 is a timing chart showing the operation of the correction pulse generation circuit shown in FIG. 3, and FIG. 5 is a circuit diagram showing a specific example of the correction pulse generation circuit. 20...0.5H delay line, 22...analog switch, 24...FM demodulator, 26...
- Adder, 28... Synchronous separation circuit, 30... Correction pulse creation circuit, 302... ■ Synchronous separation/delay circuit, 304... ■ Synchronous separation circuit, 308.310.
...and gate, 312...analog switch.

Claims (1)

[Claims] Repeatedly reproducing an FM-modulated field signal recorded on a magnetic recording medium, passing the reproduced FM field signal through a delay circuit whose delay time is 1/2 horizontal scanning period,
An FM field signal delayed by 1/2 horizontal scanning period and an FM field signal not delayed are alternately selected every vertical scanning period by switching a switch to obtain a frame signal, and then the output signal of the switch is selected. In a field/frame conversion method for demodulating a vertical synchronization signal, a vertical synchronization signal is detected from the demodulation output, a correction pulse is created to delay the leading edge of the vertical synchronization signal by a predetermined amount based on the vertical synchronization signal, and the correction pulse is A field/frame conversion method characterized by adding the above demodulated signal to the demodulated signal.