JPS61230479A - Processor for composite video signal waveform of television - Google Patents

Abstract

PURPOSE:To eliminate the occurrence of a flicker on a screen by a waveform process to coincide the level of a video signal in a reproducing signal that is delayed with the level of the video signal in the reproducing signal that is not delayed without receiving the influence by temperature and the like. CONSTITUTION:The peak level of the video signal in the reproducing signal that is delayed by H/2 at a delay circuit 25 and the peak level of the video signal in the reproducing signal that is not delayed are inputted respectively to the input terminals of a pair of operational amplifiers 29 and 30 which are easy to be balanced and also, the output of each operational amplifier is inputted to a differential amplifire 31 and an error voltage is obtained byh comparing those. Based upon the error voltage, these are coincided with the level of the video signal of both signals and also the pedestal levels of both reproducing signals are coincided by a pedestal level circuit 37 and furthermore, the sync chip levels of both reproducing signals are fixed at a fixed potential by an NPN transistor Tr 3. Thus, the composite video signal from which possibility of occurrence of flickering by the flicker is eliminated is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a television composite video signal waveform processing device used, for example, when reading a composite video signal from a disk memory in an electronic still camera and displaying it on a television.

[Prior art and its problems] The standard television system is 1/2 interlaced scanning. For example, in the NTSC system, the horizontal scanning line of one field is 262.5H (one day is one horizontal opening period), and one frame=2 fields is 525H. Therefore, 1 field -262,5H is 1
When reproducing a rotating disk of an electronic still camera that is recorded in rotation, the horizontal synchronization at the recording joint (starting point or ending point) will be off by 0.58, that is, 1/2 of the horizontal synchronization period, which is normal for image reception. The screen on the machine becomes distorted and cannot be displayed normally. For this reason, it is necessary to generate a continuous horizontally synchronized reproduction signal from the recording joint by passing the reproduction signal from the disk through a 0.5H delay circuit every other field repetition period. That is, (a
) shows the playback signal from the disk, but it is necessary to create a playback signal as shown in Figure 2 (b) by delaying this by 0.5) 1 every other field for each field repetition period. be. In addition, v9 in the figure is a vertical synchronization signal, H8
is a horizontal synchronizing signal, and in this case, both signals are delayed every other signal.

However, the 0.58 delay circuit is connected to a charge-coupled device (CO
When configured with The difference appears on the screen of the receiver as a change in brightness and darkness at the frame frequency, causing the problem that the screen flickers.

For example, FIG. 3 is a circuit block diagram showing a conventional example.
In this circuit, a reproduced signal read from a disk by a head 1 is passed through an amplifier 2 and a bypass filter 3 to a demodulation circuit 4.
and the reproduced signal output from the demodulation circuit 4 is set to 0.
．． 58 is supplied to the delay circuit 5 and the capacitor 031
The voltage is supplied to the base of the PNP transistor Tr31 via the transistor Tr31.

The reproduced signal delayed by 0.58 in the delay circuit 5 is supplied to the base of a PNP transistor Tr32 via a level correction circuit 8 consisting of a balanced modulation circuit 6 and an adder 7, and roughly via a capacitor C32. There is. The sync tip level of the reproduced signal output to the emitters of both the transistors Tr31 and Tr32 is connected to the diode D31, [)3.
2. Detected by sync chip level detection circuit 9.10 consisting of capacitors C33 and C34 and resistors R31 and R32,
It is supplied to the differential amplifier 11. The differential amplifier 11 detects the difference between the sync tip level of the undelayed reproduction signal and the sync tip level of the delayed reproduction signal, and supplies the difference to the balanced modulation circuit 6 as an error voltage. The balanced modulation circuit 6 outputs a signal with a gain corresponding to the difference in the level of the error voltage, and the adder 7 outputs a delayed reproduction signal whose level has been corrected to match the level of the undelayed reproduction signal. .

Then, an undelayed reproduction signal and a delayed reproduction signal are alternately taken out from the emitters of the transistors Tr31 and Tr32 and supplied to an output amplifier 13 via an analog switch 12 that alternately switches the contact points at each field repetition period. . Further, the analog switch 1
A synchronous separation circuit 14 is provided between 2 and the output amplifier 13,
This synchronization separation circuit 14 outputs a pulse that is generated only during the pedestal period of the reproduced signal, and the pulse is used to switch the switch 15.
is turned on during the pedestal period to cause the capacitor C35 to maintain the pedestal level of the reproduced signal.

The pedestal level held in this capacitor 035 is supplied to a pedestal clamp circuit 16, and the output of the pedestal clamp circuit 16 is connected to each of the transistors Tr31 and Tr32 via resistors R33 and R311, respectively.
The pedestal level of the undelayed reproduction signal is made to match the pedestal level of the delayed reproduction signal.

Therefore, in conventional circuits, the pedestal levels of the undelayed playback signal and the delayed playback signal are made to match, and the level of the video signal is corrected according to the difference in the sync chip level after making the pedestal levels match. The reproduced signal is output from the output amplifier 13 as a composite video signal Sv. Therefore, in the conventional example, as shown in FIG. 4, for example, the difference between the pedestal level L2 of the reproduced signal delayed by 0.5 days and the sync chip level L1 is b2, and the difference between the pedestal level L2 and the peak level L3 of the video signal is b2. a2, and the pedestal level L2' of the reproduced signal without delay.
(=L2) and the sync tip level L1' is b
When the difference between the pedestal level L2' and the peak level 1B' of the video signal is al at l, if the delay circuit 5 has no nonlinear distortion and the gain loss due to the signal level is constant, al/b1- The relationship a2/b2 is established, and even if the sync chip levels are compared and level corrected, the video signal levels can be made to roughly match and there is no problem. However, as a delay circuit, non-linear distortion may occur. When using a device composed of a charge-coupled device that produces
/b1≠a2/b2, and as a result, if the level is corrected by comparing the sync chip levels, it is not possible to match the video signal levels, which causes the problem of flickering due to bright and dark flickering on the screen. there were. This is particularly noticeable on screens with brightness that is easily noticeable to the eye (corresponding to the peak level of the video signal), and even if the peak level of the video signal changes by about 1%, there is a problem in which flickers appear. .

In order to solve this problem, the present inventors first developed a pair of peak level detection means for detecting the peak levels of the video signal in the playback signal output from the delay circuit and the playback signal as it is output from the demodulation circuit, respectively. , a peak level difference detection means that compares the peak levels of the video signals detected by the respective peak level detection means, detects the difference, and outputs it as an error voltage; and a peak level difference detection means that responds to the output level from the peak level difference detection means. peak level correction means for correcting the peak level of the video signal in the playback signal output from the delay circuit so as to match the peak level of the video signal in the playback signal output as is from the demodulation circuit, and supplying the corrected signal to the circuit switching means; A television composite video signal waveform processing device is provided. (Special application 1984
(Refer to Publication No. 196219) An example of the circuit in this prior application is as shown in FIG. That is, in this circuit, the emitter of the transistor Tr31 (see FIG. 3) is connected to the diode [
) 33 in the forward direction, and further via a resistor R35 to the other end of a parallel circuit of a resistor R36 and a capacitor 036, one end of which is grounded, and the base of an emitter follower NPN transistor Tr33. Also, the emitter of the transistor 7r32 (see Figure 3) is connected to the diode D3.
4 in the forward direction, one end of which is grounded through the resistor R37, and the other end of the parallel circuit of the resistor R3B and the capacitor C37, and the emitter follower NPN transistor T.
Connected to the base of r34. The transistor T
The emitter of r33 is connected to the differential amplifier 17 via a resistor R39.
is connected to the input terminal (+) of the transistor T r3
4 is connected to the input terminal (+) of the operational amplifier 18 of the voltage follower through the resistor R40, and an integrating capacitor is connected between the input terminal (-) and the output terminal of the differential amplifier 17. 03B is connected. The input terminal (+) of the differential amplifier 17 and the input terminal (+) of the operational amplifier 18
+) is connected with a bias circuit including a resistor R41, a variable resistor VR, and a resistor R42 connected in series. The output terminal of the differential amplifier 17 is connected to a diode limiter [) 3
5 to the connection point between resistors R43 and R44. One end of the resistor R43 is connected to the power supply terminal, and one end of the resistor R44 is grounded. Then, the voltage appearing at the connection point of the resistors R43 and R44 is collected by an integrating circuit 19.
is supplied to. This integrating circuit 19 is connected between a series circuit of a capacitor C39 whose one end is connected to the power supply terminal and a capacitor C40 whose one end is grounded, and the connection point of this series circuit and the connection point of the resistors R43 and R44. and a resistor R45. The output of one of the integrating circuits is supplied to the input terminal C of the balanced modulation circuit 6.

In this circuit, the peak level of the video signal in the reproduced signal output to the transistor Tr31 is determined by the diode [)33, resistor R35, resistor R36 and capacitor 03.
The peak level of the video signal in the reproduced signal is detected by a circuit consisting of a transistor Tr33 and a transistor Tr33, and is supplied to one input terminal (+) of the differential amplifier 17, and is output to a transistor Tr32.
, resistor R37, resistor R38, capacitor C37 and transistor 7r34, and is supplied to the other input terminal (-) of differential amplifier 17 via operational amplifier 18. Then, the differential amplifier 17 compares the peak level of the video signal in the undelayed reproduction signal and the peak level of the video signal in the delayed reproduction signal, and outputs an error voltage according to the difference.

Therefore, the balanced modulation circuit 6 receives the input reproduction signal with a gain corresponding to the error voltage obtained by comparing the peak level of the video signal in the undelayed reproduction signal and the peak level of the video signal in the delayed reproduction signal. It will be processed.

However, in this circuit, although the conventional problems can be solved, the transistors Tr33 and Tr34 are connected to the differential amplifier 17.
Since the transistors are located on the input side of the circuit, any unbalance in the voltage between the base and emitter of each transistor will greatly affect the operation of the circuit. In particular, transistors are easily affected by temperature, so each transistor Tr33,
If there is a temperature difference or a difference in temperature characteristics in the Tr34, the difference acts as an offset voltage equivalent to the voltage difference in the video signal input via the diodes D33 and [)34, and becomes a difference in the detected voltage output. appears. When this offset voltage reaches 0.5% of the video signal, it directly affects the voltage difference between the video signals, resulting in a 0.5% voltage difference between the video signals.

If there is a voltage difference of 0.5%, a problem occurs in which flicker appears in the image.

The present invention has been made in view of the above circumstances, and it is possible to make the level of the video signal in the delayed reproduction signal and the video signal level in the video signal in the non-delayed reproduction signal unaffected by temperature or the like. To provide a television composite video signal waveform processing device capable of processing waveforms so that they always match and obtaining a composite video signal without the risk of flickering on the screen due to flicker.

[Means for Solving the Problems] The present invention provides a method for extracting a composite video signal for displaying one frame of image using a 1/2 interlaced scanning method from a video signal storage medium that stores it as a one-field repetitive reproduction signal. (0, 5) consisting of a demodulation circuit that outputs a reproduced signal, and a charge-coupled device that delays the reproduced signal from this demodulation circuit by 1/2 time of the horizontal synchronization period (delay circuit and output from this delay circuit). a circuit switching means for alternately passing the reproduced signal outputted from the demodulation circuit and the reproduced signal as it is outputted from the demodulation circuit at each field repetition period; and a pulse signal that separates a synchronization pulse from the reproduced signal and corresponds to the pedestal period of the reproduced signal. A synchronous separation circuit outputs a pulse signal corresponding to the pedestal period, and a pulse signal corresponding to the pedestal period is inputted from the synchronous separation circuit, and the pedestal level of the reproduced signal passing through the circuit switching means is detected and held, and is output from the delay circuit. A pedestal level control means for controlling the pedestal levels of the reproduced signal and the reproduced signal as-is outputted from the demodulation circuit to match each other, and an image in the reproduced signal outputted from the delay circuit and the reproduced signal as-is outputted from the demodulation circuit. a pair of peak level detection means for respectively detecting the peak level of the signal; a pair of operational amplifiers; connected between the output terminals of each operational amplifier;
It has a resistor circuit that supplies a balanced voltage of the same level to one input terminal of the amplifier, and a differential amplifier that receives the output from the output terminal of each operational amplifier and detects the difference voltage, and detects each peak level. peak level difference detection means for inputting the peak level of the video signal detected by the means to the other input terminal of each operational amplifier, and outputting the difference between the peak levels from the differential amplifier as an error voltage;
In response to the output level from this peak level difference detection means, the peak level of the video signal in the playback signal output from the delay circuit is corrected so that it matches the peak level of the video signal in the playback signal output as is from the demodulation circuit. peak level correction means for supplying the signal to the circuit switching means, a reproduction signal outputted from a delay circuit that responds to the synchronization pulse from the synchronization separation circuit and passes through the circuit switching means, and a reproduction signal output as it is from the demodulation circuit. sync chip level setting means for setting the sync chip level to a preset fixed potential to obtain a television composite video signal for image display.

[Function] By having the above-described configuration, the present invention transfers the peak level of the video signal in the delayed reproduced signal and the peak level of the video signal in the undelayed reproduced signal from the resistor circuit to one input terminal with a balanced voltage of the same level. is input to the other input terminal of a pair of operational amplifiers that can be easily balanced, and roughly compares the output of each operational amplifier by inputting it to a differential amplifier to determine the error voltage. Matching the level of the delayed video signal with the level of the undelayed video signal based on the error voltage, and matching the pedestal level of the delayed playback signal with the pedestal level of the undelayed playback signal by a pedestal level control means; By roughly setting the sync tip level of the delayed reproduction signal and the sync tip level of the undelayed reproduction signal to fixed potentials by the sync chip setting means, the peak level of the video signal in the delayed reproduction signal and the undelayed reproduction signal is determined. , the pedestal level and the sync tip level are made to match each other.

[Embodiments of the invention] Embodiments of the present invention will be described below with reference to the drawings.

Reference numeral 21 denotes a head, and this head 21 receives a playback signal from a disk, which is a video signal storage medium, which stores a composite video signal for displaying one frame of image in a 1/2 interlace scanning method as a one-field repeated playback signal. I'm trying to read it out.

The reproduction signal read by this head 21 is supplied to a demodulation circuit 24 via an amplifier 22 and a bypass filter 23. The demodulation circuit 24 functions to output a reproduction signal and a synchronization signal, and outputs the reproduction signal to a charge-coupled device (COD).
> is supplied to the 0- and 5-day delay circuit 25, and also connected to the PNP transistor Tr via the capacitor C1.
1 base. Note that the synchronization signal is supplied to a synchronization separation circuit (not shown) and is synchronously separated. The delay circuit 25 delays the input reproduced signal by 1/2 time of the horizontal synchronization period, and sends this delayed reproduced signal to the input terminal 2 of the balanced modulation circuit 26 constituting the peak level correction means and to the adder 27. supplying. The balanced modulation circuit 26 inputs to its input terminal B a reference voltage obtained by a voltage dividing circuit of resistors R1 and R2, and also inputs to its input terminal C an error voltage from a peak level difference detection means to be described later. The input reproduced signal is processed with a gain according to the magnitude of the voltage, a positive or negative polarity signal is output from the output terminal 0, and the signal is supplied to the adder 27. The adder 27 superimposes the signal from the balanced modulation circuit 26 on the reproduction signal from the delay circuit 25, corrects the level, and sends the level-corrected delayed reproduction signal to the base of the PNP transistor Tr2 via the capacitor C2. is supplied to. The collector of the transistor Tr1 is grounded, and its emitter is connected to one fixed contact 281 of the analog switch 28 constituting the circuit switching means, and one end is grounded through the diode D1 in the forward direction and the resistor Ra. The other end of the parallel circuit of the resistor R4 and the capacitor C3 is connected to the input terminal (+) of the first operational amplifier 29. The collector of the transistor Tr2 is grounded, and the emitter thereof is connected to the other fixed contact 282 of the analog switch 28, through a diode D2 in the forward direction, and through a resistor R5, which is a resistor whose one end is grounded. R6 and capacitor C
4 and the input terminal (+) of the second operational amplifier 30. A circuit consisting of the diode D1, the resistor R:1, a parallel circuit of the resistor R4 and the capacitor C3 constitutes a peak level detection means for detecting the peak level of the video signal in the undelayed reproduced signal, and the diode D2, the resistor R5, A circuit consisting of a parallel circuit of a resistor R6 and a capacitor C4 constitutes peak level detection means for detecting the peak level of the video signal in the delayed reproduction signal.

In this circuit, if the capacitances of the capacitors C3 and C4 are made relatively large, even if the peak level of the video signal has a waveform, the average value of the peak levels can be detected as the peak level.

A series circuit of resistors R15, R16, and R17 is connected as a resistor circuit between the output terminals of each of the operational amplifiers 29 and 30, and the connection point between the resistors R15 and R16 is connected to the input terminal of the first operational amplifier 29 ( -), and the connection point between the resistor RIB and R17 is connected to the input terminal (-) of the second operational amplifier 30. In addition, the resistance R
15 and R17 have the same resistance value. The output terminal of the first operational amplifier 29 is connected to the input terminal (+) of the differential amplifier 31 via a resistor R1B, and further connected to the movable terminal of the first variable resistor VR1 via a resistor R19. ing. The output terminal of the second i-arithm amplifier 30 is connected to the input terminal (-) of the differential amplifier 31 via a resistor R20.
is connected to. The differential amplifier 31 has its input terminal (
-) and its output terminal, a resistor R21 and a capacitor C
A parallel circuit with 7 is connected.

The differential amplifier 30 receives the peak level of the undelayed video signal and the peak level of the delayed video signal input from each operational amplifier 29, 30, detects the level difference, and uses the difference as an error voltage. I am trying to output it. The output terminal of the differential amplifier 31 is connected to a voltage limiting circuit 32 via a resistor R22. This voltage limiting circuit 32 is composed of a series circuit of a pair of constant voltage diodes ZD1 and zD2, and the resistor R22 is connected to the connection point between the anode of one constant voltage diode ZD1 and the cathode of the other constant voltage diode ZD2. There is. The cathode of the one constant voltage diode ZD1 is connected to the + power supply terminal, and the anode of the other constant voltage diode ZD2 is grounded. A connection point between the anode of one constant voltage diode ZD1 and a cathode of the other constant voltage diode ZD2 is connected to a connection point of a series circuit of a pair of capacitors C9 through a resistor R23 forming an integrating circuit 33. There is.

The other end of the one capacitor Ca is connected to the power supply terminal, and the other end of the other capacitor C9 is grounded.

The contact points of the capacitors CB and C9 are supplied to the input terminal C of the balanced modulation circuit 26 via a resistor R24.

The common contact 28 of the analog switch 28 is the connection point between the resistor R7 and the switch 34 of the series circuit of the resistor 7, the switch 34, and the capacitor C5 connected between the power supply terminal and the ground, and the input terminal of the synchronous separation circuit 35. and the output amplifier 36 via resistors R8 and R9 in series.
is connected to the input terminal of The synchronization separation circuit 35 outputs a pulse generated only during the pedestal period of the reproduced signal and a synchronization pulse, turns on the switch 34 for the pedestal period by the pulse generated during the pedestal period, and configures the synchronization pulse as a sync chip level setting means. It is supplied to the base of the NPN transistor Tr3. The voltage between the terminals of the capacitor C5 is supplied to the input terminal of the pedestal clamp circuit 37. This pedestal clamp circuit 3
7 to the transistor Tr1 via the resistor R10.
It is also supplied to the base of the transistor Tr2 via the resistor R11. The resistance R
7, R10, R11, the switch 34, the capacitor C5, and the pedestal clamp circuit 37 constitute pedestal level control means. The emitter of the transistor Tr3 is grounded via a capacitor C6, and the emitter of the variable resistor VR2 in a series voltage divider circuit consisting of a resistor R12, a second variable resistor VR2, and a resistor R13 is connected between the power supply terminal and the ground. Connected to a movable terminal. The collector of the transistor Tr3 is connected to the connection point between the resistors R8 and R9. Note that a resistor R14 is connected between the base and emitter of the transistor Tr3.

In the apparatus according to the embodiment of the present invention configured as described above, the reproduced signal read from the disk by the head 21 is outputted via the amplifier 22, the bypass filter 23, and the demodulation circuit 24. The reproduced signal from the demodulation circuit 24 is delayed by a delay circuit 25 by 1/2 time of the horizontal synchronization period, that is, by 005 days. This delayed reproduction signal is supplied to a balanced modulation circuit 26 and an adder 27. Then, the balanced modulation circuit 2 receives the reproduced signal delayed by the adder 27 as it is.
7 is superimposed and level-corrected, and the level-corrected reproduction signal is supplied to the base of the transistor Tr2 via the capacitor C2.

On the other hand, the undelayed reproduced signal outputted from the demodulation circuit 24 is passed through the transistor T via the capacitor C1.
supplied to the base of rl. However, transistor T
An undelayed reproduction signal is output to the emitter of r1,
A delayed reproduction signal is also output to the emitter of the transistor Tr2.

The peak level of the video signal in the reproduced signal output to the transistor Trl is detected by a circuit consisting of a diode D1, a resistor R3, a resistor R4, and a capacitor CE+, and is output to one input terminal of the differential amplifier 31 via one operational amplifier 29. (+), and also the transistor Tr
2, and is detected by the regeneration path output to the differential amplifier 31 via the other operational amplifier 30 to the other input terminal (-
). Then, the differential amplifier 31 compares the peak level of the video signal in the undelayed reproduced signal and the peak level of the video signal in the delayed reproduced signal, and outputs an error voltage according to the difference. This error voltage is input to the input terminal C of the balanced modulation circuit 26 via the voltage limiting circuit 32 and the integrating circuit 33. Therefore, the balanced modulation circuit 26 receives the input reproduction signal with a gain corresponding to the error voltage obtained by comparing the peak level of the video signal in the undelayed reproduction signal and the peak level of the video signal in the delayed reproduction signal. It will be processed. Therefore, the level-corrected playback signal output from the adder 27 that superimposes the output of the balanced modulation circuit 26 on the delayed playback signal as it is is the peak level of the video signal in the undelayed playback signal. It will be corrected to match the level. Furthermore, this circuit uses operational amplifiers 29 and 30 that ensure balance even if there is a temperature change in the circuit section that detects the level difference.
Moreover, since the balanced voltage that determines the degree of amplification while maintaining balance is input to each of the operational amplifiers 29 and 30 from the resistor circuit, even if there is a temperature change, the level fluctuation due to it is surely canceled out in the differential amplifier 31. will be done. Therefore, even if there is a temperature change, the peak level of the reproduced signal obtained by level-correcting the delayed reproduced signal will surely match the peak level of the video signal in the undelayed reproduced signal. It will be corrected. Further, offset voltage can be compensated by adjusting the input level to the input terminal (+) of the differential amplifier 31 by adjusting the first variable resistor (R1).

Further, the pedestal level of the reproduced signal obtained via the analog switch 28 is held in the capacitor C5 by the on/off operation of the switch 34. This holding voltage is supplied to the base of the transistor Tr1 via the pedestal clamp circuit 37, roughly via the resistor RIO, and also to the base of the transistor Tr2 via the resistor R11, and is delayed by the operation of each transistor Tr1 and Tr2. The pedestal level of the reproduced signal that is not delayed matches the pedestal level of the delayed reproduced signal. Therefore, the reproduced signal obtained via the analog switch 28 is a signal in which the peak level and pedestal level of the video signal of the delayed signal and the undelayed signal match.

Furthermore, the transistor Tr3 is turned on by the synchronization pulse from the synchronization separation circuit 35, and the resistor R8 is thereby turned on.
A voltage set by the second variable resistor VR2 and held in the capacitor C6 appears at the connection point between and R9. This voltage is set to a level that sets the sync tip level of the reproduced signal, and thereby the sync tip levels of the undelayed reproduced signal and the delayed reproduced signal are fixed at the set level. Therefore, the reproduced signal Sv finally output from the output amplifier 36 is a signal in which the three levels of the peak level, pedestal level, and sync tip level of the video signal match between the undelayed signal and the delayed signal. . Therefore, if the playback signal Sv output from the output amplifier 36 is displayed on a television receiver as a composite video signal, no flicker will appear on the screen due to level changes even if the temperature changes. You can get a clear screen.

In addition, since the output of the differential amplifier 31 is integrated by the integrating circuit 33 with a large time constant, the voltage supplied to the balanced modulation circuit 26 is sufficiently converted into DC, and the peak level can be corrected more reliably. become able to. Moreover, this integrating circuit 33 uses two capacitors C8 and CB, one of which is connected to the + power supply terminal and the other is grounded, so that when the power is turned on, charging is performed according to the capacitance ratio of both capacitors. Therefore, even when the power is turned on, a voltage close to normal DC voltage can be obtained in a short time, and the transient time can be shortened.

Furthermore, during transitions such as when starting a reproduction operation or switching reproduction tracks, noise is added instantaneously, causing a temporary unbalanced state in the detected output.

This unbalance is amplified by the differential amplifier 31. However, such voltage is limited by the voltage limiting circuit 32, and even if the voltage is biased toward the positive or negative side, the integrating circuit 33
Since the voltage supplied to the integrator is limited to a certain voltage range, it is possible to prevent phenomena such as large transient voltages being applied to the integrator circuit and cause the operating point to fluctuate, and also to prevent flicker from occurring during switching transients. be able to.

In the above embodiment, a voltage limiting circuit and an integral circuit are inserted between the differential amplifier and the balanced modulation circuit, but this is not necessarily necessary in the present invention.

[Effects of the Invention] As detailed above, according to the present invention, the level of the video signal in the delayed reproduction signal and the level of the video signal in the video signal in the undelayed reproduction signal are not affected by temperature or the like. It is therefore possible to provide a television composite video signal waveform processing device that can perform waveform processing so that they always match, and can obtain a composite video signal that is free from the risk of flickering on the screen.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a waveform diagram showing delay control of a reproduced signal by a delay circuit, Fig. 3 is a circuit diagram showing a conventional example, and Fig. 4 is a conventional reproduced signal. FIG. 5 is a waveform diagram for explaining the level shift of , and FIG. 5 is a partial circuit diagram for explaining the process of realizing the present invention. 21...Head, 24...Demodulation circuit, 25...0
．． 5H delay circuit, 26... Balanced modulation circuit, 28...
Analog switch, 29.30... operational amplifier, 31
... Differential amplifier, 34 ... Switch, 35 ... Synchronous separation circuit, 37 ... Pedestal clamp circuit, Dl
, D2...diode, R3, R4, RF! , R
s, R15, RlB, R17...Resistance, CB, C
4, Cs, C6... Capacitor, Trl, Tr2.
...Juunjista. Applicant's agent Patent attorney Takehiko SuzueflXzFigure 4Figure 5

Claims (1)

[Claims] A demodulation circuit that outputs the playback signal taken out from a video signal storage medium that stores a composite video signal for displaying one frame of an image in a 1/2 interlace scanning method as a one-field repeated playback signal, and the demodulation circuit A 0.5H delay circuit consisting of a charge-coupled device that delays the reproduction signal from the circuit by 1/2 time of the horizontal synchronization period, and a reproduction signal output from this delay circuit and the same output from the demodulation circuit. A circuit switching means for alternately passing the reproduced signal for each field repetition period; a sync separation circuit for separating a synchronization pulse from the reproduction signal and outputting a pulse signal corresponding to a pedestal period of the reproduction signal; and the sync separation circuit. A pulse signal corresponding to a pedestal period is input from the circuit switching means, and the pedestal level of the reproduced signal passing through the circuit switching means is detected and held, and the reproduced signal output from the delay circuit and the demodulation circuit are output from the demodulation circuit. pedestal level control means for controlling the pedestal levels of the intact reproduced signals to match each other, and detecting the peak levels of the video signals in the reproduced signal outputted from the delay circuit and the unchanged reproduced signal outputted from the demodulation circuit, respectively. a pair of peak level detection means, a pair of operational amplifiers, a resistance circuit connected between the output terminals of each of the operational amplifiers and supplying a balanced voltage of the same level to one input terminal of the amplifier, and each of the operational amplifiers. It has a differential amplifier that receives the output from the output terminal of the operational amplifier and detects the difference voltage thereof, and the peak level of the video signal detected by each of the peak level detection means is input to the other input terminal of each of the operational amplifiers. a peak level difference detecting means for inputting and outputting a peak level difference from the differential amplifier as an error voltage; and an image in a reproduced signal output from the delay circuit in response to the output level from the peak level difference detecting means. peak level correction means for correcting the peak level of the signal so as to match the peak level of the video signal in the reproduced signal directly output from the demodulation circuit and supplying the corrected signal to the circuit switching means; and a synchronization pulse from the synchronization separation circuit. sync chip level setting for setting the sync chip level of the reproduced signal output from the delay circuit passing through the circuit switching means and the reproduced signal output as is from the demodulation circuit to a preset fixed potential in response to the circuit switching means. What is claimed is: 1. A television composite video signal waveform processing device, comprising means for obtaining a television composite video signal for image display.