JPS6182589A - Waveform processor of television composite video signal - Google Patents

Abstract

PURPOSE:To obtain a sharp picture without flickering in terms of an electronic still camera by setting and controlling securely pedestal levels of a reproduction signal which has been delayed and that which has not to a normal level when a composite video signal is read out from a disk memory. CONSTITUTION:In terms of a differential amplifier 30, the peak level of a video signal in a reproduction signal which is not delayed is compared with that of a delayed reproduction signal, and according to the difference and error voltage is outputted. As a result, a balance modulation circuit 26 processes an inputted reproduction signal with gains in accordance with the error voltage obtained through the comparison. An adder 27 overlaps the output of the balance modulation circuit 26 with the delayed reproduction signal. The reproduction signal, which is level-corrected and outputted from the adder 27, is corrected in terms of peak level of its video signal so as to coincide with te peak level of the video signal in the reproduction signal which is not delayed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a television composite video signal waveform processing device used, for example, when reading a composite video signal from a disk memory in an electronic still camera and displaying it on a television.

[Prior Art j The standard television system uses 1/2 interlaced scanning. For example, in the NTSC system, one field has 262.58 horizontal scanning lines (one day is one horizontal opening period), and one frame = 2 fields, which is 525H. Therefore, when reproducing a rotating disk of an electronic still camera on which 1 field = 262.5H is recorded per revolution, the horizontal synchronization at the recording joint (starting point or ending point) is 0.58, that is, 1 horizontal synchronization period. ,−'
This results in a deviation of 2, which causes distortion on the screen of a normal television receiver, making normal display impossible. For this reason, it is necessary to generate a continuous horizontally synchronized reproduction signal from the recording joint by passing the reproduction signal from the disk through a 0.5H delay circuit every other field repetition period. That is, the sixth
(a) in the figure shows the playback signal from the disc,
This is repeated for 0.5H every other field every cycle.
By delaying it, it is necessary to create a reproduced signal as shown in FIG. 6(b). Note that in the figure, Vs is a vertical synchronization signal, and H8 is a horizontal synchronization signal, and in this case, both signals are delayed every other signal.

However, if a level difference occurs between the 0.5H delayed reproduction signal and the undelayed reproduction signal, it will appear on the Ue@iso screen as a change in brightness at the field frequency, causing the screen to flicker.

Therefore, it is necessary to match the pedestal level of the delayed reproduction signal with the pedestal level of the undelayed reproduction signal. Conventional circuits that have achieved this are:
The one shown in FIG. 7 is known. That is, this circuit supplies the reproduction signal read from the disk by the head 1 to the demodulation circuit 4 via the amplifier 2 and the bypass filter 3, and supplies the reproduction signal output from the demodulation circuit 4 to the 0.5H delay circuit 5. At the same time, the emitter is connected to the power supply terminal via the resistor R6 via the capacitor C1.
It is supplied to the base of the NP type transistor Tr1. 0.58il with the delay circuit 5! The extended reproduced signal is passed through a level correction circuit 8 consisting of a balanced modulation circuit 6 and an adder 7, and further via a capacitor C2, and then the emitter is connected to a resistor R7.
The voltage is supplied to the base of a PNP transistor Tr2 connected to the power supply terminal through the power supply terminal. Note that the collectors of both the transistors Trl and Tr2 are grounded, forming an emitter follower circuit. Both the transistors 7rl, T
The sink chip level of the reproduced signal output to the emitter of r2 is set by diodes D1, D2, capacitors C3, C4,
The signal is detected by a sink tip level detection circuit 9.10 consisting of resistors Rt and R2, and is supplied to the differential amplifier 11. The differential amplifier 11 detects the difference between the sync tip level of the undelayed reproduction signal and the sync tip level of the delayed reproduction signal, and supplies the difference to the balanced modulation circuit 6 as an error voltage. The balanced modulation circuit 6 outputs a signal with a gain corresponding to the level of the error voltage, and the adder 7 outputs a delayed reproduction signal whose level has been corrected to match the level of the undelayed reproduction signal. . Then, an undelayed reproduction signal and a delayed reproduction signal are alternately taken out from the emitters of the transistors 7r1 and 7r2 through an analog switch 12 that alternately switches their contacts at each field repetition period, and are supplied to an output amplifier 13. There is. Further, a synchronous separation circuit 14 is provided between the analog switch 12 and the output amplifier 13, and a pulse generated only during the pedestal period of the reproduced signal is output from the synchronous separation circuit 14, and the pulse turns on the switch 15 during the pedestal period. This causes the capacitor C5 to maintain the pedestal level of the reproduced signal. This capacitor C
The pedestal level held at 5 is supplied to the pedestal clamp circuit 16, and the pedestal clamp circuit 16
The outputs are supplied to the bases of the transistors Trl and Tr2 via resistors R3 and R4, respectively, so that the pedestal level of the undelayed reproduction signal and the pedestal level of the delayed reproduction signal are made to match.

[Problems to be solved by the invention] In such a conventional circuit, both transistors Tri and Tr2
is always in operation, so that no matter which way the analog switch 12 is switched, both the delayed and undelayed reproduction signals will be pedestally clamped by the output from the pedestal clamp circuit 16.

That is, the pedestal level of the other reproduction signal that does not pass through the analog switch 12 is clamped by the pedestal level of the reproduction signal that has passed through the analog switch 12. On the other hand, there is no problem if the pedestal levels at the emitters of both transistors Trl and Tr2 are the same level, but in reality, capacitors C3 and 04
, the difference in DC level at Cs, both transistors Trl,
The pedestal level of the delayed reproduction signal and the non-delayed reproduction signal will be different due to a difference in VBE of Tr2 or a difference in internal resistance of each switching circuit of the analog switch 12. For this reason, the pedestal clamp circuit 34
I am trying to correct it. The pedestal level of the delayed playback signal is actually lower than the normal level, so it is raised to the normal level by a pedestal clamp circuit, and the pedestal level of the undelayed playback signal is almost the normal level, so the pedestal clamp is used. No correction is made in the circuit.

For this reason, for example, when the delayed playback signal Sl passes through the analog switch 12 and the pedestal level is set as shown in FIG. If the pedestal level of the reproduced signal Sr' that is at the same level but is not delayed becomes higher than the normal level, and conversely, the undelayed reproduced signal 82' passes through the analog switch 12 and the pedestal level is set, the correction Since this is not performed, there is a problem in that the pedestal level of the delayed reproduced signal S2 is lower than the normal level. When such a problem occurs, a level difference occurs between the delayed video signal and the non-delayed video signal, and this level difference appears as a change in brightness on the screen between images, causing so-called flicker.

This invention was devised to solve such problems, and provides a television composite video in which the pedestal level of a delayed playback signal and the pedestal level of an undelayed playback signal can always be made to match at a normal level. The purpose of the present invention is to provide a signal waveform processing device.

[Means for Solving the Problems] The present invention retrieves a composite video signal for displaying one frame of image using a 1/2 interlaced scanning method from a video signal storage medium that stores it as a one-field repeated playback signal. a demodulation circuit that outputs a reproduced signal, and a demodulation circuit that delays the reproduced signal from this demodulation circuit by 1/2 time of the horizontal synchronization period.
, a 58 delay circuit, a circuit switching means for alternately passing the reproduced signal outputted from the delay circuit and the reproduced signal output as it is outputted from the demodulation circuit alternately at each field repetition period, and separating the synchronization pulse from the reproduced signal. A synchronous separation circuit outputs a pulse signal corresponding to the pedestal period of the reproduced signal, and a pedestal level of the reproduced signal passing through circuit switching means is adjusted in response to the pulse signal corresponding to the pedestal period from the synchronous separation circuit. a pedestal level control means that detects and holds the pedestal level of the reproduced signal outputted from the delay circuit and controls the pedestal level of the reproduced signal outputted as it is from the demodulation circuit to be constant; and output from the delay circuit. a pair of peak level detection means for detecting the peak level of the video signal in the reproduced signal to be reproduced and the reproduction signal as it is outputted from the demodulation circuit, respectively; a peak level difference detection means for detecting the difference and outputting it as an error voltage; and a peak level of the video signal in the reproduced signal output from the delay circuit in response to the output level from the peak level difference detection means. peak level correction means for correcting the reproduced signal outputted from the demodulation circuit as it is to match the peak level of the video signal and supplying the corrected signal to the circuit switching means; and a passing circuit switching operation for the delayed reproduction signal by the circuit switching means. In response to this, the pedestal level control means detects the pedestal level of the delayed reproduction signal, and one of the peak level detection means detects the peak level of the video signal in the delayed reproduction signal, and the circuit switching means In response to the passage circuit switching operation of the undelayed reproduction signal, the pedestal level control means detects the pedestal level of the undelayed reproduction signal, and the other peak level detection means produces a video signal in the undelayed reproduction signal. A level detection control means for performing peak level detection is provided, and a television composite video signal for image display is provided.

[Operation 1] By having the above-described configuration, the present invention can control the pedestal level setting of the delayed reproduction signal when the pedestal level of the delayed reproduction signal is detected by the pedestal level control means via the circuit switching means. Only the peak level detection of the video signal in the playback signal is performed, and the pedestal level setting control of the playback signal that is not delayed and the peak level detection of the video signal in the playback signal are prohibited, and the playback signal that is not delayed is prohibited. When the pedestal level is detected by the pedestal level controlling means via the circuit switching means, only the pedestal level setting control of the playback signal that is not delayed and the peak level detection of the video signal in the playback signal are performed and the delay is delayed. The pedestal level setting control of the reproduced signal and the detection of the peak level of the video signal in the reproduced signal are prohibited.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

Reference numeral 21 denotes a head, and this head 21 receives data from a disk, which is a video signal storage medium, which stores a composite video signal for displaying one frame of image in a 1, -' 2 interlaced scanning method as one field of repeated playback signal. The playback signal is read out.

The reproduced signal read by this head 21 is passed through an amplifier 22 and a bypass filter 23 to I! 314 circuit 24. The demodulation circuit 24 has the function of outputting a reproduction signal and a synchronization signal, and supplies the reproduction signal to a 0, 5H delay circuit 25 composed of a charge-coupled device such as a COD element, and also to an emitter follower via a capacitor C1. It is supplied to the base of the PNP transistor Tr1 that constitutes the circuit. Note that the synchronization signal is supplied to a synchronization separation circuit (not shown) and is synchronously separated.

The delay circuit 25 delays the input playback signal by 1/2 time of the horizontal synchronization period, and sends the delayed playback signal to the input terminal I of the balanced modulation circuit 26 and the adder 27, which constitutes peak level correction means. supplying. The balanced modulation circuit 26 inputs to its input terminal B a reference voltage obtained by a voltage dividing circuit of resistors R1 and R2, and also inputs to its input terminal C an error voltage from a peak level difference detection means to be described later. It processes the input reproduced signal with a gain of 1 depending on the magnitude of the voltage, outputs a positive or negative polarity signal from output terminal 0, and supplies the signal to the adder 27. The adder 27 superimposes the signal from the balanced modulation circuit 26 on the reproduction signal from the delay circuit 25 to perform level correction, and configures an emitter follower circuit by passing the level-corrected delayed reproduction signal through a capacitor C2. It is supplied to the base of the PNP transistor Tr2. The collector of the transistor Trl is grounded, and its emitter is connected to one fixed contact 281 of the analog switch 28 constituting the circuit switching means, and also connected to the diode D1.
is connected in the forward direction, and further connected to the other end of a parallel circuit of a resistor R4 and a capacitor C3, one end of which is grounded, and the base of an emitter follower NPN transistor Tr3 via a resistor R3. The collector of the transistor Tr2 is grounded, and the emitter thereof is connected to the other fixed contact 282 of the analog switch 28, through a diode D2 in the forward direction, and further through a resistor R5, which has one end grounded. and the other end of the parallel circuit with the capacitor C4 and the base of the emitter follower NPN transistor Tr4. The diode D
1. A circuit consisting of a parallel circuit of resistor R3, resistor R4 and capacitor C3, and transistor Tr3 constitutes a peak level detection means for detecting the peak level of the video signal in the undelayed reproduced signal, and also includes a diode D2, resistor Rs, A circuit consisting of a parallel circuit of resistor R6 and capacitor C4 and transistor Tr4 constitutes peak level detection means for detecting the peak level of the video signal in the delayed reproduction signal. Each of the transistors Tr3, T
The collector of r4 is connected to the + power supply terminal, and the emitter is grounded via a resistor. In this circuit, if the capacitances of the capacitors C3 and C4 are made relatively large, even if the peak level of the video signal has a waveform, the average value of the peak levels can be detected as the peak level. The emitter output of the transistor Tr3 is passed through two voltage follower operational amplifiers to one input terminal (
+).

Further, the emitter output of the transistor Tr4 is supplied to the other input terminal (-) of the differential amplifier 30. The differential amplifier 30 includes transistors Tr3 and Tr4.
Detecting the level difference by inputting the peak level of the undelayed video signal and the peak level of the M-stretched video signal inputted through the M, and outputting the difference as an error voltage;
Input terminal Ct of the balanced modulation circuit 26 via a resistor:
supplying.

The common contact 283 of the analog switch 28 has one end connected to +
It is connected to the other end of the load resistor 7 connected to the N power supply terminal, and also to the base of the NPN transistor l'-rf3. The transistors Tri, Tr2, and load resistor R7 constitute level detection control means. The transistor Tr6 has its collector connected to the + power supply terminal, its emitter grounded via the resistor R15, grounded via the switch 31 and the capacitor C5 in series, and connected to the input terminal of the synchronous separation circuit 32. It is connected to the input terminal of the output amplifier 33 via resistors Re and R9 in series. The synchronization separation circuit 32 outputs a pulse generated only during the pedestal period of the reproduced signal and a synchronization pulse, and the pulse generated during the pedestal period is used to control the switch 3.
1 is turned on during the pedestal period, and a synchronizing pulse is supplied to the base of the NPN transistor Tr5 constituting the sync tip level setting means. The voltage across the terminals of the capacitor C5 is supplied to the input terminal of the pedestal clamp circuit 34. This pedestal clamp circuit 34
The output of the transistor Tr2 is supplied to the base of the transistor TN via a resistor R10, and is also supplied to the base of the transistor Tr2 via a resistor R41.

The resistors R10 and R11, the switch 31, and the capacitor C
s, the pedestal clamp circuit 34 constitutes a pedestal level control circuit. The emitter of the transistor 7r5 is grounded via a capacitor Cs, and
Variable resistor VR in a series voltage divider circuit of resistor R12, variable resistor VR1, and resistor R13 connected between the power supply terminal and ground
is connected to the variable terminal of The transistor Tr5
The collector of is connected to the connection point between the resistors Re and R9. Note that a resistor R14 is connected between the base and emitter of the transistor Tr5.

In the apparatus according to the embodiment of the present invention configured as described above, the reproduced signal read from the disk by the head 21 is outputted via the amplifier 22, the bypass filter 23, and the demodulation circuit 24. The reproduced signal from the demodulation circuit 24 is delayed by a delay circuit 25 by 1/2 time of the horizontal synchronization period, that is, 0.5H. This delayed reproduction signal is supplied to a balanced modulation circuit 26 and an adder 27. Then, the output from the balanced modulation circuit 27 is superimposed on the reproduced signal delayed by the adder 27 as it is, the level is corrected, and the level-corrected reproduced signal is supplied to the base of the transistor Tr2 via the capacitor C2. .

On the other hand, the undelayed reproduced signal outputted from the demodulation circuit 24 is supplied to the base of the 1-transistor Trl via the capacitor C1. Now, the analog switch 28 connects its common contact 283 to one fixed contact 28.
1, the emitter of the transistor Tr1 is connected to the power supply terminal via the analog switch 28 and the load resistor R7, so that an undelayed reproduction signal is output to the emitter of the transistor Tr1. On the other hand, the emitter of the transistor Tr2 is never connected to the power supply terminal, so it does not operate. Thus, the peak level of the video signal in the reproduced signal output to the transistor Tr1 is detected by a peak level detection means comprising a diode Dr, a resistor R3, a resistor R4, a capacitor C3, and a transistor Tr3. Further, only the pedestal level of the reproduced signal that is not delayed is detected by the pedestal level control means. Therefore, at this time, as shown in FIG. 2, only the non-delayed reproduced signal @Sl whose pedestal level is set to the normal level is output to the peak level detection means.

Further, if the analog switch 28 connects its common contact 283 to the other fixed contact 282, the transistor Tr
2 emitter is analog switch 28 and load resistor R7
The delayed reproduction signal is output to the emitter of the transistor Tr2. On the other hand, the emitter of the transistor Tr1 is never connected to the power supply terminal, so it does not operate. Therefore, the peak level of the video signal in the reproduced signal output to the transistor Tr2 is determined by the diode D2 and the resistor Rs.
, resistor R6, capacitor C4 and transistor Tr4
The peak level is detected by a peak level detection means consisting of: Further, only the pedestal level of the delayed reproduction signal is detected by the pedestal level control means. Therefore, at this time, only the delayed reproduction signal S2 whose pedestal level is set to the normal level is output to the peak level detection means as shown in FIG. Therefore, when the analog switch 28 connects its common contact 283 to one of the fixed contacts 281, only the reproduction signal that is not delayed is controlled to set its pedestal level, and its peak level is detected by the peak level detection means. On the other hand, when the analog switch 28 connects its common contact 283 to the other fixed contact 282, only the delayed reproduction signal is controlled to set its pedestal level, and the peak level detection means controls its pedestal level. The peak level will be detected.

In this way, each peak level detecting means detects the peak level of both the undelayed reproduced signal and the delayed reproduced signal with their pedestal levels controlled to normal levels. . The peak level signal detected by one peak level detection means is supplied to one input terminal (+) of the differential amplifier 30 via the operational amplifier 29, and the peak level signal detected by the other peak level detection means is supplied to one input terminal (+) of the differential amplifier 30 via the operational amplifier 29. A level signal is supplied to the other input terminal (-) of the differential amplifier 3o. Then, in the differential amplifier 30, the peak level of the video signal in the undelayed reproduction signal and the peak level of the video signal in the delayed reproduction signal are compared, and an error voltage corresponding to the difference is output. Therefore, the balanced modulation circuit 26 compares the peak level of the video signal in the undelayed reproduced signal with the peak level of the video signal in the delayed reproduced signal, and outputs the input reproduced signal with a gain corresponding to the error voltage iq. It will be processed. Therefore, the level-corrected playback signal output from the adder 27 that superimposes the output of the balanced modulation circuit 26 on the delayed playback signal as it is is the peak level of the video signal in the undelayed playback signal. It will be corrected to match the level.

Further, the transistor Tr5 is turned on by the synchronization pulse from the synchronization separation circuit 32, and as a result, the voltage set by the variable resistor VR and held in the capacitor C6 appears at the connection point between the resistors R6 and R9. This voltage is set to a level that sets the sync tip level of the reproduced signal, and thereby the sync tip levels of the undelayed reproduced signal and the delayed reproduced signal are fixed at the set level.

Therefore, the reproduced signal finally output from the output amplifier R33 is a signal in which the undelayed signal and the delayed signal have the same three levels: the peak level, the pedestal level, and the sync tip level of the video signal.

In this way, the pedestal levels of the undelayed playback signal and the delayed playback signal are reliably set to the normal level, and the peak levels of the video signals in both playback signals can also be made to match, thereby eliminating flickering in brightness and darkness. It is possible to obtain a composite video signal that provides a clear screen without any blemishes.

Next, another embodiment of the invention will be described with reference to the drawings.

In this embodiment, only essential parts are shown, and the same parts as those in the previous embodiment are denoted by the same reference numerals, and detailed explanation will be omitted.

First, what is shown in FIG. 3 is the transistor Tr1,
NPN transistors Tr7 and Tr8 in place of Tr2
The collectors of the transistors Tr7 and Tr8 are connected to the power supply terminal, and the emitters are connected to the fixed contacts 281 and 282 of the analog switch 28, respectively, and the common contact 283 of the analog switch 28 is connected to the collectors of the transistors Tr7 and Tr8.
is grounded via a load resistor R16.

In this case, the polarity of the transistors Tr7 and Tr8 is opposite to that of the above-mentioned embodiment, but even in this case, the transistors Tr7 and Tr8 only operate when the analog switch 28 is switched to the fixed contacts 28* and 282, respectively. In this case as well, the same effects as in the above embodiment can be obtained.

In addition, the transistors Tr1 and Tr2 shown in FIG.
In this case, the diodes D3 and D4 operate only when the analog switch 28 is switched to the fixed contact 281° and 282, respectively. Similar effects can be obtained.

Furthermore, the transistors Tr1 and Tr2 shown in FIG.
A resistive voltage divider circuit 35 consisting of resistors R17 and R18 instead of
In this case, each resistor voltage divider circuit 35.36 has an analog switch 28 connected to a fixed contact 281.28.
Since the partial pressure level is determined only when switching to iq
It is something that can be done.

[Effects of the Invention] As detailed above, according to the present invention, there is provided a television composite video signal in which the pedestal level in the delayed reproduction signal and the pedestal level in the non-delayed reproduction signal can always be made equal to the regular level. A waveform processing device can be provided.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram showing the output of a delayed reproduction signal and an undelayed reproduction signal to the peak level detection means in the same embodiment, and FIG. 3 ~ Figure 5 is a circuit diagram of a main part showing another embodiment of the present invention, and Figure 6 is a delay control of a reproduced signal by a delay circuit.
FIG. 7 is a circuit block diagram showing a conventional example.
FIG. 8 is a waveform diagram showing the output of a delayed reproduction signal and a non-delayed reproduction signal to a sync chip level detection circuit in the related art. 21...Head, 24...Demodulation circuit, 25...0
．． 5HM extension circuit, 26... Balanced modulation circuit, 27...
Adder, 28...Analog switch, 30...Differential amplifier, 31...Switch, 32...Synchronization separation circuit, 34...Pedestal clamp circuit, DI, C2,
C3, C4...Diode, R3, R4, Rs SR
s, R7, R10, R11, R16...Resistance, C3
, C4, Cs... Capacitor, Tri, Tr2.7'
r3, Tr4, Tr7, Tr8...transistors. ! Applicant's agent Patent attorney Takehiko Suzue ■ Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (4)

[Claims] (1) A demodulation circuit that outputs the playback signal taken out from a video signal storage medium that stores a composite video signal for displaying one frame of image in a 1/2 interlace scanning method as a one-field repeat playback signal; , which delays the reproduced signal from this demodulation circuit by 1/2 time of the horizontal synchronization period.
．． a 5H delay circuit; circuit switching means for alternately passing the reproduced signal outputted from the delay circuit and the reproduced signal outputted from the demodulation circuit as-is at each field repetition period; and separating a synchronization pulse from the reproduced signal. a synchronous separation circuit that outputs a pulse signal corresponding to the pedestal period of the reproduced signal; and a pedestal of the reproduced signal that responds to the pulse signal corresponding to the pedestal period from the synchronous separation circuit and passes through the circuit switching means. pedestal level control means that detects and holds the level and performs control so that the pedestal level of the reproduced signal output from the delay circuit and the pedestal level of the intact reproduced signal output from the demodulation circuit are constant; a pair of peak level detection means for detecting the peak levels of video signals in the playback signal outputted from the delay circuit and the playback signal output as is from the demodulation circuit, respectively; and the video detected by the respective peak level detection means. peak level difference detection means for comparing the peak levels of the signals, detecting the difference and outputting it as an error voltage; and a reproduction signal output from the delay circuit in response to the output level from the peak level difference detection means. peak level correction means for correcting the peak level of the video signal so as to match the peak level of the video signal in the reproduced signal directly output from the demodulation circuit and supplying the corrected signal to the circuit switching means; In response to the passage circuit switching operation of the reproduced signal, the pedestal level control means detects the pedestal level of the delayed reproduced signal, and the peak level detection means detects the peak level of the video signal in the delayed reproduced signal. In response to the passage circuit switching operation of the undelayed reproduction signal by the circuit switching means, the pedestal level control means detects the pedestal level of the undelayed reproduction signal and detects the other peak. and level detection control means for causing the level detection means to detect the peak level of the video signal in the undelayed reproduced signal, thereby obtaining a television composite video signal for image display. Processing equipment. (2) The level detection control means constitutes an emitter follower circuit, and includes a pair of transistors to which the output from the pedestal level control means is inputted to the base, and a common connection between each transistor through each switching circuit of the circuit switching means. and a load resistor connected to the load resistor, and only the transistor electrically connected to the load resistor operates to output a signal to the corresponding peak level detection means. TV complex video signal waveform processing device. (3) The level detection control means includes a pair of diodes to which the output from the pedestal level control means is applied to the cathodes, and a load resistor commonly connected to each of the diodes through each switching circuit of the circuit switching means. The television composite video signal waveform according to claim 1, characterized in that only the diode whose load resistance is electrically connected operates to output a signal to the corresponding peak level detection means. Processing equipment. (4) The level detection control means includes a pair of resistor voltage divider circuits to which the output from the pedestal level control means is applied to one end and the other end is grounded, and circuit switching means at the voltage division point of each resistor voltage divider circuit. It consists of a load resistor, one end of which is connected to the positive terminal, which is commonly connected through each of the switching circuits, and a signal is sent to the corresponding peak level detection means from the resistor voltage divider circuit to which the load resistor is electrically connected. 2. The television composite video signal waveform processing device according to claim 1, wherein the television composite video signal waveform processing device outputs the following: