JPH09238273A - Multi-scanning system crt display device and its synchronizing signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To width a range of a pulse width of a synchronizing signal with which the multi-scanning system CRT display device copes. SOLUTION: A capacitor 14 is used to cut off a DC component of a synchronizing signal, a circuit consisting of resistors 16-18 and diodes 19, 20 slices a voltage level and provides a DC bias so as to increase a change in an average voltage with respect to a change in the duty factor. A synchronizing signal polarity discrimination circuit 12 discriminates the polarity based on the average voltage so as to widen a range of the pulse width whose polarity is able to be discriminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-scan type CRT display device, and more particularly to a multi-scan type CRT display device capable of expanding the range of sync signals capable of discriminating polarities and corresponding to various kinds of sync signals. The present invention relates to a synchronization signal processing circuit.

[0002]

2. Description of the Related Art In recent years, the mainstream of computer systems has a plurality of deflection frequencies, such as starting at a low frequency of about 30 kHz at startup and switching to a high horizontal deflection frequency of about 100 kHz at application startup. As the CRT display device connected to the above system, a so-called multi-scan CRT display device which is synchronized with a plurality of deflection frequencies has become mainstream. Along with this, there are various types of system synchronization signals, and it is required to support various pulse widths and polarities.

On the other hand, the CRT display device is provided with a sync signal processing circuit for correcting the distortion of the input sync signal, and the sync signal processing circuit reproduces the sync signal. In generating the synchronization signal, it is necessary to set the polarity of the reproduction output of the synchronization signal to either the positive polarity or the negative polarity regardless of the polarity of the input synchronization signal.

FIG. 6 is a block diagram of a conventional synchronizing signal processing circuit. In this conventional sync signal processing circuit, the DC component of the incoming sync signal is cut off by the capacitor 1, and the voltage level of the signal that has passed through this capacitor 1 is composed of diodes 3-5 and resistors 6, 7. The circuit is used to clamp at two different potentials and DC bias. The clamped and DC biased signal is input to the non-inverted sync signal regenerator 10 and the inverted sync signal regenerator 11.
The non-inverted sync signal regenerator 10 reproduces the signal without inverting the polarity, and the inverted sync signal regenerator 11 inverts the polarity to reproduce.

The voltage of the clamped and DC-biased signal is also averaged by the integrating circuit composed of the resistor 8 and the capacitor 9, and this average voltage is input to the polarity discriminator 12. The polarity discriminator 12 controls the switching operation of the output selector switch 13 by this average voltage and outputs either the inverted and reproduced sync signal or the non-inverted reproduced sync signal.

FIG. 7 is a diagram showing the switching operation of the polarity discriminator 12 and the relationship between the duty ratio of the synchronizing signal and the average voltage. When the input voltage of the polarity discriminator 12 is equal to or higher than VH, a control signal for selecting the output C (non-inverted output) is output to the switch 13, whereby the synchronization signal whose polarity is not inverted is output from the switch 13. When the input voltage is equal to or lower than VL, a control signal for selecting the output A (inverted output) is output to the switch 13, and the synchronization signal whose polarity is inverted is output from the switch 13. When the input voltage is located between VH and VL, that is, when the polarity of the synchronizing signal is unknown, a control signal for selecting the output B is output to the switch 13, and the green composite signal is output from the switch 13. To be done.

Incidentally, as one related to the synchronizing signal processing circuit using the integrating circuit, for example, Japanese Patent Laid-Open No. 63-278094.
There is an official gazette.

[0008]

In the conventional circuit shown in FIG. 6, since the synchronizing signal is reproduced, the voltage amplitude of the input signal becomes small. Therefore, the change of the average voltage with respect to the change of the pulse width of the synchronizing signal becomes small.
Further, due to the temperature characteristic of the diode that clamps the voltage level, the difference between the upper limit VH and the lower limit VL of the clamp voltage is reduced, and the voltage amplitude of the signal is further reduced. As a result, the relationship between the pulse width of the synchronization signal and the average voltage is as shown in FIG. 7, and there is a problem that the range in which the polarity cannot be determined is wide (the range in which the polarity can be determined is narrow). For this reason, the conventional CRT display device can only cope with a synchronizing signal having a pulse width duty ratio of about 10% and cannot deal with a synchronizing signal having a pulse width larger than that.

It is an object of the present invention to provide a multi-scan CRT display device having a wide range of pulse widths of sync signals (corresponding range of duty ratios of sync signals) and a sync signal processing circuit thereof. is there.

[0010]

SUMMARY OF THE INVENTION The above-mentioned object is to obtain the input from the relationship between the duty ratio of the synchronizing signal and the integrated voltage of the synchronizing signal and the integrated voltage obtained by integrating the incoming synchronizing signal. CRT that determines the polarity of the incoming sync signal and reproduces and uses the sync signal based on the result of the decision
This is achieved by providing the display device with a circuit that increases the amount of change in the integrated voltage with respect to the amount of change in the duty ratio of the input synchronizing signal.

By increasing the amount of change in the integrated voltage with respect to the amount of change in the duty ratio, the range in which the polarity of the sync signal can be discriminated is widened, and it becomes possible to deal with various kinds of sync signals.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 5 is a block diagram of a CRT display device according to an exemplary embodiment of the present invention. The CRT display device includes a CRT 30, a video amplifier circuit 31,
The vertical output circuit 32, the horizontal output circuit 33, the high voltage rectification circuit 34, the vertical oscillation amplification circuit 35, the horizontal oscillation amplification circuit 36, the synchronizing signal processing circuit 37, and the power supply 38 are provided.
The synchronization signal processing circuit 37 takes in the synchronization signal, reproduces the synchronization signal in which the distortion of the synchronization signal is corrected, and outputs the negative synchronization signal to the vertical oscillation amplification circuit 35 and the horizontal oscillation amplification circuit 36 in the present embodiment. To do.

FIG. 1 is a detailed configuration diagram of the synchronization signal processing circuit. The synchronization signal processing circuit according to the present embodiment is configured by adding an external circuit to the conventional synchronization signal processing circuit shown in FIG. 6 (usually a portion other than a capacitor is integrated into one chip IC). However, the entire circuit shown in FIG. 1 (excluding the capacitor) can be integrated into one chip IC.

The external circuit comprises a capacitor 14 connected to the input end of the synchronizing signal, a resistor 15 connecting the connection point between the resistors 8 and 9 and the capacitor 14, and a voltage Vcc.
Resistor 16,17,1 directly connected between the
8, the connection point between the resistors 16 and 17 and the capacitor 14
A diode 19 that connects between the connection point of the resistor 15 and the resistor 15 in the reverse direction, and a diode 20 that connects between the connection point of the resistor 17 and the resistor 18 and the connection point of the capacitor 14 and the resistor 15 in the forward direction. Composed of and.

The capacitor 14 slices the voltage amplitude of the DC component of the synchronizing signal, and the synchronizing signal that has passed through the capacitor 14 has resistors 16, 17, 18 and diodes 19, 20.
The voltage amplitude is clamped and the resistance 1
The voltage is integrated and averaged by the RC filter composed of 5 and the capacitor 9. This average voltage is input to the polarity discriminator 12. Therefore, the capacitor of the two RC filters including the capacitor 9 and the resistor 8 and the capacitor 9 and the resistor 15 are shared. This makes it possible to arbitrarily set the rate of change of the average voltage with respect to the amount of change of the duty ratio of the synchronization signal.

The polarity discriminator 12 discriminates that the polarity of the synchronizing signal is positive when the input voltage is VL or less, and selects the output A of the inversion regenerator 11. When the input voltage is equal to or higher than VH, the polarity of the sync signal is determined to be negative and the output C of the non-inverting regenerator 10 is selected. Input voltage is VH and VL
In the case of between, since the polarity is unknown, the green composite output B is selected. Incidentally, FIG. 2 shows the relationship between the synchronizing signal input and the synchronizing signal output. Since the waveform of the synchronization signal is rectangular, the average voltage is represented by average voltage = voltage amplitude × duty ratio + DC bias voltage (1), and the change amount of the integrated voltage with respect to the change amount of the duty ratio of the synchronization signal, that is, FIG. The slope of the graph is proportional to the voltage amplitude and the duty ratio.

In the conventional sync signal processing circuit of FIG. 6, the voltage amplitude level of the sync signal is reduced to the amplitude of the forward voltage of the diode for reproducing the sync signal, so that the duty ratio of the sync signal changes. The amount of change in the integrated voltage with respect to the amount is small. Also, the forward voltage of the diode decreases due to variations between components and temperature rise, so the signal amplitude tends to become smaller, and the change amount of the average voltage with respect to the change amount of the duty ratio of the synchronization signal is smaller. It will be as described above.

On the other hand, with the configuration shown in FIG. 1, it is possible to increase the amount of change of the average voltage with respect to the amount of change of the duty ratio as shown in FIG. Hereinafter, the reason will be described. The synchronizing signal from which the DC component is removed by the capacitor 14 is clamped to the voltage divided by the resistors 16, 17, and 18. The upper limit voltage of the clamp is set to Va + Vf and the lower limit is set to Vb−Vf (Va and Vb are
These are the voltage at the connection point of the resistors 16-17 and the voltage at the connection point of the resistors 17-18, respectively. Vf is the forward voltage value of the diodes 19 and 20). The clamped synchronization signal is integrated and averaged by the resistor 15 and the capacitor 9, and the average voltage is input to the polarity discriminator 12.

The voltage input to the polarity discriminator 12 is the output voltage of the RC filter (integration circuit) composed of the resistor 8 and the capacitor 9 and the output voltage of the RC filter (integration circuit) composed of the resistor 15 and the capacitor 9. It becomes the voltage which added the output voltage. As a result, as shown in FIG. 4, the amount of change in the average voltage with respect to the amount of change in the duty ratio of the synchronization signal becomes large, and the range in which the polarity can be determined becomes wide.

FIG. 3 is a diagram showing the relationship between the duty ratio of the synchronizing signal and the average voltage integrated and averaged by the resistor 15 and the capacitor 9. When the duty ratio is small,
As shown in (b), the synchronous signal whose direct current component is blocked is clamped at the potential of Vb-Vf, and the average voltage value becomes low. On the contrary, when the duty ratio is large, (c)
As shown in, the synchronization signal with the DC component cut off is Va +
It is clamped at the potential of Vf, and the average voltage value becomes high. Therefore, as shown in FIG. 4, the average voltage input to the polarity discriminator 12 is small when the duty ratio is small, large when the duty ratio is large, and the slope of the graph becomes large.
The distance between b becomes narrow. As a result, the duty ratio range in which the polarity can be discriminated is widened. Thereby, in the present embodiment,
It is possible to accurately cope with the input of a sync signal having a pulse width of 30 to 40%.

[0021]

According to the present invention, the multi-scan method C
In the RT display device, since the change amount of the polarity discrimination voltage with respect to the change of the pulse width of the sync signal is increased,
The range of sync signals that can be handled is widened.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a synchronization signal processing circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between inputs and outputs of the synchronization signal processing circuit shown in FIG.

FIG. 3 is a diagram showing a change in duty ratio of a synchronization signal and a change in integrated voltage.

FIG. 4 is a graph showing circuit characteristics of the synchronization signal processing circuit shown in FIG.

FIG. 5 is a schematic configuration diagram of a multi-scan CRT display device according to an embodiment of the present invention.

FIG. 6 is a configuration diagram of a conventional synchronization signal processing circuit.

7 is a graph showing circuit characteristics of the conventional synchronization signal processing circuit shown in FIG.

[Explanation of symbols]

1, 9, 14 ... Capacitors 2, 6, 7, 8, 15, 1
6, 17, 18 ... Resistor, 3, 4, 5, 19, 20 ... Diode, 10 ... Non-inverting sync signal regenerator, 11 ... Inverting sync signal regenerator, 12 ... Polarity discriminator, 13 ... Output changeover switch.

Claims (4)

[Claims] 1. The polarity of the input synchronizing signal is determined from the relationship between the duty ratio of the synchronizing signal and the integrated voltage of the synchronizing signal, and the integrated voltage obtained by integrating the input synchronizing signal. In a multi-scan CRT display device that reproduces and uses a synchronization signal based on the determination result,
A multi-scan CRT display device comprising a circuit for increasing a variation of an integrated voltage with respect to a variation of a duty ratio of an input synchronizing signal. 2. The polarity of the input synchronizing signal is determined from the relationship between the duty ratio of the synchronizing signal and the integrated voltage of the synchronizing signal, and the integrated voltage obtained by integrating the input synchronizing signal. In a sync signal processing circuit of a multi-scan CRT display device that reproduces a sync signal based on the determination result, a circuit that increases the amount of change in the integrated voltage with respect to the amount of change in the duty ratio of the input sync signal is provided. A synchronous signal processing circuit of a multi-scan CRT display device characterized by the above. 3. A capacitor for cutting off a direct current component of an input pulse-shaped synchronizing signal, and a first circuit for clamping a voltage amplitude of a pulse signal passing through the capacitor at two different potentials to perform a DC bias. A second circuit comprising: first means for reproducing a sync signal having a polarity opposite to that of the sync signal from the output signal of the circuit; and second means for reproducing a sync signal having the same polarity as the sync signal, and the first circuit. In the synchronization signal processing circuit, the filter circuit integrating and averaging the output signals of the second circuit and the switch circuit for selecting and outputting the first means output or the second means output of the second circuit according to the average voltage. Is installed on a route different from that for blocking the DC component of the input synchronizing signal, clamping the voltage amplitude of the signal with two different potentials, and then averaging the voltage. A synchronizing signal processing circuit for a multi-scan CRT display device, further comprising an additional circuit for inputting the average voltage to the switch circuit in addition to the average voltage output from the filter circuit. 4. A multi-scan CRT display device comprising the synchronization signal processing circuit according to claim 3.