JPH0818820A - Video signal output circuit - Google Patents

Abstract

PURPOSE:To realize a video signal output circuit in which a cutoff voltage of a cathode ray tube is adjusted without generating a sag due to a vertical frequency component of a video signal with a simple configuration with respect to the video signal output circuit outputting the video signal to the cathode ray tube. CONSTITUTION:A video amplifier 11 comprising a current source A40 and a resistive element R40 and a cathode ray tube 12 are DC-coupled and a DC level shift means 41 is provided to shift a DC voltage level of a video signal S1 by the DC voltage generated across the resistive element R40 in response to a DC current I0 of the current source A40 to easily shift the DC voltage level of the video signal S1 and the sag by the vertical frequency component of the video signal S1 is not produced and a cut-off voltage of the cathode ray tube 12 is easily adjusted.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. Industrial Application Conventional Technology (FIGS. 4 to 6) Problem to be Solved by the Invention (FIGS. 7 to 9) Means for Solving the Problem (FIGS. 1 to 3) Action (FIGS. 1 to 3) ) Example (1) First Example (FIGS. 1 and 2) (2) Second Example (FIG. 3) (3) Other Example Effects of the Invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal output circuit, and is particularly suitable for application to a video signal output to a cathode ray tube (CRT) such as an information processing device.

[0003]

2. Description of the Related Art Conventionally, in this type of CRT, the cut-off voltage is as high as about 100 to 120 [V], the R signal system,
There is a variation of about 20% between the G signal system and the B signal system. Therefore, in this CRT, a DC voltage (hereinafter referred to as DC offset voltage) is applied between the cathode of the CRT and the first grid together with the video signal amplified to several tens of [V], and the R signal system, G The cutoff voltage between the signal system and the B signal system is matched to obtain an appropriate image.

Here, in the home television device, as shown in FIG.
As shown in, when the video signal S1 is output to the CRT1, it is output via the cascode amplifier 2. This cascode amplifier 2 has a cascode-connected transistor Q ₁ ,
Becomes in emitter grounded amplifier formed by Q _2, it amplifies the video signal S1 input to the base of the transistor Q ₁ outputted from the collector of the transistor Q _2. At this time C
The video signal S2 output to RT1 is offset by the DC offset voltage. The video signal S2 is CRT1.
Is directly input to the cathode of.

In this case, since the frequency characteristic of the home television device is as low as 10 [MHz] or less, the load resistance R _L of the cascode amplifier 2 having a large resistance value can be used. Therefore, even if the power supply voltage V _CC is high, the power consumption of the load resistor R _L does not increase so much, and even if the DC offset voltage of the video signal S2 is changed when adjusting the cutoff voltage of the CRT1, the power consumption does not fluctuate. Relatively few.
Further, since the collector currents of the transistors Q ₁ and Q ₂ are small, high withstand voltage components can be used. In consideration of such a point, in the home television device, as a result, the video signal S2 is directly input to the cathode of the CRT1.

On the other hand, in the information processing apparatus, since the frequency characteristic of the CRT is as high as 30 [MHz] or higher, when outputting a video signal to the CRT, a video amplifier satisfying this frequency characteristic is required. When the output end of the video amplifier is configured by the cascode amplifier 2 as described above, the load resistance R _L must be reduced in order to obtain high frequency characteristics,
As the load resistance R _L , for example, a resistance value of several 100 [Ω] to 1 [KΩ] is used.

In this case, the CR connected to the information processing device
Since T does not require a very high luminance, the amplitude value of the video signal is as low as about 45 [V _PP ]. However, in the video amplifier, the breakdown voltage of the transistor used is low, and the power supply voltage is generally limited to 70 to 80 [V]. Further, in the video amplifier, since the load resistance R _L is small as described above, the power consumption increases, and it is difficult to secure a dynamic range in which the DC offset voltage of the video signal can be varied when adjusting the cutoff voltage of the CRT. . Therefore, in the information processing apparatus, a video output circuit capable of adjusting the cutoff voltage of the CRT is required between the video amplifier and the cathode of the CRT.

As such a video output circuit, there is a clamp circuit in which a video amplifier and a cathode of a CRT are capacitor-coupled and clamped to a predetermined voltage on the cathode side of the CRT. Although various circuits can be considered as the clamp circuit, the clamp circuit 10 as shown in FIG. 5 is the simplest. In this case, the clamp circuit 10 is inserted between the video amplifier 11 of the information processing device and the cathode of the CRT 12.

In the clamp circuit 10, the video amplifier 11 is connected to the cathode of the CRT 12 via the capacitor C ₁₀ , and the cathode of the CRT 12 is connected to the cutoff adjusting power source V _CO via the diode D ₁₀ . Further, in the clamp circuit 10, an adder circuit 13 is provided in the preceding stage of the video amplifier 11, and as shown in FIG. 6, a blanking pulse S10 is inserted in the horizontal blanking interval of the video signal S1. In this case, the clamp circuit 1
0 is diode-clamped at the distal end of the blanking pulse S10 inserted, by adding a DC offset voltage to the video signal component obtained through the capacitor C ₁₀ CRT 12
Output to the cathode of.

[0010]

However, this clamp circuit 10 has a problem that the pedestal level fluctuates unless the signal level of the blanking pulse S10 to be inserted is accurate. Therefore, the adder circuit 13 for inserting the blanking pulse S10 must be designed so as not to be affected by temperature characteristics and the like, and special design and difficulty are required in the design.

In addition to the clamp circuit 10, FIG.
As shown in, there is a clamp circuit 20 that clamps the video signal S1 without any modification. In this clamp circuit 20, the video amplifier 11 is connected to the cathode of the CRT 12 via a capacitor C ₂₀ , and the CRT 1 is connected.
The cathode of No. ₂ is connected to the cutoff adjustment power source V _CO via the diode D ₂₀ and the switch SW ₂₀ . In this case, the clamp circuit 20 switches the switch S in the back porch section of the horizontal synchronizing signal added to the video signal S1, as shown in FIG.
Diode clamped by turning on the W _20, capacitor C ₂₀
A DC offset voltage is added to the video signal component obtained via the output signal and output to the cathode of the CRT 12.

However, in the clamp circuit 20, it is an indispensable condition to avoid the portion of the horizontal synchronizing signal and perform the clamp in the back porch section, and there is a problem that the complete clamping cannot be performed at a short timing of the back porch section. Experiments have shown that a full-clamp requires a back pouch of approximately 1 μS at a horizontal frequency of 30 KHz. Although various clamp circuits 10 and 20 are conceivable as the video output circuit for adjusting the cutoff voltage of the CRT 12 in this way, even if either clamp circuit 10 or 20 is adopted, the video amplifier 11 and the cathode of the CRT 12 are connected. As long as the capacitors are coupled, it is difficult to avoid sag (waveform distortion due to low frequency components) due to the vertical frequency components of the video signal S1.

As a method for solving this, as shown in FIG. 9, there is a clamp circuit 30 for connecting the video amplifier 11 and the cathode of the CRT ₁₂ by using a variable Zener diode ZD ₃₀ . However, this clamp circuit 3
At 0, the variable voltage range by the variable Zener diode ZD ₃₀ is low, and the variable Zener diode ZD _{30 is connected} to a DC voltage (for example, 0 to 5) of a digital analog converter.
When controlled by [V], there is a problem that the control circuit becomes complicated and the cost becomes high.

The present invention has been made in consideration of the above points, and is a video signal output circuit capable of adjusting the cut-off voltage of the cathode ray tube with a simple structure without causing sag due to the vertical frequency component of the video signal. Is to propose.

[0015]

In order to solve such a problem, according to the present invention, in the video signal output circuit 40 (or 50) for outputting the video signal S1 amplified by the video amplifier 11 to the cathode ray tube 12, Current source A ₄₀ (or A
₅₀ ) and a resistance element R ₄₀ , which DC-couples the video amplifier 11 and the cathode ray tube 12 and generates a DC voltage in the resistance element R ₄₀ according to the DC current I ₀ of the current source A ₄₀ (or A ₅₀ ). Therefore, the DC level shift means 41 (or 51) for shifting the DC voltage level of the video signal S1 is provided.

In the present invention, the current source A ₄₀ (or A ₅₀ ) has one end connected to the resistance element R ₄₀ and the other end connected to a predetermined potential or ground potential.

In the present invention, the current control means R ₄₂ for changing the direct current I ₀ to the current source A ₄₀ (or A ₅₀ ).
(Or R ₅₂ ) is provided, and the DC current I ₀ is changed by the current control means R ₄₂ (or R ₅₂ ) to change the DC voltage generated in the resistance element R ₄₀ .

In the present invention, the resistance element R ₄₀ is
Video amplifier 11 and cathode of cathode ray tube 12 or first
The video signal S is connected in series with the grid and
The capacitor element C ₄₀ that bypasses the AC component of 1 is connected in parallel.

[0019]

A current source A ₄₀ (or A ₅₀ ) and a resistance element R _{40 are provided} , and the video amplifier 11 and the cathode ray tube 12 are DC-coupled,
Further, the DC level shift means 41 for shifting the DC voltage level of the video signal S1 by the DC voltage generated in the resistance element R ₄₀ according to the DC current I ₀ of the current source A ₄₀ (or A ₅₀ ).
By providing (or 51), the DC voltage level of the video signal S1 can be shifted without causing sag due to the vertical frequency component of the video signal.

Further, the current source A ₄₀ (or A ₅₀ ) is provided with a current control means R ₄₂ (or R ₅₂ ) for changing the direct current I _0, and the current control means R ₄₂ (or R ₅₂ ) is used for the direct current I ₀
By changing the DC voltage generated in the resistance element R ₄₀ , the offset amount of the DC voltage level of the video signal S1 can be easily adjusted.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

(1) First Embodiment In FIG. 1 in which parts corresponding to those in FIG. 4 are designated by the same reference numerals, 40 denotes a video output circuit as a video signal output circuit as a whole, and a resistor R ₄₀ and a variable current. It is constituted by a DC level shift circuit 41 consisting of a source A ₄₀ . In this case, the DC level shift circuit 41 connects the video amplifier 11 and the CRT 12 so as to be DC-coupled, and
The DC voltage level of the video signal S1 supplied to the circuit is shifted. Here, the resistor R ₄₀ of the DC level shift circuit 41 is connected in series between the video amplifier 11 and the cathode of the CRT 12. A capacitor C ₄₀ is connected in parallel to the resistor R ₄₀ , and bypasses the AC component of the video signal S1 output from the video amplifier 11. As a result, the deterioration of the frequency characteristic caused by the insertion of the resistor R ₄₀ is improved.

On the other hand, the variable current source A ₄₀ has its input side connected to the power supply voltage V _CC2 and its output side connected to one end of the resistor R ₄₀ (ie, the cathode side of the CRT 12). in this case,
Variable current source A ₄₀ of the DC current I ₀ DC voltage by connexion resistor R ₄₀ in (= resistor R ₄₀ × DC current I ₀₎ is generated, the DC voltage as a DC offset voltage, is output from the video amplifier 11 It is added to the video signal S1. Ie CR
At the cathode of T12, the DC offset voltage is
The video signal S1 whose DC voltage level is level up is input. In this case, since the DC voltage level of the video signal S1 is in the level-up direction, it is possible to adjust the pedestal level of the CRT 12 in the level-up direction as a result.

When the DC current I ₀ of the variable current source A ₄₀ is changed, only the DC voltage generated in the resistor R ₄₀ changes,
Amplified video signal S output from the video amplifier 11
1 does not change. That is, the direct current I of the variable current source A ₄₀
By changing ₀ , only the DC offset voltage can be changed.

Here, as shown in FIG. 2, the variable current source A ₄₀
Is constructed using a PNP type transistor Q ₄₀ . The emitter of the transistor Q ₄₀ is connected to the power supply voltage V _CC2 via the resistor R _41, and the collector of the transistor Q ₄₀ is connected to one end of the resistor R ₄₀ (cathode side of the CRT 12). Further, a DC voltage obtained by dividing the power supply voltage V _CC2 by the variable resistors R ₄₂ and R ₄₃ is input to the base of the transistor Q ₄₀ . The DC voltage turns on the transistor Q ₄₀ , and the variable current source A ₄₀ outputs the DC current I ₀ .

In this case, by changing the resistance value of the variable resistor R ₄₂ , the base voltage changes and the collector current of the transistor Q ₄₀ changes, which changes the direct current I ₀ of the variable current source A ₄₀ . Incidentally, the power supply voltage V _CC2 supplied to the variable current source A ₄₀ is set to be higher than the power supply voltage V _CC1 supplied to the video amplifier 11. Further, the video output circuit 40 includes an R signal system, a G signal system,
It is provided for each system of the B signal system. That is, the R signal, the G signal, and the B signal are input to the CRT 12 via the video output circuit 40, respectively.

In the above structure, the amplified video signal S1 output from the video amplifier 11 is input to the cathode of the CRT 12 via the resistor R ₄₀ and the capacitor C ₄₀ . In this case, since a DC voltage is generated in the resistor R ₄₀ by the DC current I ₀ of the variable current source A ₄₀ , the DC voltage (that is, the DC offset voltage) is actually equal to the DC voltage at the cathode of the CRT 12. The video signal S1 whose level is level up is input. When the resistance value of the variable resistor R ₄₂ is changed, the DC current I ₀ of the variable current source A ₄₀ changes, and the DC voltage (that is, the DC offset voltage) generated in the resistor R ₄₀ changes. As a result, the offset amount of the DC voltage level of the video signal S1 supplied to the cathode of the CRT 12 can be adjusted, and thus the cutoff voltage of the CRT 12 can be adjusted.

Therefore, in the video output circuit 40 provided for each of the R signal system, the G signal system, and the B signal system, the direct current I ₀ of the variable current source A ₄₀ is independently changed as described above, and the direct current I ₀ is changed. By changing the offset voltage, the variation in the cut-off voltage among the R signal system, the G signal system, and the B signal system can be easily adjusted, and an appropriate image can be obtained on the CRT 12.

In this way, in the video output circuit 40,
By adjusting the cut-off voltage of the CRT 12 by providing a DC level shift circuit 41 for DC-coupling the video amplifier 11 and the CRT 12 and shifting the DC voltage level of the video signal S1 by the DC voltage generated in the resistor R ₄₀ . You can In this case, since the video amplifier 11 and the CRT 12 are DC-coupled by the DC level shift circuit 41, the sag generated by the capacitor coupling unlike the conventional case does not occur in principle. Further, in the video output circuit 40, the time limit at the time of clamping that occurs when using the conventional clamp circuits 10 and 20 is eliminated, and the DC voltage level of the video signal S1 can be changed at any timing of the video signal S1. Incidentally, in the video output circuit 40, cost reduction can be expected as compared with the conventional clamp circuits 10 and 20.

According to the above structure, the DC level shift circuit 41 is provided which DC-couples the video amplifier 11 and the CRT 12 and shifts the DC voltage level of the video signal S1 by the DC voltage generated in the resistor R ₄₀ . As a result, the cutoff voltage of the CRT 12 can be easily adjusted without causing sag due to the vertical frequency component of the video signal S1.

(2) Second Embodiment In FIG. 3 in which parts corresponding to those in FIG. 1 are designated by the same reference numerals, 50 denotes a video output circuit as a video signal output circuit as a whole, and a DC level shift circuit 51. The video amplifier 11 and the CRT 12 are DC-coupled to shift the DC voltage level of the video signal S1 supplied to the CRT 12. In this embodiment, the DC level shift circuit 51 has the same structure as that of the first embodiment except the structure of the variable current source A ₅₀ .

Here, the variable current source A ₅₀ is constructed by using an NPN type transistor Q ₅₀ . Transistor Q ₅₀
Is connected to one end of the resistor R ₄₀ (cathode side of the CRT 12), and the emitter of the transistor Q ₅₀ is connected to the resistor R _40.
Connected to ground potential through ₅₀ . The base of the transistor Q ₅₀ is a DC voltage is input by dividing the voltage V _bb in resistor R ₅₁ and a variable resistor R _52. This DC voltage turns on the transistor Q ₅₀ , and the variable current source A ₅₀
Sinks a DC current I ₀ .

In this case, the direct current I ₀ of the variable current source A ₅₀
As a result, a DC voltage is generated in the resistor R _40, and the DC voltage is added to the video signal S1 output from the video amplifier 11 as a DC offset voltage. At this time, the DC voltage is generated so as to lower the DC voltage level of the video signal S1. That is, the cathode of the CRT 12 is supplied with the video signal S1 whose DC voltage level is lowered by the amount of this DC voltage (that is, DC offset voltage). In this case, since the DC voltage level of the video signal S1 is in the level-down direction, the pedestal level of the CRT 12 can be adjusted in the level-down direction as a result.

In the variable current source A ₅₀ , the base voltage changes and the collector current of the transistor Q ₅₀ changes by changing the resistance value of the variable resistor R ₅₂ . As a result, the DC current I ₀ of the variable current source A ₅₀ changes, and the DC voltage generated in the resistor R ₄₀ (that is, the DC offset voltage) changes. Incidentally, also in the case of this embodiment, the video output circuit 50
Are provided for the R signal system, the G signal system, and the B signal system, respectively.

In the above structure, the amplified video signal S1 output from the video amplifier 11 is input to the cathode of the CRT 12 via the resistor R ₄₀ and the capacitor C ₄₀ . In this case, a DC voltage is generated in the resistor R ₄₀ by the DC current I ₀ of the variable current source A ₅₀ , so that the cathode of the CRT 12 actually has a DC voltage equivalent to this DC voltage (that is, DC offset voltage). The video signal S1 whose level has been lowered is input. When the resistance value of the variable resistor R ₅₂ is changed, the DC current I ₀ of the variable current source A ₅₀ changes and the DC voltage (that is, the DC offset voltage) generated in the resistor R ₄₀ changes. As a result, the offset amount of the DC voltage level of the video signal S1 supplied to the cathode of the CRT 12 can be adjusted.

In this way, in the video output circuit 50 provided for each of the R signal system, the G signal system, and the B signal system, the DC current I ₀ of the variable current source A ₅₀ is independently changed as described above, and the DC current is supplied. By changing the offset voltage, the variation in the cut-off voltage among the R signal system, the G signal system, and the B signal system can be easily adjusted, and an appropriate image can be obtained on the CRT 12. Incidentally, in the video output circuit 50, the power supply V _{bb is set} to C
By making it higher than the cutoff voltage of RT12,
Since the first grid voltage of the CRT 12 can be connected to the ground, cost reduction can be expected.

According to the above construction, the DC level shift circuit 51 for DC-coupling the video amplifier 11 and the CRT 12 and shifting the DC voltage level of the video signal S1 by the DC voltage generated in the resistor R ₄₀ is provided. As a result, the cutoff voltage of the CRT 12 can be easily adjusted without causing sag due to the vertical frequency component of the video signal S1.

(3) Other Embodiments In the second embodiment described above, the case where the direct current I ₀ of the variable current source A ₅₀ is changed by the variable resistor R ₅₂ has been described, but the present invention is not limited to this. Not limited to this, for example, the output of the digital analog converter is connected to the base of the transistor Q ₅₀ , and the output voltage of the digital analog converter is changed according to the digital data output from a predetermined control circuit to change the variable current source A. The DC current I _{0 of 50} may be changed. In this case, if the control circuit is composed of, for example, a microcomputer, a so-called microcomputer, the DC offset voltage can be variously set and automatically adjusted according to the situation.

In the above embodiment, the case where the resistor R ₄₀ is connected in series between the video amplifier 11 and the cathode of the CRT 12 has been described, but the present invention is not limited to this, and the resistor R ₄₀ can be connected to the video amplifier. The same effect as in the above case can be obtained also when connecting in series between 11 and the first grid of the CRT 12.

In the above embodiment, the case where the video output circuits 40 and 50 are provided between the CRT 12 and the video amplifier 11 of the information processing apparatus has been described, but the present invention is not limited to this, and the present invention is applicable to consumers. It may be applied to a television device.

[0041]

As described above, according to the present invention, a direct current voltage is generated in the resistance element which is composed of a current source and a resistance element, which is used for direct current coupling between the video amplifier and the cathode ray tube, and which corresponds to the direct current of the current source. Thus, by providing the DC level shift means for shifting the DC voltage level of the video signal, it is possible to easily shift the DC voltage level of the video signal, thus causing sag due to the vertical frequency component of the video signal. The cut-off voltage of the cathode ray tube can be easily adjusted without doing so.

[Brief description of drawings]

FIG. 1 is a connection diagram showing a video output circuit according to an embodiment of the present invention.

FIG. 2 is a connection diagram showing a variable current source of the video output circuit.

FIG. 3 is a connection diagram showing a video output circuit according to a second embodiment.

FIG. 4 is a connection diagram showing a method of outputting a video signal by a conventional cascode amplifier.

FIG. 5 is a connection diagram showing a conventional clamp circuit using a blanking pulse.

FIG. 6 is a schematic diagram for explaining the operation of the clamp circuit.

FIG. 7 is a connection diagram showing a conventional clamp circuit by switching.

FIG. 8 is a schematic diagram for explaining the operation of the clamp circuit.

FIG. 9 is a connection diagram showing a clamp circuit using a conventional variable Zener diode.

[Explanation of symbols]

1, 12 ... Cathode ray tube (CRT), 2 ... Cascode amplifier, 10, 20, 30 ... Clamp circuit, 11 ... Video amplifier, 13 ... Addition circuit, 40, 50 ... Video output circuit, 41, 51 ... DC level shift circuit.

Claims (4)

[Claims] 1. A video signal output circuit for outputting a video signal amplified by a video amplifier to a cathode ray tube, comprising: a current source and a resistance element, wherein the video amplifier and the cathode ray tube are DC-coupled, and A video signal output circuit comprising a DC level shift means for shifting a DC voltage level of the video signal by a DC voltage generated in the resistance element according to a DC current of a current source. 2. The video signal output circuit according to claim 1, wherein the current source has one end connected to the resistance element and the other end connected to a predetermined potential or a ground potential. . 3. The current source is provided with a current control means for changing the direct current, and the current control means changes the direct current to change the direct current voltage generated in the resistance element. The video signal output circuit according to claim 1 or 2. 4. The resistance element comprises the video amplifier and a cathode or a first of the cathode ray tube.
The video signal output circuit according to claim 1, wherein a capacitor element that is connected in series with the grid and that bypasses the AC component of the video signal is connected in parallel.