JP2761806B2 - Signal processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing apparatus for controlling transmission of an analog input signal, inserting a signal, and the like, and more particularly to a DC voltage for a desired period of an output signal corresponding to the analog input signal. The present invention relates to a circuit technique suitable for converting to a level or for inserting a desired signal in a transmission path of an input signal.

[Conventional technology]

A muting circuit is known as a device that temporarily blocks transmission during transmission of an input signal.

However, when muting a video device, for example, for a luminance signal, simply blocking the signal transmission will
The brightness of the reproduced video is not constant, making it very difficult to see. In addition, as for the recent video equipment, as disclosed in “Television Technology, July 1989, pp. 20-21,” multi-functionalization has been achieved, and signal transmission is performed regardless of luminance signals and color signals. When the reference level fluctuates, it appears as a change in luminance and a change in color tone.

[Problems to be solved by the invention]

Therefore, for example, when muting is performed on a luminance signal, the DC voltage must be set to a desired level, and for that purpose, offset adjustment is required. on the other hand,
Video equipment is integrated into an IC.
Actually, the adjustment is performed by an external adjustment element. In such a configuration, it takes time to adjust,
The need for external components increases the manufacturing cost. In addition, there is a problem in that it is difficult to set a stable DC voltage when the temperature changes because the external components and the circuit elements inside the IC have different temperature dependencies.

The present invention has been made in view of the above problems, and has as its object to simplify the circuit configuration, eliminate the need for external components when forming a semiconductor integrated circuit, and obtain an output signal corresponding to an input signal. Another object of the present invention is to provide a signal processing device configured to obtain an output signal that does not correspond to an input signal at a desired voltage level.

[Means for solving the problem]

An object of the present invention is to provide a differential pair for switching a current path corresponding to a voltage level difference between a pair of input signals whose levels change in opposite phases or a voltage level difference between a reference voltage and a single-phase input signal. A current switch circuit composed of transistors configured as described above, and one current path of the current paths, for example, connected in series between a power supply and the collector of one transistor to obtain an output signal corresponding to the input signal, A load circuit comprising a plurality of resistors for obtaining an unsupported output signal, and forming a current bypass of a constant current at a desired timing corresponding to, for example, a pulse signal with respect to the current path forming the load circuit, This is achieved by a signal processing device having an output signal that does not correspond to the input signal due to a voltage drop, that is, a current bypass circuit for generating a DC voltage.

Further, the above object according to the present invention is achieved by forming a plurality of current bypasses having different current amounts by the current bypass forming circuit.

[Action]

According to the signal processing device having the above configuration, when the current bypass circuit is not formed by the current bypass circuit, the current switch circuit including the transistors connected to the differential pair and the input signal are supported by the action of the load resistance. An output signal is obtained.

On the other hand, when the current bypass is formed by the current bypass forming circuit, the current of the preset current bypass flows through the load circuit, and the voltage of the output signal is reduced due to the voltage drop corresponding to the current amount. The level is determined. Further, the voltage level of the output signal can be set to a desired voltage level by forming a plurality of current bypasses having different current amounts and selectively driving them by the current bypass forming circuit.

〔Example〕

Hereinafter, a first embodiment of a signal processing apparatus to which the present invention is applied will be described with reference to FIG. The present embodiment describes the basic circuit configuration and operation of the present invention, and specific examples will be sequentially described in the second embodiment and thereafter.

Differential amplifier 1 shown in FIG. 1 amplifies an input signal V _in, and those opposite phase of the output voltages V1, V2 to be supplied to the next stage of the current switch circuit 2 to each other. The current switch circuit 2 includes a pair of transistors Q1 and Q2, resistors RE1 and RE2 for providing linearity, and a constant current circuit CS1 for setting the current of the current switch circuit 2 to I1.

The load resistors R1 and R2 correspond to a load circuit according to the present invention, and perform current / voltage conversion and setting of a DC voltage level during muting. The muting switch S1 and the constant current circuit CS2 for defining the current at the time of muting constitute a current bypass circuit forming circuit according to the present invention, and the current bypass is formed by driving the switch S1 to ON. Done. The switch S2 is turned off simultaneously when the switch S1 is turned on, and the circuit is connected to the load resistors R1 and R2.
Prevent the CS1 current from flowing.

In order to set the output voltage level at the time of mute at the center of the signal voltage at the time of not muting, the load resistance R
1, the resistance value of R2 is set to R1 = R2, and the constant current circuits CS1, CS2
The current amounts of the currents I1 and I2 defined by are set as I1 = I2, In a relationship. Then, the final output signal _Vout of the signal processing device is obtained by the voltage drop of the load resistors R1 and R2.

Next, the circuit operation will be described. When performing a normal amplification operation, the switch S1 is turned off and the switch S2 is turned on.
To the differential amplifier 1, the case of supplying an analog input signal V _in as shown on the right side of FIG. 1, the output voltage V1 of the opposite phase from the differential amplifier 1, V2 is obtained, the transistors Q1, Q2 the bases of Is applied to During t1 (V1> V2), the output voltage V1
The collector-emitter current IQ of transistor Q1
1 increases, and the collector-emitter current IQ2 of the transistor Q2 decreases in inverse proportion to this current.

Therefore, the current IQ2 flowing through the load resistors R1 and R2 is also reduced, and
The voltage level of the output signal V _out which is determined by Q2 × (R1 + R2) is, V _cc - because (R1 + R2) × IQ2, and the small current value of the IQ2, becomes the voltage level close to the power supply V _cc.

On the other hand, during t2 (V1 <V2), the current IQ2 of the transistor Q2 increases and the current IQ1 of the transistor Q1 decreases. The voltage level of the output signal V _out which is determined by the IQ2 × (R1 + R2) _{is, V cc - (R1 + R2} ) × IQ2 next, since the current value of the IQ2 increases, becomes small voltage level. Therefore,
Switch S1 is off, if the switch S2 is set to ON, the output signal V _out corresponding to the input signal V _in is obtained.

Next, a circuit operation when the switch S1 is turned on and the switch S2 is turned off will be described.

When the switch S2 is turned off and the switch S1 is turned on by a pulse signal Vp having a predetermined pulse width, the power supply _Vcc
, A current bypass from the load resistor R1 to the constant current circuit CS2 via the switch S1 is formed. Further, since the switch S2 is off, the current IQ2 does not flow through the resistors R1 and R2. Then, while the current bypass is formed, the current I2 flows regardless of the input signal. Since the relationship of I1 = I2, when the current I2 flows through the constant current circuit CS2, the current R2 does not flow through the current path of the resistor R2 and the transistor Q2, and there is no voltage drop due to the resistance R2. However, it is determined by I2 × R1. The voltage applied to the transistor Q2
, The voltage level of the output signal _Vout becomes _Vout = _Vcc− I2 × R1. Since the relations of R1 = R2 and I1 = I2 are set, the voltage level of the output signal _Vout is 電 圧 that of the normal operation.

That is, turns on the switch S1, if you turn off the switch S2, the level of the output signal V _out does not correspond to the level change of the input signal V _in, the signal of muting is performed. In addition, the level of the output signal V _out during the muting period is always 1 / the level of the normal operation as shown by the dotted line in the waveform of the output signal.
It is set to the level of 2, in other words, the midpoint level.

Therefore, it is not necessary to provide a current adjusting means or the like for level adjustment at the time of muting. Also, the current I2
Is stabilized, so that the muting level is made constant, so that level adjustment at the time of signal transmission / reception becomes easy, and multipurpose use becomes possible. Further, there is no need for adjusting means for current adjustment and voltage adjustment. In addition, since the present circuit uses a differential input, there is an effect that it is not affected by fluctuations and variations in DC levels of V1 and V2.

Next, a second embodiment will be described with reference to FIGS. Note that the same reference numerals are given to portions having the same functions as in the first embodiment, and description thereof will be omitted.

The double-emitter transistor Q3 has the same function as the switch S1 and also serves as the switch S2 shown in FIG.

Each emitter is connected to a constant current circuit CS1 via resistors RE1 and RE2. Therefore, when the transistor Q3 is turned on, the resistor R1, the transistor Q3, and the constant current circuit CS1
Is formed. The current flowing through this current bypass becomes I1, and the same muting as described above is performed.

The pulse signal Vp switches between muting and normal operation, and is supplied from a pulse generation circuit (not shown). The pulse signal Vp changes to a high level (Vp> V1, Vp> V2) during muting, and drives the transistor Q3 on. Also, during normal operation, the transistor Q3 is kept at the off level to keep the transistor Q3 in the off state (Vp <V
1, VP <V2). The output signal _Vout is obtained from an output transistor Q4 configured as an emitter follower. Note that the constant current circuit CSe is a constant current source of the output transistor Q4.

 Next, the circuit operation will be described.

First, the normal operation will be described. The pulse signal Vp is set to low level (Vp <V1, Vp <V2), and the transistor Q3
Turn off. Therefore, during normal operation, transistor Q3
The effect of can be neglected. The differential amplifier 1, the input signal V _in as shown in FIG. 3 (a) is supplied. Then, the differentially amplified output voltages V1 and V2 having opposite phases are supplied to respective bases of the transistors Q1 and Q2. Transistor Q
1, Q2 performs the same amplification operation as described in the first embodiment, the current IQ1, IQ2 are increased or decreased in response to the level change in the input signal V _in. The collector voltage Vo of the transistor Q2 has a voltage level determined by _Vcc− IQ2 × (R1 + R2),
The level changes according to the current IQ2.

Voltage Vo is supplied to the base of output transistor Q4. Therefore, the output signal V _out is to that corresponding to the input signal V _in as shown in FIG. 3 (c).

On the other hand, when performing muting, the pulse signal Vp is set to a high level (Vp> V1, Vp> V2).

During the period Th in which the pulse signal Vp is at the high level, the transistor Q3 is turned on, Q1 and Q2 are turned off, and the power supply _Vcc , the resistor R1, the double emitter of the transistor Q3, and the resistors RE1, R
E2 forms a current bypass of the constant current circuit CS1. Current flowing through the resistor R1, regardless of the level of the input signal V _in I
It is fixed at 1, and the voltage drop between both ends becomes a voltage level determined by I1 × R1.

Therefore, the voltage level of the output voltage Vo is a voltage determined by _Vcc− R1 × I1.

As a result, as shown by a dotted line in FIG. 3 (c), the output signal _Vout has the input signal Vin _in the Th period of the pulse signal Vp.
Does not appear, indicating that the muting has been performed. The muting level of the output signal V _out is V _cc
−I1 × R1−V _be DC voltage determined by (Q4). If the resistances R1 and R2 are the same as above (R1 = R2), the muting level will be half the voltage level during normal operation, in other words, the midpoint level, and the muting level will be fixed. Can be

Also in the present embodiment, in addition to the same effects as above,
Because of the differential input configuration, it can be stabilized against power supply and temperature fluctuations, and is not affected by DC fluctuations and variations in voltages V1 and V2. And the circuit configuration can be simplified.

 Next, a third embodiment will be described with reference to FIG.

The difference between the present embodiment and the second embodiment is that the transistor Q3 is constituted by a single emitter.

When performing a normal operation, the pulse signal Vp is set to a low level (Vp <V1, Vp <V2) to turn off the transistor Q3. Therefore, the output voltages V1 and V2 of the differential amplifier 1 are amplified by the current switch circuit 2, and the output transistors Q4
The output signal V _out from the emitter corresponding to the input signal V _in is obtained.

On the other hand, when performing the muting operation, the pulse signal is changed to a high level (Vp> V1, Vp> V2), and the transistor Q3 is set to ON. As a result, the resistance from the power supply V _cc R
1, a current bypass to the transistor Q3, the resistor RE3, and the constant current circuit CS1 is formed, and the current I1 flows through the resistor R1. Output signal
The voltage level of V _out becomes a DC voltage which is determined by the _{V cc -I1 × R1-V be} (Q4). In this embodiment, the reason why the resistor RE3 is provided at the emitter of the transistor Q3 is that the pulse signal Vp
In order to reduce the occurrence of switching noise when the signal is shifted to a high level. Note that the resistance value of the resistor RE3 is lower than that of the resistors RE1 and RE2 (RE1 ≧ RE3, RE2 ≧ R
E3).

Next, a fourth embodiment will be described with reference to FIG. still,
The difference between this embodiment and each of the above embodiments lies in that the amplification operation and the muting operation in the normal operation are performed by comparison with a reference voltage.

The transistors Q1, Q2 and Q5 form a current switch. The transistors Q1 and Q2 perform a switching operation by comparing the output voltage V11 of the drive circuit 11, that is, the single-phase input signal, with the reference voltage _Vref supplied from the reference power supply circuit 12. The transistor Q5 compares the reference voltage _Vref with the pulse signal Vp and forcibly turns off the transistors Q1 and Q2 during muting. The transistors Q6 and Q7 perform a muting operation by comparing the reference voltage _Vref with the pulse signal Vp.
Q6, the current path of the constant current circuit CS2 forms a current bypass.

Next, the circuit operation at the time of normal operation will be described. Since the pulse signal Vp is at a low level, the relation of _Vref > Vp is satisfied.
The transistors Q5 and Q6 are turned off. Therefore, the transistors Q1 and Q2 perform an amplification operation by comparing the voltage with the reference voltage _Vref, and the current IQ2 increases and decreases _{in accordance with} the level change of the input signal Vin. Transistor Q4 also operate in the same manner as described above, the output signal V _out will those corresponding to the input signal V _in.

On the other hand, when performing the muting operation, the pulse signal
Vp is transited to a high level, and the relations of Vp> V11 and _Vref <Vp are set. Transistor Q5 turns on and transistor
Since Q1 and Q2 are forcibly turned off, the amplification operation is disabled. Also, since the transistor Q6 is turned on, the resistance R1,
The transistor Q6 forms a current bypass of the constant current circuit CS2, and the transistor Q7 is turned off.

The amount of current in the current bypass formed by the transistor Q6 is set to be the same as the current I1 by the constant current circuit CS2. Therefore, the voltage level of the output signal _Vout is _Vcc
-I1 × R1-V will _{be (Q4) (I1 = I2} ), the same muting is performed. In this circuit, by giving a DC value to the drive circuit and the reference voltage source by the same circuit configuration, there is an effect of reducing the influence of the variation.

Next, a fifth embodiment will be described with reference to FIGS. The feature of the present embodiment lies in that, for example, character information, a date, and the like can be inserted into a video signal by utilizing the muting function.

Circuit structure and operation of the transistors Q1, Q2, Q5 is similar to the above fourth embodiment, FIG. 7 (a) to indicate such luminance signal Y as an input signal V _in is supplied. Note that the illustrated luminance signal Y is an example of a waveform during one horizontal scanning period, and is not limited to the illustrated level change.

The transistors Q1 to Q8 are connected in three differentials, and the reference voltage _Vref obtained from the reference voltage source 3 and the pulse signals _Vp1 , _Vp2
Are compared to form a current bypass by the transistor Q6 and a current bypass by the transistor Q7.
Note that the time width Th of the pulse signals V _p1 and V _p2 is as shown in FIG.
Although V _p1 > V _p2 is set as can be compared to (c), the voltage levels of both are set to V _p1 <V _p2 .

In normal operation, the pulse signals V _p1 and V _p2 are both set to low level (V _p1 and V _p2 are smaller than V1 and V2),
The transistors Q5 to Q7 are turned off, and the transistor Q8 is turned on. The output voltages V1 and V2 of the differential amplifier 1 are supplied to the bases of the transistors Q1 and Q2, and the same amplifying operation as described above is performed. However, since the load circuit is composed of three resistors connected in series, the output voltage Vo is _Vcc− IQ2 ×
The voltage is determined by (R1 + R2 + R3), and the voltage level changes according to the increase / decrease of IQ2, in other words, the level of the luminance signal Y.

Next, as an example of signal processing, insertion of character information and date will be described.
As shown in the _figure , the pulse signal V _{p1 is set} to high level (V _p1 is V1, V
2, smaller than any of V _ref and V _p2 ). As a result, the transistor Q5 is turned on, and the transistors Q1, Q2
Is turned off and the amplification operation is disabled. On the other hand, the transistor Q6 is also turned on, and the transistors Q7 and Q8 are turned off.
Power supply _Vcc , resistors R1, R2, transistor Q6, constant current circuit CS2
Is formed. The voltage level of the output signal V _out will be determined by the _{V cc -I2 × (R1 + R2} ) -V be (Q4). As a result, the level of a part of the output signal _Vout decreases as indicated by Va in FIG. 7D.

Next, at the timing shown in FIG.
_{Set p2} to high level (V _p2 > V _p1 > V1, V _p2 > V _p1 > V2, V _p2 > V
_{When the} transition is made to _p1 > _Vref ), the transistor Q7 is turned on and the transistor Q6 is turned off. Note that the pulse signal V _p1
Remains at the high level, the transistor Q5 continues to be on, and the transistors Q1 and Q2 remain off.

When the transistor Q7 is turned on, the power
A current bypass of V _cc , resistor R1, transistor Q7 and constant current circuit CS2 is formed, and output signal V _out is V _cc −I2 × R1−V _be (Q4)
The voltage level is determined by This voltage level is lower than the voltage level when transistor Q6 is turned on.
High level by the voltage drop of R2. Looking at the difference in the voltage level with respect to the waveform of the output signal _Vout , it becomes a high level as shown as Vb in FIG. 7D.

As clearly shown in FIGS. 7B and 7C, the pulse signal
The time width of V _p2 is smaller than the time width of pulse signal V _p1 . When the pulse signal _Vp2 changes to the low level while the pulse signal _Vp1 is at the high level, the transistor Q7 is turned off and the transistor Q6 is turned on again. Therefore, the output signal V
_out changes from the voltage level shown as Vb to the voltage level described as Va.

Next, when the pulse signal _Vp1 changes to low level, the transistors Q5 and Q6 are turned off, and the normal operation by the transistors Q1 and Q2 is performed. Also, transistors
Q8 turns on and no current bypass is formed. Therefore, as shown in FIG. 7 (d), the output signal _Vout is obtained by inserting a DC level irrelevant to the level of the luminance signal Y at a desired position in the luminance signal Y in one horizontal scanning period. become.

Next, an image displayed by the output signal _Vout will be described.

Now, assume that an image as shown in FIG. 8 is displayed by the luminance signal Y for one frame. If it is desired to insert a date or the like at a desired position in the image, for example, at the lower right, the level operation of the pulse signals V _p1 and V _p2 is performed as described with reference to FIG. As a result, a high luminance portion due to the pulse signal _Vp2 appears during a low luminance due to the pulse signal _Vp1 as shown in the enlarged view. Therefore, by controlling the time width and timing of the pulse signals V _p1 and V _p2 , characters, symbols, and the like can be displayed based on the difference in luminance. Moreover, the difference in luminance due to the pulse signals V _p1 and V _p2 can be set to a desired luminance difference irrespective of the luminance of the background image, and the high luminance part is framed by the low luminance part. , Very easy to see.

 Next, a sixth embodiment will be described with reference to FIG.

The circuit configuration in this embodiment is configured so that the circuit described with reference to FIG. 6 can be further simplified, and the current source CS3 can be omitted and the current source CS1 can operate to reduce the number of elements and power consumption. Things. That is, the load resistance is three resistors
The switch circuit for the differential input and the pulse for the date input, which is constituted by R1 to R3, includes transistors Q1, Q2, Q6,
Consists of Q7.

The circuit operation will be described. When the pulse signals V _p1 and V _p2 are both at a low level (when no date is sent), the base potentials of the transistors Q6 and Q7 are lower than the base potentials of the transistors Q1 and Q2. Q6 and Q7 are turned off, and current I1 at constant current point CS1 is shunted to transistors Q1 and Q2. That is, the output voltage Vo of the current switches of the transistors Q1 and Q2 is equal to the current flowing through the transistor Q2 and three currents.
R1, R2, obtained as a voltage drop across R3, the output signal V _out is to that corresponding to one or more of the magnification of the input signal V _in.

Next, consider a case where date information is transmitted to a luminance signal.
When the pulse signal _Vp1 transitions to the high level, the base of the transistor Q6 has the highest potential. Then, the transistor Q6 is turned on, the output signal V _out, as shown in the signal Va of FIG. 7 _{(d), V cc - (} R1 + R2) × I1
The level changes to the level of −V _be (Q4) (that is, 5 × IRE from the pedestal level). Further, the pulse signal V _p2 is turned to a high level, and the high level of the signal V _p2 is changed to the signal V _p1.
Above the high level, the transistor Q6 is cut off and the transistor Q7 is turned on. At this time, the output signal V _out, as shown by the signal Vb of FIG. 7 (d), changes to _{V cc} -R1 × I1-V be of (Q4) level (i.e., 80 × IRE than the pedestal level) I do.

As a result, as described with reference to FIG. 8, bordered characters and the like can be inserted into the projected image.

Note that the resistance of the current switch circuit is RE1 = RE2 ≧ RE
6. Make the relationship of RE1 = RE2 ≥ RE7, and set the resistors RE6 and RE7.
Is provided to prevent switching noise at the time of switching from appearing in the output.

By the way, current video equipment is provided with various functions as disclosed in a known example, and the differential amplifier 1 simply outputs positive-phase and negative-phase output voltages to the current switch circuit 1. Not only can it be used to supply, but it can be used for other purposes.

The differential amplifier 1 shown in FIG. 10 has a fade function, and in addition to performing the above-described signal processing on the output voltages V1 and V2, can exhibit various functions during signal transmission.

Next, an example of the differential amplifier 1 will be described with reference to FIG.

First, the basic configuration will be described. The first switch circuit 11 is a current switch for synthesizing (mixing) or switching an input signal Vin (luminance signal Y _{in the} present embodiment) described later and a title signal _Vtin . In this embodiment, four sets of switch circuits are provided. The second switch circuit 12, in response to the input signal V _in and title signals V _tin is intended to obtain the current output, in this embodiment 2
It consists of a set of switch circuits. 13 is an output circuit,
The resistors RL11 and RL12 are load resistors of the first switch circuit 11.

Clamp circuit 14, together with the generated reference voltage Va is supplied to the second switching circuit 12 supplies the title signal V _yin superimposed on the reference voltage Va when the supply of the title signal V _tin to the second switch Things. Accordingly, the clamp circuit 14 clamps the reference voltage of the title signal V _tin to the voltage Va and supplies it to the second switch circuit 12.

The clamp circuit 15 generates the reference voltage Va and supplies it to the second switch circuit,
V _in , that is, in this embodiment, for superimposing the luminance signal Y and supplying it to the second switch circuit. Thus, the clamp circuit 15 will be supplied to the second switch circuit 12 clamps the reference voltage of the input signal V _in the voltage Va. Note that the capacitors C31 and C41 provided in the clamp circuits 14 and 15 are input capacitors, and perform a DC cut at the time of inputting a signal. External parts.

Next, the circuit operation will be described. The circuit operation differs as follows depending on the level difference between the reference voltage _Vref supplied to the second switch circuit 11 and the fade voltage VF.

a) When VF <V _ref .

When the input signal V _in (luminance signal Y) is supplied to the clamp circuit 15 through a capacitor C41, it is applied to the base of the transistor Q24 constituting the switching circuit 12 is superimposed on the voltage Va. Although the base of the transistor Q23 is takes voltages Va, the current flowing through the transistor Q24 is increased by the application of an input signal V _in, the current through the transistor Q23 decreases. Therefore, a current path for the transistors Q17 and Q18 forming the first switch circuit 11 is formed.

The reference voltage _Vref is supplied to the base of the transistor Q17, and the fade voltage VF is supplied to the transistor Q18. However, since the level is set as described above, the current flowing through the resistor RL12 and the transistor Q17 increases. I do.
As a result, the voltage drop across the resistor RL12 is increased in response to the input signal V _in. Accordingly, an output signal V2 having an opposite phase is obtained from the emitter of the transistor Q19 constituting the output circuit 13.

On the other hand, looking at the current path formed by the transistor Q23, since _Vref > VF, the current flowing through the resistor RL11 and the transistor Q13 increases with respect to the current flowing through the transistor Q14. However, since the current is reduced by the action of the transistor Q23, the voltage drop of the resistor RL11 is small.

Therefore, a positive-phase output signal V1 is obtained from the emitter of the transistor Q20 that forms the output circuit 13.

When the title signal V _tin is supplied in this state, the voltage Va
And applied to the base of a transistor Q22 forming the second switch circuit 12. Although the voltage Va is applied to the base of the transistor Q21, the base voltage of the transistor Q22 becomes high. The current flowing through the transistor Q22 increases, and the current of the transistor Q21 decreases.
A switch circuit including transistors Q15 and Q16 is provided between the transistor Q22 and the power supply _Vcc .
Since the relation of V _ref > VF is set, the transistor Q
The current flowing through 16 increases. Since no collector of the transistor Q16 is connected to the resistor RL12, it does not appear affected title signal V _tin output signal V2 of the opposite phase.

On the other hand, in the current path formed by the transistor Q21, a switch circuit constituted by the transistors Q11 and Q12 is provided. However, since the relation of _Vref > VF is set, the current flowing through the transistor Q12 increases. I do. Since the collector of the transistor Q12 is not connected to the resistor RL11, the title signal V _tin is added to the positive-phase output signal V1.
Does not appear.

That is, when the relation of V _ref > VF is set, the input signal V
Output signals V1 and V2 of the normal phase and the negative phase corresponding to _in are obtained.

b) When VF> V _ref .

While performing signal processing on the input signal V _in as described above, supplies the title signal V _tin as Fig. 11 (b), for the desired period ta as shown in FIG. (C) VF> Set to V _ref . The transistor Q22 receives the input signal V
It operates in the same manner as described above _in response to _in , but the current flowing through the transistor Q18 for the transistors Q17 and Q18 provided in the collector circuit increases.

That is, the switch from the transistor Q17 to the transistor Q18 is performed. Therefore, the resistance RL12 input signal V _in does not flow a current corresponding to the input signal V _in to an output signal V2 of the opposite phase
Does not appear.

For the title signal V _tin , the transistor Q22 operates in the same manner as described above, but for the transistors Q15 and Q16 provided in the collector circuit, the amount of current flowing through the transistor Q15 increases. That is, the transistor Q
This means that the switch from 16 to Q15 has been performed. Therefore, the amount of current flowing through the resistor RL12 corresponds to the title signal V _tin, and the output signal V2 having the opposite phase also changes to the title signal V _tin.
Corresponds to _tin .

On the other hand, in the current path of the transistor Q23, switching from the transistor Q13 to Q14 is performed. In the current path of the transistor Q21, the transistor Q21
The switch from 12 to Q11 is performed. Therefore, the resistance RL1
The current flowing through 1 and the voltage drop are small, and the positive-phase output signal V1 corresponds to the title signal _Vtin .

That is, when VF> _Vref , the title signal V _tin
, And output signals V1 and V2 of the normal phase and the negative phase corresponding to.

Returning from (b) to (a).

As a result of performing the above operation for the desired period ta, a component of the title signal V _tin appears in the output signal V _out (showing the positive-phase output) as shown in FIG. 11D. When reset to relationship again V _ref> VF From this state, the circuit operates as described in (a) is carried out, resulting output signal V _out corresponding to the input signal V _in as shown in later period ta Can be

By the way, the transition time of the fade signal VF from low level to high level or from high level to low level is defined as
As shown in FIG. 12, when the transition is large, in other words, the transition is slow over a long period of time, and each of the resistors R11 to R18 constituting the first switch circuit 11 is set to a high resistance value, the following remarkable operation is performed. Is performed.

That is, by setting the resistances of the resistors R11 to R18 to a high resistance value, the time of the switch operation in the first switch circuit 11 becomes longer. As a result, at the voltage values before and after the reference voltage _Vref and the fade voltage VF intersect, the output signals V1,
And the input signal V _in and the title signal V _tin becomes longer appears time at the same time to V2, gradual fade-in, so capable of performing fade-out. That is, by setting the resistances of the resistors R11 to R18 to a high resistance value, the synthesis time of the two signals shown as MIX in FIG. 12, that is, the mixing time can be lengthened. Therefore, the mixing time can be adjusted by setting the resistance values of the resistors R11 to R18, and the circuit can be easily designed and can be used for various purposes.

The input signal V _in, the clamp circuits 14 and 15 provided in the input path of the title signal V _tin, because it sets the respective pedestal level voltages Va, also be a constant DC value of the output signal V1, V2 Can be. Therefore, the reference level is set for the output signals V1 and V2, and the signal processing described with reference to FIGS. 1 to 9 is easily performed. Furthermore, since each switch circuit is configured to connect a transistor to a target, the circuit operation is not affected by fluctuations in power supply and temperature, and stable circuit operation is performed.
Variations in pedestal level are also reduced.

Note that the number of clamp circuits and the number of current switches constituting the first and second switch circuits are not limited to the above, and can be increased according to the number of title signals to be input and the like.

〔The invention's effect〕

As described above, the signal processing device according to the present invention includes a current switch circuit that obtains an output signal corresponding to an input signal;
A current side path forming circuit for forming a current side path for the current switch circuit corresponding to the pulse signal is provided, and at the time of forming the current side path, an output signal corresponding to an input signal is cut off and a current flowing through the current side path is cut off It is configured to obtain an output signal of a predetermined level based on the output signal.

Further, a plurality of current bypasses are selectively formed by the current bypass forming circuit, and the level of the output signal can be set to a desired level.

According to the signal processing device having the above configuration, transmission of an input signal can be temporarily cut off to set a desired DC level, and the time and level can be easily adjusted by the time width and level of the pulse signal. be able to.

Therefore, when implementing a semiconductor integrated circuit, it is not necessary to provide an external component for voltage adjustment, and it is possible to simplify the equipment to which this signal processing device is applied and to improve the usability.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a basic configuration of the present invention, FIG. 2 is a circuit diagram showing a second embodiment of the present invention, FIG. 3 is a waveform diagram for explaining the circuit operation, and FIG. FIG. 5 is a circuit diagram showing a fourth embodiment, FIG. 6 is a circuit diagram showing a fifth embodiment, FIG. 7 is a waveform diagram illustrating circuit operation, and FIG. 8 is muting. FIG. 9 is a circuit diagram showing a sixth embodiment, FIG. 10 is a circuit diagram showing one embodiment of a differential amplifier, FIG. 11 is a waveform diagram for explaining circuit operation, and FIG. FIG. 4 is a signal waveform diagram illustrating a change in a fade signal. Explanation of reference numerals: 1 ... Differential amplifier, 2, 11, 12 ... Current switch circuit, 13, 14 ... Clamp circuit, R1, R2, RL11, RL12 ...
… Load resistance, V _in …… Input signal, V1, V2 …… Differential output, V
_out: output signal, Vp: pulse signal, V _ref: reference voltage, VF: fade voltage, V _tin: title signal, Q1 to
Q41: transistor, I, IQ1, IQ2 ... current.

Claims (2)

(57) [Claims] A current switch circuit for switching a plurality of current paths in response to a voltage level difference between a pair of input signals whose levels change in opposite phases or a voltage level difference between a reference voltage and a single-phase input signal; A load circuit connected in series to one of the current paths to obtain an output signal corresponding to the input signal and to obtain an unsupported output signal; and a desired timing for the current path forming the load circuit. And a current bypass forming circuit for generating an output signal incompatible with the input signal at one end of the load circuit due to a voltage drop of the load circuit. . 2. A current switch circuit for switching a plurality of current paths according to a voltage level difference between a pair of input signals whose levels change in opposite phases or a voltage level difference between a reference voltage and a single-phase input signal. A load circuit connected in series to one of the current paths to obtain an output signal corresponding to the input signal and to obtain an unsupported output signal; and a desired timing for the current path forming the load circuit. Forming a plurality of current bypasses having different current amounts, and generating an output signal at one end of the load circuit that is incompatible with the input signal and that changes in level according to the current amount. A signal processing device comprising: a circuit;