JPS62225024A - Wintegration circuit - Google Patents

Abstract

PURPOSE:To obtain an integration circuit with a long time constant while an output dynamic range is expanded by connecting a capacitor between one output terminal and other output terminal of a differential amplifier. CONSTITUTION:The capacitor 6 is inserted between one output terminal and the other output terminal of the differential amplifier l. Outputs of the output terminals are inputted to an adder 9 via buffer circuits 7,8 respectively. Thus, since an inverting output signal of the amplifier l is fed across the capacitor 6, the midpoint of the capacitor 6 is a ground point in terms of AC and the circuit is shown in an equivalent circuit in figure. Let the capacitance of the capacitor 6 be C, then the combined capacitance of the split capacitors 6A,6B is 2C. When an output voltage of +1V is given at one output of the amplifier 1, a voltage -1V is applied to the other output terminal and vice versa. Thus, the dynamic range of the output is + or -2V and the value is twice that of a conventional integration circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrating circuit configured using a capacitor inside an IC circuit.

[Summary of the invention]

This invention connects a capacitor between two output terminals of a differential amplifier, connects the two output terminals of the differential amplifier to the input terminal of an adder via a buffer circuit, and derives the output terminal from the adder. This is an integrating circuit with an expanded dynamic range and a longer time constant by reducing the charging and discharging current of the capacitor.

[Conventional technology]

In order to realize an integrating circuit with a long time constant, it is necessary to increase the capacity of the integrating capacitor or to decrease the charging/discharging current. In conventional RC integration circuits, the time constant was lengthened by connecting a time constant circuit consisting of a resistor and a large capacitor to the outside of the IC. ) has the problem of increasing the manufacturing cost of the IC.I
An example of an integrating circuit that can increase the time constant by using a capacitor built inside the circuit is the one shown in FIG.

In FIG. 6, 21 represents a differential amplifier, one input terminal of which is supplied with an input signal from an input terminal 22, and the other input terminal connected to a reference voltage source 23. The constant current #24 of the differential amplifier 21 is switched by the switching circuit 25. Differential amplifier 21
A capacitor 26 inside the IC is connected to the output terminal of the differential amplifier 21 , and the output terminal of the differential amplifier 21 is led out as an output terminal 28 via a buffer circuit 27 .

A concrete connection of the above-mentioned integrating circuit is shown in FIG.

The input terminal 22 is connected to the base of the transistor 31,
A reference voltage source 23 is connected to the base of the transistor 32 . Diode-connected transistors 34, 35 and 36.3 are connected between the respective collectors of transistors 31 and 32 and power supply terminal 33 for a current mirror circuit.
7 is connected. A constant current #38. A constant current source consisting of a diode-connected transistor 39 and a transistor 40 is connected. A switching transistor 41 is inserted between the base of this transistor 40 and ground. A switching pulse is supplied to the base of the switching transistor 41 from a terminal 42 . When the switching pulse is at a high level, the switching transistor 41 is turned on, and the constant current supply to the differential amplifier is cut off. Further, a capacitor 26 is inserted between the collector of the L transistor 31 and the ground, and an output terminal 28 is led out via a buffer circuit 27.

A charging/discharging current is supplied to the capacitor 26 according to the difference between the input terminal and the reference voltage. In order to increase the time constant of such an integrating circuit, it was necessary to increase the capacitance of the capacitor 26 and to decrease the charging/discharging current of the capacitor 26.

[Problem that the invention seeks to solve]

The capacitance of the capacitor 26 formed inside the IC has been limited to about 80 (pF) from the viewpoint of cost and process. Moreover, the constant current to be switched is the seventh
In the configuration shown in the figure, the switched transistor 4
Since the collector current of 0 is transmitted to the capacitor 26 through the collector-emitter of the transistor 31, the value of the constant current to be switched cannot be made small;
The limit of miniaturization was about nA3. Therefore, the time constant was restricted by these values and could not be made sufficiently long. Furthermore, the dynamic range of the output was equal to the dynamic range of the output of the differential amplifier. Therefore, when a VCO (voltage controlled oscillator) is connected at the subsequent stage, there is a drawback that it is not possible to sufficiently absorb variations in the characteristics of the VCO (control voltage - oscillation frequency).

Therefore, an object of the present invention is to lengthen the time constant by making the charging/discharging current of the capacitor smaller, and to
An object of the present invention is to provide an integrating circuit that can expand the dynamic range of output.

[Means for solving problems]

The present invention provides a differential amplifier in which a capacitor is connected between one output terminal and the other output terminal, and one output terminal and one input terminal of the differential amplifier are connected to each other via a first buffer circuit. The other output terminal and the other input terminal of the differential amplifier are connected via a second buffer circuit, and the adder is provided with an adder from which an output signal is taken out.

[Effect]

Since a capacitor is connected between the opposite phase output terminals of the differential amplifier, the dynamic range of the output is twice that of a conventional integrating circuit. Therefore, when connecting a VCO at a subsequent stage, it is possible to deal with variations in the characteristics of the VCO.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, all elements including the capacitor are built into an IC. An explanation of this example is as follows:
Made in the order of the items below.

a, Basic configuration, Application example of AFC circuit to filter C9 Specific connection a, Basic configuration In FIG. 1, one input terminal of the differential amplifier indicated by l is derived as input terminal 2, A reference voltage source 3 is connected to the other input terminal of the . The constant current supplied to the differential amplifier 1 is obtained by switching a constant current generated by a constant current source 4 by a switching circuit 5.

A capacitor 6 is inserted between one output terminal and the other output terminal of the differential amplifier 1. One output terminal of the differential amplifier l is connected to one input terminal of the adder 9 via the buffer circuit 7, and the other output terminal of the differential amplifier l is connected to the other input terminal of the adder 9 via the buffer circuit 8. connected to the input terminal. The output terminal of adder 9 is derived as output terminal 10.

Adder 9 generates a current output.

In this embodiment, since the opposite-phase output signal of the differential amplifier 1 is supplied to both ends of the capacitor 6, the midpoint of the capacitor 6 becomes a ground point in terms of AC. Therefore, the circuit connection shown in FIG. 1 can be represented by the equivalent circuit shown in FIG. 2. If the value of capacitor 6 is C, then the value of divided capacitors 6A and 6B in FIG. 2 is 2C. When an output voltage of +1■ is generated at one output terminal of the differential amplifier 1, an output voltage of -iv is generated at the other output terminal. Conversely, when an output voltage of +1V is generated at one output terminal, an output voltage of -1V is generated at the other output terminal. Therefore, the dynamic range of the output becomes +2■, which can be expanded to twice that of the conventional integrating circuit.

b. Example of application to a filter of an AFC circuit FIG. 3 shows the configuration of an example in which the present invention is applied to a filter of an AFC circuit. The AFC circuit is a rotating head type VTR.
It is provided in the recording circuit of , and is used to generate a conversion carrier signal for converting a carrier color signal into a low-band conversion color signal.

In the AFC circuit, a VCO with a center frequency of 378 rH (fH: horizontal scanning frequency) is provided, and by dividing the output signal of this VCO by (1/8), the output signal is 743 (kl).
1z) conversion carrier signal is formed. Also, V.C.
The signal obtained by frequency-dividing the output signal of O and the horizontal synchronization signal are AFC.
The detection circuit performs a phase comparison, and the phase comparison output is supplied to the VCO as a control voltage via a low-pass filter.

In this case, if the phase of the VCO output signal and the horizontal synchronization signal are largely shifted, the AF signal indicated by 20 in FIG.
The control voltage of the VCO is forcibly raised or lowered by the CID circuit.

In FIG. 3, an AFC error signal from an AFC detection circuit is supplied to an input terminal 18, and this AFC error signal is supplied to an adder circuit 9 via a low-pass filter 19. The output signal of the low-pass filter 19 is transmitted to the adder circuit 1
2. The output signal of the adder circuit 12 is supplied to one input terminal of the differential amplifier 11. Differential amplifier 11.
Constant current rX14. Switching circuit 15. The capacitor 16 and the buffer circuit 17 constitute an integrating circuit similar to the conventional one. A negative feedback path including an attenuator 13 is provided between the output terminal of the buffer circuit 17 and the adder circuit 12.

The output signal of the buffer circuit 17 is supplied to the adder circuit 9 and also to one input terminal of the differential amplifier l.

The differential amplifier l constitutes an integrating circuit similar to that shown in FIG. The output signal of this integrating circuit is supplied to an adding circuit 9. I formed in the AFCID circuit 20
The D error signal is added to the AFC error signal.

This ID error signal is added to both ends of the capacitor 6 by current addition, and in order to speed up the pull-in,
It is added by voltage addition to the other input terminal of the differential amplifier 11 of the previous stage integrating circuit.

The filter shown in FIG. 3 described above has a low-pass characteristic shown by a in FIG. It has a frequency characteristic that is a combination of the low-pass characteristic shown in C. The attenuation slope of low-pass characteristic A is -6 (dBloct), and the attenuation slope of low-pass characteristic C is 12 (dB10ct). Low-pass characteristics a and b realize characteristics similar to a lag lead filter. , differential amplifier l has characteristics such that the time constant is long and the attenuation slope is large, and a DC feedback loop is formed by this integrating circuit.V
The APC circuit provided in the reproduction circuit of the TR is the above-mentioned AF
It is configured similarly to the C circuit.

C9 Specific Connections The specific connections of the embodiment of the present invention shown in FIG. 1 above are shown in FIG. The input terminal 2 to which an input signal such as an AFC error signal is supplied is supplied to a differential amplifier 55 using a pair of Darlington connections, and is converted into a differential signal current.

A constant current source 58 and a series connection of diode-connected transistors 56 and 57 are inserted between the power supply line 51 and the ground line 53, and one of the differential signal currents is supplied to the connection point between the transistors 56 and 57. . Constant current source 5
The connection point between the transistor 8 and the transistor 56 is connected to the base of the transistor 59. The collector of the transistor 59 is connected to the power supply line 51, the emitter of the transistor 59 is grounded via a constant current s6o, and is connected to the base of a transistor 64 via a resistor 61. The base of this transistor 64 is grounded through the collector and emitter of the transistor 62. A switching pulse is supplied to the base of the transistor 62 from a terminal 63. When the switching pulse is at a high level, transistor 62 is turned on and transistor 64 is turned off.

The other signal current taken out to the other output terminal of the differential amplifier 55 is supplied to the base of the transistor 74 through a circuit configuration similar to the configuration related to the one signal current described above. That is, transistors 66.67, 69.72 corresponding to the transistors 56, 57, 59.62 are provided, constant current sources 58 and 60 and corresponding constant currents tA 68 and 70 are provided, and a resistor 61 and a corresponding resistor 71 are provided. is provided.

The emitters of transistors 64 and 74 are grounded, and capacitor 6 is inserted between their collectors. Further, respective collectors of transistors 64 and 74 are connected to respective collectors of transistors 75 and 76. A predetermined DC voltage source 77 is connected to the bases of each of transistors 75 and 76. The emitters of transistors 75 and 76, respectively, are connected to the collectors of transistors 78 and 79.
It is connected to a power supply line 52 via the emitters.

One output voltage of the differential output voltage taken out across the capacitor 6 is connected to the Darlington contact Vi81 and the constant current source 8.
2, and the output signal of this emitter follower connection is fed to the transistor 83 . It is supplied to the base of a transistor 86 via an emitter follower connection consisting of a transistor 84 as a level shift diode and a constant current source 85. The emitter of transistor 86 is grounded via resistor 87, and its collector is connected to power supply line 51.

Regarding the other output voltage of the differential output voltages taken out across the capacitor 6, a connection similar to that of the above-mentioned one output voltage is provided. That is, Darlington Connection 91
and constant current #92 constitute an emitter-follower connection, and transistor 93 is a diode-connected transistor 9.
4 and a constant current source 95 constitute another emitter follower connection, and the output voltage via the other emitter follower connection is connected to the base of a transistor 96. The emitter of the transistor 96 is grounded via a resistor 97, and the collector thereof is connected to the power supply line 51.

Transistor 86 and transistor 96 are emitter follower transistors, and a differential output voltage is taken out from the respective emitters of transistors 86 and 96. Further, for midpoint control, the emitters of transistors 86 and 96 are connected via resistors 88 and 98 of equal value, and a midpoint potential is taken out from the connection point of resistors 88 and 98. The resistors 88 and 98 constitute a resistance adder circuit.

This midpoint potential is supplied to the base of one transistor 101 of the differential amplifier 100. A reference voltage source 103 corresponding to the midpoint potential to be controlled is connected to the base of the other transistor 102 of the differential amplifier 100. 104 is a constant current source of the differential amplifier 100.

The collector of transistor 101 is connected to power supply line 52, and the collector of transistor 102 is connected to transistor 1.
Connected to the collector of 05. The emitter of transistor 105 is connected to power supply line 52.

The base of this transistor 105 is commonly connected to the bases of the aforementioned transistors 78 and 79 to form a current mirror circuit. Transistor 106 is hre
(Emitter grounded current amplification factor) Connected for cancellation.

Further, output voltages taken out from the respective emitters of transistors 86 and 96 are supplied to the bases of transistors 111 and 112 forming a Gilbert type adder circuit. Transistors 111 and 112 constitute a differential amplifier, and their respective collectors are connected to transistors 113 and 114.
connected to the emitter of Transistors 113 and 11
A common DC voltage source 115 is connected to the base of 4,
The collectors of each of transistors l 13 and 114 are connected to power supply line 52 .

The collectors of transistors 111 and 112 are connected to the bases of transistors 116 and 117, and a constant current source is connected to a common connection point between the emitters of transistors 116 and 117. The collector of transistor 116 is connected to power supply line 52, and the collector of transistor 117 is connected to power supply line 52 via diode-connected transistor 118. The addition output current taken out to the collector of transistor 117 is
8 and a transistor 119 to the output terminal 10.

In the embodiment of the present invention described above, the differential signal current extracted by the differential amplifier 55 corresponds to the difference between the input voltage applied to the input terminal 2 and the reference voltage. This differential signal current is converted into (1/X) times as small a current as the collector current of the transistors 64 and 74, respectively.

The base-emitter voltage of transistor 56 is VBEI.
Let the voltage between the base and emitter of the transistor 57 be VIE2, the constant current of the constant current source 58 be 11, the constant current of the constant current source 60 be xl, and the voltage between the base and emitter of the transistor 59 be Vo. , transistor 6
The base-emitter voltage of transistor 64 is VBt4, and the constant current that flows when transistor 64 is on is . Then, the base potential Va of the transistor 61 and the transistor 59
The emitter potential vb of has the following relationship.

(k: Boltzmann constant, T: absolute temperature, q: electron charge, I: saturation current) From the above equation, (Io = I+ /x). Therefore, (
By setting X>1), the current ■ is reduced to (1/X) of 11. can be passed through transistor 64. When turning off the current I0, the transistor 62 is turned on.

Other signal currents among the differential signal currents are similarly reduced to (1/X) and flow through the transistor 74. Further, since the capacitor 6 is directly connected to the collector of each of the transistors 64 and 74, the switching speed is increased, and the collector current of the transistors 64 and 74 can be set to a small current, for example, 40 (nA). . Therefore, it is possible to make the time constant longer than before.

Further, control is performed such that the midpoint potential of the capacitor 6 is always located at the center potential of the dynamic range, so that the dynamic range of the output can be effectively utilized. As shown in FIG. 5, the respective DC potentials at both ends of the capacitor 6 are set to VA, V, and the respective emitter potentials (DC potentials) of the transistors 86 and 96 are set to V, , V. The midpoint control will be described below, assuming that the reference voltage from the reference voltage source 103 is Vr.

Potentials VA and ■8 are DC equal, and potentials ■,
and V are the transistors 86 and 9 connected between the bases and emitters of the plurality of emitter follower connected transistors.
However, by canceling the base-emitter voltage, (■E = V, = V, =
V. ).

The values of the resistor 88 and the resistor 98 are made equal, and the potential at the connection point between the two is assumed to be . Let Vt be the midpoint potential of the capacitor 6 to be controlled, and let it be (■[=Vr).

During normal operation, when a voltage change .alpha. occurs due to the signal current, it becomes (vA÷Vt+V.alpha., V,=Vt-.alpha.). Therefore, VE = V2 (V4 + Vs ) = 'A (Vc +
Since V6 ) = V t (V L = V r),
Transistors 101 and 102 of differential amplifier 100 are balanced.

Assuming that the constant current tXxoh is 212, the transistor 75 is
A constant current I0 flows through each of transistors 64 and 76, and is controlled to balance the currents of transistors 64 and 74, respectively.

Further, when the potentials of both VA and 6 are increased by Vβ, that is, v,=vt+vα×βV,=Vt−Vα+β, then v,=vt+vβ. As the base potential of the transistor 101 increases (■β), the currents flowing through the transistors 75 and 76 both decrease from (2). Therefore, the potential vA and ■
, is lowered, and negative feedback is applied to suppress the rise in potential Vβ.

Furthermore, even if the potentials of both VA and V drop by ■β, contrary to the above, the currents flowing through the transistors 75 and 76 both increase more than IZ, so that the potential decreases V
Negative feedback is applied to suppress β.

As described above, the midpoint potential ■t of the capacitor 6 is always controlled to (Vt=Vr) and maintained at the center of the dynamic range.

Although omitted in FIG. 5, the AFCID circuit 2
The ID error signal from 0 (see FIG. 3) is added across capacitor 6 with current addition.

[Effects of the Invention] According to the present invention, by adopting a balanced configuration, the dynamic range of the output can be twice that of a non-balanced configuration. Therefore, AFC circuit or A
When generating VCO control signals like a PC circuit,
The width of change in the oscillation frequency of the VCO is doubled, making it possible to cope with variations in the characteristics of the VCO.

Furthermore, if the capacitor is directly connected to the collector of the transistor that switches the current, as in the above embodiment, the charging/discharging current of the capacitor can be minimized, and the time constant can be made longer. becomes possible.

[Brief explanation of drawings]

Fig. 1 is a connection diagram of an embodiment of this invention, Fig. 2 is a connection diagram showing an equivalent circuit of an embodiment of this invention, and Figs.
The figure shows a connection diagram and a frequency characteristic route diagram showing the configuration when this invention is applied to an AFC circuit filter, Fig. 5 is a connection diagram showing a specific connection of an embodiment of the invention, and Fig. 6 is a conventional FIG. 7 is a connection diagram showing specific connections of a conventional integrating circuit. Explanation of main symbols in the drawings 1: Differential amplifier, 2: Input terminal, 4: Constant current source,
6: Capacitor, 7, 8: Bathophone circuit, 9: Adder circuit, lO: Output terminal. Agent Patent Attorney Tadashi Sugiura Tomo - Toro Hiroshi T Reikuchi Figure 1 Figure 2 Characteristics of F41L 1 Figure 4 Sumitomo's integral circuit Figure 6 Conventional product conversion ζ Figure 1

Claims (1)

[Claims] A differential amplifier having a capacitor connected between one output terminal and the other output terminal, and one output terminal and one input terminal of the differential amplifier are connected via a first buffer circuit. and an adder from which the other output terminal and the other input terminal of the differential amplifier are connected via a second buffer circuit, and an output signal is taken out.