JP3460876B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device (LSI).
More specifically, the present invention relates to a semiconductor device including a flip-flop type phase shifter, or a semiconductor device including a flip-flop type phase shifter and a Gilbert cell type frequency multiplier.

In digital radio communication technology, a quadrature carrier is required at the time of modulation and demodulation of a signal, and a semiconductor device for digital radio communication equipment requires a phase shifter for generating the quadrature carrier. The phase shift accuracy of the phase shifter, that is, the fact that the two carriers have different phases by exactly 90 ° directly affects the modulation / demodulation accuracy and influences the communication quality. Therefore, the phase shift accuracy of the phase shifter is improved. There is a need.

[0003]

2. Description of the Related Art FIG. 11 shows a conventional flip-flop type phase shifter 12 formed on a semiconductor device 11. The phase shifter 12 includes an input buffer 13 and a frequency dividing circuit 14. The input buffer 13 includes an input differential circuit 15 and an emitter follower circuit 16. The differential circuit 15 has a pair of NPN transistors 18 and 19 and an activation transistor 21 formed of an NPN transistor. NP
The emitters of N-transistors 18 and 19 are coupled, and both emitters are connected to the collector of activation transistor 21. The collectors of the NPN transistors 18 and 19 are connected via resistors to a power supply VCC as a high potential power source, and the emitters of the activation transistor 21 are connected via resistors to a ground GND as a low potential power source. NPN
Complementary signals IN and IN bar having a predetermined frequency are input to the bases of the transistors 18 and 19.

When the activation transistor 21 is turned on based on the reference voltage V _B2 , the differential circuit 15 is activated and NP
Complementary signal I from the collectors of N transistors 18 and 19
A pair of amplified signals VA and VA, which are obtained by amplifying N and IN bars, are output to the emitter follower circuit 16.

The emitter follower circuit 16 includes NPN transistors 22 and 23 and activation transistors 24 and 25 which are NPN transistors. The collector of the NPN transistor 22 is connected to the power supply VCC, the emitter of the transistor 22 is connected to the collector of the activation transistor 24, and the base of the transistor 22 is connected to the collector of the NPN transistor 18 to input the amplified signal VA. Has been done. The collector of the NPN transistor 23 is connected to the power supply VCC, the emitter of the transistor 23 is connected to the collector of the activation transistor 25, and the base of the transistor 23 is connected to the collector of the NPN transistor 19 so that the amplified signal VA bar is supplied. It has been entered. The emitters of the activation transistors 24 and 25 are connected to the ground GND via resistors, respectively.

When the activation transistors 24 and 25 are turned on based on the reference voltage V _B1 , the emitter follower circuit 1
6 is activated and outputs complementary signals VO and VO bar having the same frequency as the input signals IN and IN bar to the frequency dividing circuit 14 from the emitters of the NPN transistors 22 and 23.

The frequency dividing circuit 14 comprises four differential circuits 26, 2
7, 28, 29, an activation circuit 30, an emitter follower circuit 31, and activation transistors 32, 33, 34 made of NPN transistors. A plurality of (four in FIG. 11) activation transistors 34 are provided. The activation circuit 30 includes two differential circuits 30A and 30B,
The output signal VO is input to the bases of the NPN transistors of one of the differential circuits 30A and 30B.
The output signal VO bar is input to the bases of the other NPN transistors of A and 30B.

When the activation transistors 32, 33 and 34 are turned on based on the reference voltage V _B1 , the frequency dividing circuit 14 is activated. Then, the activation circuit 30 outputs the output signals VO and V.
The differential circuits 26 and 29 and the differential circuit 2 based on O bar
7 and 28 are activated alternately.

The emitter follower circuit 31 has four NPNs.
The transistors 35, 36, 37 and 38 are provided. NPN
The transistors 35-38 are the four differential circuits 26-2.
9 is turned on and off based on the operation of 9, and the output signals VO, V
Carriers L1 to L4 having a frequency of O bar, that is, a frequency that is half the frequency of the input signals IN and IN bar are respectively output. If the phase of the carrier L1 is 0 degrees, the phase of the carrier L2 is 90 degrees, and the carrier L3
Is 180 degrees, and the phase of the carrier L4 is 270 degrees.

[0010]

In order for the flip-flop type phase shifter 12 configured as described above to output the carriers L1 to L4 which are 90 degrees out of phase with each other,
In principle, perfect symmetry of the circuit is required. The symmetry also includes that they are partially the same. That is, input buffer 1
It is necessary that the characteristics and layout of the transistors that form the differential circuit 15 and the emitter follower circuit 16 of FIG. Further, the four differential circuits 26 to 29 and the differential circuit 30 which configure the frequency dividing circuit 14
It is necessary that the layouts of A and 30B are symmetrical, and that the characteristics and layout of the transistors forming the differential circuits 26 to 29, the differential circuits 30A and 30B, and the emitter follower circuit are symmetrical.

However, in an actual semiconductor device, since there are asymmetries due to layout restrictions and variations in element characteristics due to the manufacturing process, the phases of the carriers L1 to L4 output from the phase shifter 12 are different. The difference is not exactly 90 degrees, and the phase shift accuracy decreases.

Also, a flip-flop type phase shifter 1
2 includes spurious signals (unnecessary frequency components) with respect to the input signals IN and IN bar, in particular, spurious signals having an even multiple of the frequency of the input signals IN and IN bar, the input signal IN and IN bar as shown in FIG. The interval at which the amplitude of IN bar changes and the levels of the input signals IN and IN bar cross, that is,
The duties t1 to t4 have different values. Therefore, as shown in FIG. 12, the phase of the carrier L2 deviates from the ideal value indicated by the two-dot chain line at t2 as indicated by the chain line, and the phase shift accuracy decreases.

Also, a flip-flop type phase shifter 1
In No. 2, the duty of the input signals IN and IN bar differs depending on the value of the bias voltage of the input signals IN and IN bar, and the phase shift accuracy decreases. That is, as shown in FIG. 13, when the input signals IN and IN bar of the phase shifter 12 have the same bias voltages V _D11 and V _D12 , the phase difference α between the carriers L1 and L2 is 90 degrees. However, as shown in FIG. 14, the input signal I of the phase shifter 12 is
When the bias voltage V _{D11 of} N is higher than the bias voltage V _D12 of the input signal IN bar, the carriers L1 and L
The phase difference β of 2 becomes less than 90 degrees, and the phase shift accuracy decreases. Further, as shown in FIG. 15, when the bias voltage V _D12 of the input signal IN bar of the phase shifter 12 is higher than the bias voltage V _D11 of the input signal IN, the carrier L
The phase difference γ between 1 and L2 becomes larger than 90 degrees, and the phase shift accuracy decreases.

Since the flip-flop type phase shifter 12 divides the frequency of the input signals IN and IN to ½ and outputs the carriers L1 to L4, in order to obtain a carrier of a desired frequency, the phase is shifted. A semiconductor device is often provided with a Gilbert cell type frequency multiplier for doubling the frequency of the input signal in the preceding stage of the shifter 12. However, the output of this frequency multiplier usually contains spurious, and an offset (deviation) occurs in the bias voltage of the differential output. Therefore, if the Gilbert cell type frequency multiplier and the phase shifter are connected and the output of the frequency multiplier is input to the phase shifter, the duty of the input signals IN and IN bar will be different and the phase shift accuracy will be reduced. .

As described above, the reduction in the phase shift accuracy of the carrier output from the phase shifter lowers the accuracy of modulation / demodulation, resulting in an increase in error rate and a decrease in communication quality. The present invention has been made to solve the above problems,
An object of the invention is to provide a semiconductor device capable of improving the phase shift accuracy of the phase shifter.

[0016]

FIG. 1 is a diagram for explaining the principle of the present invention. The phase shifter comprises an input buffer 1 and a frequency dividing circuit 5. The input buffer 1 includes an input differential circuit 2 having a pair of bipolar transistors 3 and 4, inputs complementary signals IN and IN bar to the bipolar transistors 3 and 4, and a pair of signals based on the complementary signals IN and IN bar. V
Outputs O and VO bars. The frequency divider circuit 5 outputs the output signal VO,
The frequency of the VO bar is divided into halves to output a pair of carriers L1 and L2 whose phases are different by 90 degrees. The bias circuit 6 is for adjusting the bias voltage of the pair of complementary signals IN and IN bar.

Further, the bias circuit, based on a control voltage signal to generate a pair of bias voltage, and a differential circuit for supplying a pair of bipolar transistors of the differential circuit for input to the pair of bias voltage .

[0018] Then, the control voltage signal is generated by the voltage generating resistor externally against the high potential power supply and the low-potential power source.

According to the second aspect of the invention, the phase shifter has an input buffer.
It includes a buffer 1 and a frequency dividing circuit 5. Input buffer 1 is one
Input differential with paired bipolar transistors 3, 4
Complementary to bipolar transistors 3 and 4
Input signals IN and IN bar, and complementary signals IN and IN bar
To output a pair of signals VO and VO bar based on. Dividing
The path 5 divides the frequency of the output signals VO and VO bar in half.
A pair of carriers L1 and L2 that rotate around and have a phase difference of 90 degrees
Output. The bias circuit 6 includes a pair of complementary signals IN, IN
It is for adjusting the bias voltage of the bar. That
And a Gilbert cell type frequency multiplier for outputting a complementary signal obtained by multiplying the frequency of the input signal by two. The complementary signal output from the frequency multiplier is directly input to a pair of bipolar transistors of the input buffer, and a bias circuit is provided. Is a capacitance that couples the emitters of a pair of bipolar transistors of the input differential circuit.

According to the invention of claim 3 , the phase shifter has an input buffer.
It includes a buffer 1 and a frequency dividing circuit 5. Input buffer 1 is one
Input differential with paired bipolar transistors 3, 4
Complementary to bipolar transistors 3 and 4
Input signals IN and IN bar, and complementary signals IN and IN bar
To output a pair of signals VO and VO bar based on. Dividing
The path 5 divides the frequency of the output signals VO and VO bar in half.
A pair of carriers L1 and L2 that rotate around and have a phase difference of 90 degrees
Output. The bias circuit 6 includes a pair of complementary signals IN, IN
It is for adjusting the bias voltage of the bar. That
And a Gilbert cell type frequency multiplier for outputting a complementary signal obtained by multiplying the frequency of the input signal by two. The complementary signal output from the frequency multiplier is directly input to a pair of bipolar transistors of the input buffer, and a bias circuit is provided. Is a load including at least an inductance connected to the collector of the bipolar transistor which constitutes the differential circuit of the Gilbert cell type frequency multiplier.

[0021]

According to the first aspect of the present invention, the bias voltage of the complementary signals IN, IN bar input to the input buffer 1 of the phase shifter is adjusted by the bias circuit 6, and the complementary signal I
The duty of N and IN bars changes. As a result, the phase difference between the pair of carriers L1 and L2 output from the frequency dividing circuit 5 is adjusted.

Further, a pair of bias voltage based on the voltage of the control voltage signal is generated.

Then , a pair of control voltage signals is generated across the voltage generating resistor, a pair of bias voltages is generated based on the pair of control voltage signals, and is supplied to a pair of bipolar transistors of the input differential circuit. To be done. The voltage value of the pair of control voltage signals changes by changing the resistance value of the voltage generating resistor, and the pair of bias voltages changes based on the change of the control voltage signal.

According to the invention of claim 2 , in the bias circuit,
Therefore, the complementary signal input to the input buffer of the phase shifter
Bias voltage is adjusted to change the duty of the complementary signal.
Turn into. As a result, a pair of capacitors output from the frequency divider circuit.
The rear phase difference is adjusted. Then, by providing a Gilbert cell type frequency multiplier that outputs a complementary signal obtained by multiplying the frequency of the input signal by two, the carrier of the desired frequency can be obtained. The complementary signal of the frequency multiplier usually contains spurious and also causes an offset in the bias voltage of the differential output.
However, even if there is a bias voltage offset in the complementary signal, the offset is absorbed by the capacitance being charged. Therefore, the duty of the complementary signal of the frequency multiplier has a constant value, the phase difference of the carrier becomes 90 degrees, and the phase shift accuracy of the phase shifter is improved.

According to the invention of claim 3 , in the bias circuit,
Therefore, the complementary signal input to the input buffer of the phase shifter
Bias voltage is adjusted to change the duty of the complementary signal.
Turn into. As a result, a pair of capacitors output from the frequency divider circuit.
The rear phase difference is adjusted. The voltage generated in the inductance by the offset current can change the interval at which the levels of the pair of input signals of the phase shifter intersect, and the phase shift accuracy of the phase shifter is improved.

[0026]

Embodiments of the present invention will be described below with reference to FIGS. For convenience of explanation, in each embodiment, the same components as those of the phase shifter 12 of FIG. 11 are designated by the same reference numerals, and the description thereof will be partially omitted, and the same components in each embodiment will also be designated by the same reference numerals. Is attached and part of the description thereof is omitted.

[First Embodiment] FIG. 2 shows a semiconductor device 41 of the first embodiment. The input buffer 4 is provided on the semiconductor device 41.
A flip-flop type phase shifter 42 including the frequency division circuit 3 and the frequency dividing circuit 14 is formed. The input buffer 43 includes a differential circuit 44 as a bias circuit and an input differential circuit 15
And an emitter follower circuit 16.

The differential circuit 44 has a pair of NPN transistors 45 and 46 and activation transistors 47 and 48 which are NPN transistors. NPN transistor 4
The emitters of 5,46 are resistors R for lowering the amplification factor.
1 and the emitters of both transistors 45 and 46 are connected to the collectors of activation transistors 47 and 48, respectively. The collectors of the NPN transistors 45 and 46 are the NPN transistors 18 and 1 of the differential circuit 15.
9 and the collectors of both transistors 45 and 46 are connected to a power source Vcc as a high potential power source via a resistor. The emitters of the activation transistors 47 and 48 are connected to a ground GND as a low potential power source via a resistor. The control voltage signal V _C is input to the base of the NPN transistor 45 from outside the semiconductor device 41, and the reference voltage signal Vr is input to the base of the NPN transistor 46. Control voltage signal V _C
The voltage value of can be changed.

When the activation transistors 47 and 48 are turned on based on the reference voltage V _B3 , the differential circuit 44 is activated. The differential circuit 44 generates a pair of bias voltages based on the control voltage signal V _C , and supplies the pair of bias voltages to the bases of the NPN transistors 18 and 19 of the differential circuit 15.

When the activation transistor 21 is turned on based on the reference voltage V _B2 , the differential circuit 15 is activated and NP
Complementary signal I from the collectors of N transistors 18 and 19
A pair of amplified signals VA and VA, which are obtained by amplifying N and IN bars, are output to the emitter follower circuit 16.

When the activation transistors 24 and 25 are turned on based on the reference voltage V _B1 , the emitter follower circuit 16 is activated, and the emitters of the NPN transistors 22 and 23 generate the same signals as the input signals IN and IN bar. Complementary signals VO and VO having a frequency are output to the frequency dividing circuit 14.

When the activation transistors 32, 33 and 34 are turned on based on the reference voltage V _B1 , the frequency dividing circuit 14 is activated. Then, the activation circuit 30 outputs the output signals VO and V.
The differential circuits 26 and 29 and the differential circuit 2 based on O bar
7 and 28 are activated alternately.

The NPN transistors 35 to 38 are turned on and off based on the operation of the four differential circuits 26 to 29, and are halved in frequency of the output signals VO and VO, that is, the frequencies of the input signals IN and IN bar. The carriers L1 to L4 having a frequency of 1 are output respectively.

The phase difference between these carriers L1 to L4 is
In principle, assuming that the phase of the carrier L1 is 0 degrees, the phase of the carrier L2 is 90 degrees and the phase of the carrier L3 is 180 degrees.
Further, the phase of the carrier L4 is 270 degrees. In the actual semiconductor device 41, because of circuit asymmetry due to layout restrictions and element characteristic variations due to the manufacturing process, the phase difference between the carriers L1 to L4 output from the phase shifter 42 is small. Not exactly 90 degrees.

Therefore, in the phase shifter 42 configured as described above, the phases of the carriers L1 to L4 are set to the semiconductor device 4.
1 is monitored from the outside, and the control voltage signal V _C is adjusted so that the phase difference between the carriers L1 to L4 is 90 degrees. Then, the values of the pair of bias voltages input to the differential circuit 15 change based on the value of the control voltage signal V _C , and the duty of the input signals IN and IN bar changes accordingly, so that the carriers L1 to L4 are changed. Phase difference of 9
It can be 0 degree, and the phase shift accuracy can be improved. Therefore, the accuracy of modulation / demodulation based on the carriers L1 to L4 of the phase shifter 42 can be improved, the error rate can be reduced, and the communication quality can be improved.

[Second Embodiment] FIG. 3 shows a semiconductor device 39 of the second embodiment. The semiconductor device 39 includes the phase shifter 42 shown in FIG. 2, a phase detector 49, and a low pass filter (LPF) 50.

The phase detector 49 is composed of, for example, an exclusive OR (EX-OR) circuit, detects the phase of the carriers L1 and L2 of the phase shifter 42, one of the carriers L1 and L2 is at H level and the other is at L level. If it is a level, an H level signal is output, and if both carriers L1 and L2 are an L level or an H level, an L level signal is output.

The low pass filter 50 of the phase detector 49
Output voltage is smoothed to control voltage signal V _CThe phase shifter 42
Output to the carrier L of the phase shifter 42.
The phase difference between 1 and L2 is 90 degrees. In this example, the phase
The phase shift is performed by the detector 49 and the low-pass filter 50.
It is possible to automatically improve the phase shift accuracy of the input signal 42.

[Third Embodiment] FIG. 4 shows a semiconductor device 51 of a third embodiment. A flip-flop type phase shifter 52 including an input buffer 53 and the frequency dividing circuit 14 is formed on the semiconductor device 51. The input buffer 53 includes a differential circuit 54 as a bias circuit, an input differential circuit 15 and an emitter follower circuit 16.

The differential circuit 54 includes a pair of NPN transistors 45 and 46, activation transistors 47 and 48 composed of NPN transistors, a resistor R2 connected to the power supply VCC, a resistor R3 connected to the ground GND, and resistors R2 and R2.
3 is provided with a voltage generating resistor Re externally attached. N
The bases of the PN transistors 45 and 46 are voltage generating resistors R
It is connected via e.

Therefore, between the power supply VCC and the ground GND.
Resistance R2, voltage generation resistance Re and resistance connected in series
The voltage between the power supply VCC and the ground GND is divided by R3.
The control voltage signal V is applied to the upper end of the voltage generating resistor Re._C1
Is generated, the control voltage signal is generated at the lower end of the voltage generating resistor Re.
V_C2Is generated. Control voltage signal V_C1Is the NPN transition
It is input to the base of the star 45 and is supplied to the reference voltage signal Vr.
Instead, control voltage signal V _C2Is the NPN transistor 46
Input. Control voltage signal V_C1, V_C2The voltage value of
Can be changed by changing the resistance value of voltage generation resistance Re
Noh.

Therefore, also in the phase shifter 52 of this embodiment, the phases of the carriers L1 to L4 are monitored from the outside of the semiconductor device 51, and the voltage generating resistors are set so that the phase difference between the carriers L1 to L4 is 90 degrees. Adjust the resistance value of Re. Then, the control voltage signal V _C1 as shown in FIG. 5, V the value of _C2 is changed, the control voltage signal V _C1, V pair of input to the differential circuit 15 based on the value of _C2 bias voltage V _D1, The value of V _D2 changes. Bias voltage V _D1 , V _D2
The duty of the input signals IN and IN bar changes according to the change of the signal, and the phase difference between the carriers L1 to L4 is 90%.
Therefore, the phase shift accuracy can be improved.

[Fourth Embodiment] FIG. 6 shows a semiconductor device 55 according to a fourth embodiment. The Gilbert cell type frequency multiplier 56 and the phase shifter 4 are provided on the semiconductor device 55.
2 are formed. The frequency multiplier 56 and the phase shifter 42 are connected by externally attached capacitors C3 and C4.

The frequency multiplier 56 includes differential circuits 57, 58,
63, input transistor 6 consisting of NPN transistor
6. Activation transistor 6 consisting of NPN transistor
7 to 71, and outputs complementary signals DO and DO bar which are obtained by multiplying the frequency of the input signal Lin by two. The Gilbert cell type frequency multiplier is thus provided with the upper differential circuit and the lower differential circuit.

The collector of the input transistor 66 is the power supply V
The transistor 66 is connected to CC, the emitter of the transistor 66 is connected to the collector of the activation transistor 68, and the oscillation signal Lin is input to the base from a voltage controlled oscillator or the like (not shown). The emitter of the activation transistor 68 is connected to the ground GND via a resistor. The collector of the activation transistor 67 is connected to the power supply Vcc via a resistor, and the emitter is connected to the ground GND via the resistor.

The emitters of the pair of NPN transistors 64 and 65 of the differential circuit 63 are coupled to each other, and both transistors 6
The emitters of 4,65 are connected to the collectors of the activation transistors 69,70. Activation transistor 69,
The emitter of 70 is grounded via a resistor.
It is connected to the.

A pair of NPN transistors of the differential circuit 57
The emitters of 58 and 59 are connected, and both emitters are NPN.
It is connected to the collector of the transistor 64. Differential times
Emission of a pair of NPN transistors 61 and 62 on the path 60
Are connected and both emitters of the NPN transistor 65
It is connected to the collector. NPN transistor 58,
The collector of 61 is a power source V via a resistor R4 as a load.
It is connected to CC and collects NPN transistors 59 and 62.
Is connected to the power supply VCC through a resistor R5 as a load.
ing. The bases of the NPN transistors 58 and 62 are capacitors
Connected to the emitter of the input transistor 66 via
Together with the bias voltage V through the resistor _B6Is entered
It The bases of the NPN transistors 59 and 61 are connected via capacitors.
Connected to the ground GND via a resistor
Bias voltage V_B6Is entered.

When the activation transistors 67 and 68 are turned on based on the reference voltage V _B4 and the activation transistors 69 to 71 are turned on based on the reference voltage V _B5 , the frequency multiplier 56 is activated. The frequency multiplier 56 has N
Input signal L from the collectors of PN transistors 58 and 61
The output signal DO obtained by doubling the frequency of in is output, and the output signal DO bar obtained by doubling the frequency of the input signal Lin is output from the collectors of the NPN transistors 59 and 62.

The phase shifter 42 inputs the complementary signals DO and DO bar as input signals IN and IN bar, and outputs carriers L1 and L2 having the same frequency as the input signal Lin. The semiconductor device 55 of this embodiment has the input signals IN, IN
The frequency of the bar is divided into two and the carriers L1 to L4 are divided.
A Gilbert cell type frequency multiplier 5 for doubling the frequency of the input signal is provided before the phase shifter 42 which outputs
By providing 6, a carrier having a desired frequency can be obtained. Also, the output signal D of the frequency multiplier 56
O and DO bars usually contain spurious,
An offset occurs in the bias voltage of the differential output. However, the phase shifter 42 has input signals IN, IN
Since the differential circuit 44 for adjusting the bias voltage of the bar is provided, the output signal DO of the frequency multiplier 56,
Even if the DO bar is input to the phase shifter 42, the carrier L
The phase difference between 1 and L2 can be 90 degrees, and the phase shift accuracy can be improved.

[Fifth Embodiment] FIG. 7 shows a semiconductor device 73 according to a fifth embodiment. The Gilbert cell type frequency multiplier 56 and the phase shifter 74 directly connected to the frequency multiplier 56 are formed on the semiconductor device 73.
The phase shifter 74 includes an input buffer 75 and the frequency dividing circuit 14
With. The input buffer 75 is an input differential circuit 78.
And the emitter follower circuit 16. The differential circuit 78 includes a pair of NPN transistors 18 and 19 and an NP.
Activation transistors 76 and 77 composed of N transistors
Have and. The emitters of the NPN transistors 18 and 19 are coupled via a capacitor C5 as a bias circuit, and the emitters of both transistors 18 and 19 are connected to the collectors of the activation transistors 76 and 77, respectively. N
The base of the PN transistor 18 is N of the frequency multiplier 56.
It is directly connected to the collectors of the PN transistors 59 and 62, and the output signal DO bar is input as the input signal IN. The base of the NPN transistor 19 is directly connected to the collectors of the NPN transistors 58 and 61 of the frequency multiplier 56, and the output signal DO is input as the input signal IN bar. The emitters of the activation transistors 76 and 77 are connected to the ground GND via a resistor.

When the activation transistors 76 and 77 are turned on based on the reference voltage V _B2 , the differential circuit 78 is activated, and a pair of amplifications are obtained by amplifying the complementary signals IN and IN bar from the collectors of the NPN transistors 18 and 19. Signals VA, V
The A-bar is output to the emitter follower circuit 16.

When the activation transistors 24 and 25 are turned on based on the reference voltage V _B1 , the emitter follower circuit 16 is activated and the emitters of the NPN transistors 22 and 23 generate the same signals as the input signals IN and IN bar. Complementary signals VO and VO having a frequency are output to the frequency dividing circuit 14.

Then, the frequency dividing circuit 14 outputs the input signal Lin.
It outputs carriers L1 to L4 having the same frequency as.
As described above, in this embodiment, the emitters of the NPN transistors 18 and 19 forming the input differential circuit 78 are connected to the capacitor C5.
Are joined by. Therefore, even if there is an offset (deviation) of the bias voltage in the output signals DO and DO bar, the offset is absorbed by being charged in the capacitor C5. Therefore, the duty of the input signals IN, IN bar becomes a constant value, the phase difference between the carriers L1 to L4 becomes 90 degrees, and the phase shift accuracy of the phase shifter 74 can be improved.

Further, since the semiconductor device 73 of this embodiment has one capacitor C5 built-in, the semiconductor device 73 having the frequency multiplier and the phase shifter can be miniaturized. [Sixth Embodiment] FIG. 8 shows a semiconductor device 79 of the sixth embodiment. The Gilbert cell type frequency multiplier 56 and the phase shifter 80 directly connected to the frequency multiplier 56 are formed on the semiconductor device 79. Phase shifter 8
Reference numeral 0 includes an input buffer 81 and the frequency dividing circuit 14.
The input buffer 81 includes an input differential circuit 78 and the emitter follower circuit 16. The emitters of the NPN transistors 18 and 19 are coupled to the semiconductor device 79 via a capacitor C6 as a bias circuit externally attached.

In the semiconductor device 79 of this embodiment, the emitters of the NPN transistors 18 and 19 forming the input differential circuit 78 are coupled by the externally attached capacitor C6. Therefore, even if the output signals DO and DO bar of the frequency multiplier 56 have a bias voltage offset, the offset is absorbed by being charged in the capacitor C6 as in the fifth embodiment. Therefore, the duty of the input signals IN and IN bar becomes constant, the phase difference between the carriers L1 to L4 becomes 90 degrees, and the phase shift accuracy of the phase shifter 80 can be improved.

In the semiconductor device 79 of this embodiment, 1
Two external terminals may be provided to externally attach one capacitor C6 to the semiconductor device 79.
Compared with 5, the number of capacitors and the number of external terminals can be halved, and the size of the semiconductor device 79 can be reduced.

[Seventh Embodiment] FIG. 9 shows a semiconductor device 83 according to a seventh embodiment. The Gilbert cell type frequency multiplier 84 and the phase shifter 1 are provided on the semiconductor device 83.
2 are formed. Differential circuit 15 of the phase shifter 12
The base of the NPN transistor 18 is a frequency multiplier 84.
Are directly connected to the collectors of the NPN transistors 59 and 62, and the output signal DO is input as the input signal IN. The base of the NPN transistor 19 of the differential circuit 15 is directly connected to the collectors of the NPN transistors 58 and 61 of the frequency multiplier 84 , and the output signal DO bar is the input signal I.
It is entered as N bar.

The frequency multiplier 84 is a differential circuit 57, 60 ,
63, input transistor 6 consisting of NPN transistor
6. Activation transistor 6 consisting of NPN transistor
7 to 71, and outputs complementary signals DO and DO bar which are obtained by multiplying the frequency of the input signal Lin by two.

The collectors of the NPN transistors 58 and 61 are connected to the power supply Vcc via the level shift resistor R6 as a load and the inductance 85. The level shift resistor R6 outputs the voltage values of the output signals DO and DO bar to the power source V.
This is for lowering the voltage value of CC. The collectors of the NPN transistors 59 and 62 have a capacitance C as a load.
7 and an inductance 85, and is connected to the power supply Vcc. Level shift resistor R6 and inductance 85
The node between and the node between the capacitance C7 and the inductance 85 are connected.

In the semiconductor device 83 of this embodiment, the duty of the input signals IN and IN bar of the phase shifter 12 can be changed by the voltage generated in the inductances 85 and 86 by the offset current, and the phase shift accuracy of the phase shifter 12 can be improved. Can be improved.

[Eighth Embodiment] FIG. 10 shows a semiconductor device 88 according to an eighth embodiment. On the semiconductor device 88, a Gilbert cell type frequency multiplier 93 and the phase shifter 12 are formed. The phase shifter 12 is the seventh embodiment.
The configuration is the same as the example, and the differential circuit 15 of the phase shifter 12 is directly connected to the frequency multiplier 93 as in the seventh embodiment.

The frequency multiplier 93 is the frequency multiplier 84.
Level shift resistor R6, inductance 85,
Instead of 86 and the capacitance C7, externally mounted inductances 89 and 90 as a load are provided. NPN transistor 5
The collectors of 8, 61 are connected to a reference power supply 91 via an inductance 89, and the collectors of NPN transistors 59, 62 are connected to a reference power supply 92 via an inductance 90.

In the semiconductor device 88 of this embodiment, by changing the pull-up voltage of the reference power sources 91 and 92, the duty of the input signals IN and IN bar of the phase shifter 12 can be changed, and the phase shifter 12 can be changed. The phase shift accuracy can be improved.

[0064]

As described in detail above, according to the invention of claim 1, the phase shift accuracy of the phase shifter can be improved.

[0065] Further, to generate a pair of bias voltage based on the voltage of the control voltage signal, it can be improved phase accuracy of the phase shifter.

Further , the control voltage signal can be generated by the voltage generating resistance, and the pair of bias voltages can be generated based on the control voltage signal to improve the phase shift accuracy of the phase shifter.

According to the second aspect of the present invention, a carrier having a desired frequency can be obtained, and the offset of the complementary signal of the frequency multiplier can be absorbed by the capacitance, so that the phase shift accuracy of the phase shifter can be improved.

According to the third aspect of the invention, the interval at which the levels of the pair of input signals of the phase shifter intersect can be changed by the voltage generated in the inductance by the offset current, and the phase shift accuracy of the phase shifter can be improved. .

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

FIG. 2 is a circuit diagram showing a phase shifter of the first embodiment.

FIG. 3 is a block diagram showing a semiconductor device of a second embodiment.

FIG. 4 is a circuit diagram showing a phase shifter of a third embodiment.

5 is a diagram showing the relationship between the external resistance value and the bias voltage in FIG.

FIG. 6 is a circuit diagram showing a semiconductor device of a fourth embodiment.

FIG. 7 is a circuit diagram showing a semiconductor device of a fifth embodiment.

FIG. 8 is a circuit diagram showing a semiconductor device of a sixth embodiment.

FIG. 9 is a circuit diagram showing a semiconductor device of a seventh embodiment.

FIG. 10 is a circuit diagram showing a semiconductor device of an eighth embodiment.

FIG. 11 is a circuit diagram showing a conventional phase shifter.

FIG. 12 is a waveform chart showing the relationship between an input signal and an output signal.

FIG. 13 is a waveform diagram showing a relationship between a bias voltage of an input signal and an output signal.

FIG. 14 is a waveform diagram showing a relationship between a bias voltage of an input signal and an output signal.

FIG. 15 is a waveform diagram showing the relationship between the bias voltage of the input signal and the output signal.

[Explanation of symbols]

1 Input Buffer 2 Input Differential Circuit 3, 4 NPN Bipolar Transistor 5 Frequency Divider 6 Bias Circuit 44 Differential Circuit 56, 84, 88 Frequency Multiplier 58, 59, 61, 62 Output Transistor 85 Inductance C5, C6 Capacitance Do, Do bar Complementary signal GND Ground as low potential power source IN, IN bar Complementary input signal L1, L2 Carrier Lin input signal Re Voltage generating resistance V _C Control voltage signal V _CC Power source as high potential power source

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03K 5/00

Claims (3)

(57) [Claims] 1. An input buffer comprising an input differential circuit having a pair of bipolar transistors, inputting complementary signals to the pair of bipolar transistors, and outputting a pair of signals based on the complementary signals, and the input buffer. The frequency of a pair of output signals of
In a semiconductor device including a phase shifter including a frequency divider circuit for outputting a pair of carriers that differ by 0 degrees, a bias circuit for adjusting a bias voltage of the pair of complementary signals is provided , and the bias circuit is a control circuit. A pair of bars based on the voltage signal.
Generate an bias voltage and apply the pair of bias voltages
Supply to a pair of bipolar transistors in the differential circuit for power
And a control voltage signal for the high-potential power supply and the low-potential power supply.
A semiconductor device that is generated by an external voltage generation resistor . 2. Having a pair of bipolar transistors
A differential circuit for input is provided and the pair of bipolar transistors
A complementary signal is input to the register and a pair based on this complementary signal is input.
Of the input buffer that outputs the signal of
The frequency of the pair of output signals is divided into halves to obtain a phase of 9
A frequency divider circuit for outputting a pair of carriers that differ by 0 degrees
In the semiconductor device provided with a phase shifter consisting of Ba for adjusting the bias voltage of the pair of complementary signal
Gill that provides an ias circuit and outputs a complementary signal that is obtained by doubling the frequency of the input signal
Bert cell type frequency multiplier
The complementary signal output from the input buffer is a pair of bypass signals of the input buffer.
The bias circuit is directly input to the polar transistor.
Is a pair of bipolar transistors of the differential circuit for input
A semiconductor device that is a capacitor that couples the emitters of 3. Having a pair of bipolar transistors
A differential circuit for input is provided and the pair of bipolar transistors
A complementary signal is input to the register and a pair based on this complementary signal is input.
Of the input buffer that outputs the signal of
The frequency of the pair of output signals is divided into halves to obtain a phase of 9
A frequency divider circuit for outputting a pair of carriers that differ by 0 degrees
In the semiconductor device provided with a phase shifter consisting of Ba for adjusting the bias voltage of the pair of complementary signal
Gill that provides an ias circuit and outputs a complementary signal that is obtained by doubling the frequency of the input signal
Bert cell type frequency multiplier
The complementary signal output from the input buffer is a pair of bypass signals of the input buffer.
The bias circuit is directly input to the polar transistor.
Is a differential circuit of the Gilbert cell type frequency multiplier.
Connected to the collector of the bipolar transistor
A semiconductor device that is a load including at least an inductance .