JP3267897B2 - Gain control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gain control circuit applied to an automatic control circuit of a semiconductor integrated circuit requiring low power operation such as a portable terminal.

[0002]

2. Description of the Related Art As a conventional gain control circuit in which the DC potential level of a control signal output terminal is constant, for example, a circuit as shown in FIG. 2 is known. The conventional gain control circuit shown in FIG. 2 is provided between the emitters of the transistors Q9 and Q10.
A first differential amplifier circuit is formed by connecting the resistor R5, the bases of the transistors Q9 and Q10 are used as input terminals 14 and 15, respectively, of the input signal, and the connection point between the transistor Q9 and the resistor R5 and the transistor Q10 and the resistor R5 are connected. The constant current sources 18 and 19 are connected to the connection points, respectively. On the other hand, the emitters of the transistor Q11 and the transistor Q12 are commonly connected to form a second differential amplifier circuit, and the transistor Q11
And the transistor Q12
9 collectors are connected. Similarly, the transistor Q13
And the emitter of the transistor Q14 are connected in common.
And a collector of the transistor Q10 is connected to a common emitter of the transistors Q13 and Q14. The bases of the transistors Q11 and Q14 and the bases of the transistors Q12 and Q13 are commonly connected to control voltage input terminals 12 and 13, respectively. The collectors of the transistors Q12 and Q13 are common, and are connected to the power supply terminal 11 via the resistor R8 and to the base of the transistor Q15. The collectors of the transistors Q11 and Q14 are respectively connected to a resistor R6,
Connected in common via R7 and connected to the emitter of transistor Q15. The collector of the transistor Q15 is connected to the power supply terminal 11. Transistor Q11 and resistor R6
And the connection point between the transistor Q14 and the resistor R7 are output terminals 16 and 17 for outputting a signal controlled by the control voltage, respectively.

In the circuit shown in FIG. 2, the voltage of the power supply terminal 11 is VCC, the current values of the constant current sources 18 and 19 are I,
The base-emitter voltage of the transistor Q15 is VBE
15, the value of the resistors R6 and R7 is RC, the value of the resistor R8 is RC / 2, and the value of the change in the small current due to the input signal is ΔI, the output voltage VO appearing at the output terminal 16 is obtained.
Is given by the following equation (1). VO = VCC-I.RC-VBE15 + A.RC..DELTA.I (1) where A is given by the following equation (2). A = EXP (Vd / VT) / (1 + EXP (Vd / VT)) (2) where Vd is the potential difference between the control voltage input terminals 12 and 13, and VT = kT / q. , K is the Boltzmann constant, T is the absolute temperature, and q is the amount of charge.

The amplitude vo of the output signal appearing at the output terminal 16 is given by the following equation (3) since it can be expressed only by the term of the minute current change due to the input signal of the above equation (1). vo = A · RC · ΔI (3) According to the above equation (3), the amplitude vo of the output signal changes depending on the potential difference Vd between the control voltage input terminals 12 and 13. Assuming that the mutual conductance of the differential amplifier circuit composed of the transistors Q9 and Q10 and the resistor R5 is gm, the differential gain Av
Is given by the following equation (4). Av = A · gm · RC (4) Therefore, as shown in the above equation (4), the control voltage input terminal 1
The differential gain can be controlled by the potential difference Vd between 2 and 13. If the DC potential level of the output terminal 16 is VOD, VOD
Is given by the following equation (5). VOD = VCC-I.RC-VBE15 (5) As shown in the equation (5), the DC potential level of the output terminal 16 is constant regardless of the potential difference Vd between the control voltage input terminals 12 and 13. It is.

[0005]

As described above, in the conventional gain control circuit shown in FIG. 2, the DC potential level of the output terminal can be kept constant regardless of the potential difference of the control voltage input terminal. At least three stages of npn transistors must be connected between the power supply terminal and GND, or four stages if npn transistors are used as the constant current source, the npn transistors must be connected in cascade, and the potential difference between the power supply terminal and GND is increased. There was a problem that it had to be secured. This leads to an increase in power consumption and is not suitable for a gain control circuit mounted on a semiconductor integrated circuit constituting a portable terminal or the like used for mobile communication.

[0006]

SUMMARY OF THE INVENTION The present invention solves such a conventional problem and provides a gain control circuit capable of maintaining a constant DC potential level of an output terminal at a low power with a gain control. The purpose is to:

In order to achieve the above object, the present invention provides a first differential circuit comprising a first and a second transistor for supplying an input signal to a base and a resistor connecting the emitters of the transistors. A dynamic amplifier circuit, and second and third differential amplifier circuits having third, fourth, fifth, and sixth transistors, each having a base connected to the control voltage input terminal to control an output signal level; A fourth differential amplifier circuit comprising seventh and eighth transistors for changing a DC current using a resistor as a load, and a DC potential of the first and second output terminals regardless of the control voltage during gain control. The collector current ratio of the seventh and eighth transistors constituting the fourth differential amplifier circuit is controlled so that the level becomes constant.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention connects first and second transistors for supplying an input signal to a base and a first resistor for connecting the emitters of the transistors to each other. A first differential amplifier circuit, and third, fourth, fifth, and sixth transistors, the bases of which are first and second control voltage input terminals, respectively. A second and third differential amplifier circuit for controlling an output signal level using a resistor as a load and outputting an output signal to first and second output terminals; and a third, fourth, fifth, and sixth differential amplifier circuit. A gain control circuit in which a common emitter of each transistor is connected to a collector of each of the first and second transistors is connected to a gain control circuit using a fourth resistor as a load.
A fourth differential amplifier circuit including an eighth transistor is added, and the ratio of the DC current flowing through the collector of the fourth resistor and the collector of the seventh transistor is simultaneously changed at the time of gain control. A gain control circuit characterized in that the DC potential level of the first and second output terminals is constant, and that the DC potential level of the output terminal can be kept constant during low-power gain control. Has an action.

According to a second aspect of the present invention, there is provided a first differential amplifier comprising a first resistor connected between emitters of first and second transistors for supplying an input signal to a base. A second differential amplifier circuit configured by connecting the emitter of the third and fourth transistors to the collector of the first transistor, and the emitter of the fifth and sixth transistors to be common; A third differential amplifier circuit configured to be connected to the collector of the second transistor, a fourth differential amplifier circuit configured to share the emitters of the seventh and eighth transistors, and the first and second differential amplifier circuits. A first and a second constant current source connected to a connection point between the emitter of the transistor and the first resistor to supply a constant current, and a constant current to a common emitter of the seventh and eighth transistors. Supply And a power supply terminal for receiving a power supply from the outside. A collector of the third transistor is connected to a power supply terminal via a second resistor and a fourth resistor. The collector of the fifth transistor is connected to a connection point between the second resistor and the fourth resistor, and the collector of the sixth transistor is connected to the second resistor and the fourth resistor via a third resistor. A collector of the seventh transistor is connected to the power supply terminal; a collector of the eighth transistor is connected to a connection point of the second resistor and the fourth resistor; The bases of the third, sixth, and seventh transistors are commonly connected, the bases of the fourth, fifth, and eighth transistors are commonly connected, and the common base of the third, sixth, and seventh transistors. And the fourth, fifth and eighth A control voltage is applied between a common base of the transistors, and control is performed from one or both of a connection point between the collector of the third transistor and the second resistor or a connection point between the collector of the sixth transistor and the third resistor. A gain control circuit that outputs an output signal controlled by a voltage,
This has the effect that the DC potential level of the output terminal can be kept constant at the time of gain control with low power.

[0010] According to a third aspect of the present invention, a product of the resistance value of the second resistor and the current value of the first current source, the resistance value of the third resistor and the current value of the second current source are provided. 3. The gain control circuit according to claim 2, wherein the product of the values is equal to the product of the resistance value of the fourth resistor and the current value of the third current source. This has the effect that the DC potential level of the terminal can be kept constant.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a gain control circuit according to the present invention. In FIG. 1, a first differential amplifier circuit A1 is formed by connecting a resistor R1 between the emitters of transistors Q1 and Q2.
2 are input terminals 4 and 5 for input signals,
The connection point between the transistor Q1 and the resistor R1 and the transistor Q
The constant current sources 8 and 9 are connected to the connection point of the resistor 2 and the resistor R1, respectively.

The second differential amplifier circuit A2 is formed by connecting the emitters of the transistors Q3 and Q4 in common, and the collector of the transistor Q1 is connected to the common emitter of the transistors Q3 and Q4. Similarly, the emitters of the transistor Q5 and the transistor Q6 are commonly connected to form a third differential amplifier circuit A3, and the collector of the transistor Q2 is connected to the common emitter of the transistor Q5 and the transistor Q6.

The collector of the transistor Q3 is connected to a resistor R2.
And the resistor R4 to the power supply terminal 1. The collectors of the transistors Q4 and Q5 are connected to a connection point between the resistors R2 and R4, and the collector of the transistor Q6 is connected to a connection point between the resistors R2 and R4 via the resistor R3.

A fourth differential amplifier circuit A4 is formed by connecting the emitters of the transistors Q7 and Q8 in common, and the constant current source 10 is connected to the common emitter of the transistors Q7 and Q8. The collector of the transistor Q7 is connected to the power supply terminal 1, and the collector of the transistor Q8 is connected to a connection point between the resistors R2 and R4.

The bases of the transistors Q3, Q6 and Q7 and the bases of the transistors Q4, Q5 and Q8 are commonly connected to control voltage input terminals 2 and 3, respectively.

A connection point between the transistor Q3 and the resistor R2 and a connection point between the transistor Q6 and the resistor R3 are connected to an output terminal 6 for outputting a signal controlled by a control voltage.
7 is assumed.

In the circuit of FIG. 1, if the value of the change in the minute current due to the input signal flowing through the resistor R2 is ΔI, the output terminal 6
Is given by the following equation (6). vo = A · R2 · ΔI (6) where A is given by the following equation (7). A = EXP (Vd / VT) / (1 + EXP (Vd / VT)) (7) where Vd is the potential difference between the control voltage input terminals 2 and 3, and VT = k · T / q. , K is the Boltzmann constant, T is the absolute temperature, and q is the amount of charge.

According to the above equation (6), the amplitude vo of the output signal
Varies with the potential difference Vd between the control voltage input terminals 2 and 3. A first transistor composed of transistors Q1 and Q2 and a resistor R1
Assuming that the mutual conductance of the differential amplifier circuit A1 is gm, the differential gain Av is given by the following equation (8). Av = A · gm · R2 (8) Accordingly, as shown in the above equation (8), the differential gain can be controlled by the potential difference Vd between the control voltage input terminals 2 and 3.

Assuming that the current flowing through the constant current sources 8 and 9 is I1, the current flowing through the constant current source 10 is I2, and the current flowing through the resistor R4 is I4, I4 is given by the following equation (9). I4 = 2 · I1 + I2 / (1 + EXP (Vd / VT)) (9)

Assuming that the potential of the power supply terminal 1 is VCC and the potential of the connection point between the transistor Q8 and the resistor R4 is V1, V1
Is given by the following equation (10). V1 = VCC-I4.R4 (10)

Assuming that the current flowing through the resistor R3 is I3, I
3 is given by the following equation (11). I3 = I1 / (1 + EXP (−Vd / VT)) (11)

Assuming that the DC potential of the output terminal 6 is VOD,
VOD is given by the following equation (12). VOD = V1-I3 · R2 (12)

From the equations (9), (10) and (11), the equation (12) is given by the following equation (13). VOD = VCC-2 · I1 · R4 + I2 · R4 / (1 + EXP (Vd / VT)) − I1 · R2 / (1 + EXP (−Vd / VT)) (13) The DC potential V2 of the output terminal 6 is controlled. Voltage input terminals 2, 3
In order to make the derivative of the equation (13) equal to zero, the current I1 flowing through the constant current sources 8 and 9 and the current The constant of the current I2 flowing through the source 10, the resistance R2, and the resistance R4 may be determined.

The derivative of the above equation (13) is given by the following equation (14). dVOD / dVd = -I2 * R4 * EXP (Vd / VT) / (VT * (1 + EXP (Vd / VT)) / 2) + I1 * R2 * EXP (Vd / VT) / (VT * (1 + EXP (Vd / VT)) ＾ 2) (14)

A conditional expression for making the above expression (14) equal to zero is given by the following expression (15). I2 · R4 = I1 · R2 (15) Accordingly, the current I1 flowing through the constant current sources 8 and 9 and the current I1 flowing through the current source 10 are satisfied so as to satisfy the condition of the expression (15).
2, the resistance of the resistor R2, and the constant of the resistor R4, the DC potential VOD of the output terminal 6 becomes constant with respect to the potential difference Vd of the control voltage input to the control voltage input terminals 2, 3.

Assuming that the DC potential of the output terminal 7 is VODX, the VODX is also constant with respect to the potential difference Vd between the potentials input to the control voltage input terminals 2 and 3.

[0027]

As described above, according to the present invention, the DC potential level of the output terminal is constant irrespective of the control voltage, and two npn transistors are provided between the power supply terminal and GND.
Even when an npn transistor is used as a stage or a constant current source, it can be realized by cascade connection of three stages of npn transistors, so that there is an effect that a gain control circuit capable of low power operation can be configured, and low power operation of a portable terminal or the like can be achieved. This is suitable for an automatic control circuit of a semiconductor integrated circuit that requires the above.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a gain control circuit for explaining an embodiment of the present invention;

FIG. 2 is a circuit diagram of a conventional gain control circuit.

[Explanation of symbols]

 1, 2 power supply terminals 2, 3, 12, 13 control voltage input terminals 4, 5, 14, 15 input signal input terminals 6, 7, 16, 17 output terminals Q1 to Q15 npn transistors R1 to R8 resistors A1 to A4 differential Amplifier circuit

Claims (3)

(57) [Claims] 1. A first circuit comprising a first and a second transistor for supplying an input signal to a base and a first resistor for connecting the emitters of the transistors to each other.
, And third, fourth, fifth, and sixth transistors, each having a base as a first and second control voltage input terminal, and an output as a load using the second and third resistors as loads. A second and third differential amplifier circuit for controlling a signal level and outputting an output signal to first and second output terminals;
A gain control circuit in which the common emitters of the fourth, fifth, and sixth transistors are connected to the collectors of the first and second transistors, respectively, from the seventh and eighth transistors using the fourth resistor as a load. By adding a fourth differential amplifier circuit to configure, and simultaneously changing the ratio of the DC current flowing through the collector of the fourth resistor and the collector of the seventh transistor at the time of gain control, the first and second differential amplifier circuits are independent of the control voltage. A gain control circuit wherein a DC potential level of a second output terminal is fixed. 2. A first differential amplifier circuit comprising a first resistor connected between emitters of first and second transistors for supplying an input signal to a base, and a third and fourth transistor, respectively. A second differential amplifier circuit configured by connecting the emitter of the first transistor to the collector of the first transistor, and connecting the emitters of the fifth and sixth transistors to the collector of the second transistor. A third differential amplifier circuit configured, a fourth differential amplifier circuit configured to share the emitters of seventh and eighth transistors, an emitter of the first and second transistors, and the first resistor A first and a second constant current source respectively connected to a connection point of the first and second to supply a constant current; a third current source to supply a constant current to a common emitter of the seventh and eighth transistors; External power supply And a power supply terminal for receiving the power supply. The collector of the third transistor is connected to the power supply terminal via a second resistor and a fourth resistor.
The collector of the transistor is connected to the second resistor and the fourth resistor.
The collector of the sixth transistor is connected to the connection point of the second resistor and the fourth resistor via a third resistor, and the collector of the seventh transistor is connected to the collector of the sixth transistor. The collector of the eighth transistor is connected to a connection point between the second resistor and the fourth resistor, and the bases of the third, sixth, and seventh transistors are commonly connected. And the fourth, fifth, eighth
Are connected in common, and the third,
A control voltage is applied between the common base of the sixth and seventh transistors and the common base of the fourth, fifth and eighth transistors, and the connection point between the collector of the third transistor and the second resistor or A gain control circuit for outputting an output signal controlled by a control voltage from one or both of a connection point of a collector of a sixth transistor and the third resistor. 3. The product of the resistance of the second resistor and the current of the first current source, the product of the resistance of the third resistor and the current of the second current source, and the product of the fourth resistor. 3. The gain control circuit according to claim 2, wherein the product of the resistance value and the current value of the third current source is equal.