JPH08315594A - Sample and hold circuit - Google Patents

Abstract

PURPOSE: To reduce the feed through by offsetting the effect of fluctuation of input signal on the holding voltage by the fluctuation of antiphase during the hold period. CONSTITUTION: An input signal VIN is fed to an input amplifying section 2 to produce signals V1 , V2 of antiphase and the signal V1 is applied to an adding section 5 through a switching section 3 during sample period. A leak component of the signal V2 from a switching section 4 of similar circuitry to the switching section 3 is applied to the adding section 5 and the gain thereof can be corrected at the input amplifying section 2. Output from the adding section is fed to a capacitor C1 and a buffer amplifier 6 and outputted therefrom. During the hold period, both switching sections 3, 4 are opened and a voltage, prevailing immediately before transition from sample period to hold period, is held in the capacitor C1. Leak components from the switching sections 3, 4 are offset because they are in antiphase relationship and thereby, the feed through is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, and more particularly to a sample and hold circuit suitable for a monolithic IC.

[0002]

2. Description of the Related Art Conventionally, a sample and hold circuit having a structure as shown in FIG. 3 has been known. This sample and hold circuit is configured as follows. That is, the signal input terminal 20 is the NPN transistor Q.
The transistor Q20 has its collector connected to the power supply V _CC and its emitter connected to the constant current source I20. The constant current source I20 is for determining the bias current of the transistor Q20. Transistor Q
The emitter of 20 is connected to the base of the transistor Q23 via the resistor R20. The collector of the transistor Q23 is connected to the power source V _CC , and the emitter is connected to the capacitor C20 and the input of the buffer amplifier 23. The transistors Q21 and Q22 are emitter-coupled, and the constant current source I21 is connected to the common connection point.
The collector of the transistor Q21 is connected to the base of the transistor Q23, the collector of the transistor Q22 is connected to the emitter of the transistor Q23, and the transistors Q21,
The paths of the currents flowing into the constant current source I21 are switched by the terminals 21 connected to the bases of Q22, and the control signals / φ, φ input to the terminals 22. The emitter of the transistor Q23 is connected to the capacitor C20 and the output terminal 24 via the buffer amplifier 23.

Japanese Patent Publication No. 6-32237 discloses a sample and hold circuit having a structure as shown in FIG. In FIG. 4, members that are the same as or correspond to those of the conventional example shown in FIG. 3 are designated by the same reference numerals, and description thereof will be omitted. 3 is different from the conventional example shown in FIG. 3 in that the collector is connected to the power supply voltage V _CC , the base is connected to the resistor R21 and the Zener diode ZD, and the emitter is connected to the base of the transistor Q23. Is.

Next, the operation of the conventional sample and hold circuit shown in FIG. 3 will be described. The control signals / φ and φ applied to the terminals 21 and 22 are signals whose voltage changes are opposite to each other, and when / φ is at the L level and φ is at the H level, FIG.
The circuit shown in (1) is set to the sample mode, and when / φ is at the H level and φ is at the L level, the circuit is set to the hold mode. First, in the sampling period, when the sampling mode is set, the transistor Q21 is turned off and the transistor Q22 is turned on.
Turns on, the constant current source I21 becomes a bias current of the transistor Q23, and the transistor Q23 also turns on. As a result, the input signal V _IN applied to the signal input terminal 20 is applied to the capacitor C20 via the transistor Q20, the resistor R20 and the transistor Q23. That is, when the voltage between the base and the emitter when the transistor is on is V _BE, and the voltage drop of the resistor R20 due to the base current of the transistor Q23 is ignored, the voltage represented by the following equation (1) is applied to the capacitor C20. To be done. V _IN −V _{BE (Q20)} −V _{BE (Q23)} (1) Therefore, a signal obtained by direct-current level shifting the input signal V _IN is output via the buffer amplifier 23. Output from terminal 24.

Next, in the hold period, when the hold mode is set, the transistor Q21 is turned on, the transistor Q22 is turned off, and the current of the constant current source I21 flows through the path of the transistor Q20-resistor R20-transistor Q21 and the transistor Q21 is turned on. Q23 is off. Therefore, since both the transistor Q22 and the transistor Q23 are off, no current flows in or out of the capacitor C20, and the capacitor C20 holds the potential immediately before the change from the sample period to the hold period.

[0006] Here, when the holding voltage held in the capacitor C20 and the _{V HC, V IN -V BE (} Q20) -I 21 · R 20 <V HC ········ (2) above ( 2) Constant current source I21 and resistor R
If the values I ₂₁ and R ₂₀ of ₂₀ are set, the transistor Q23 is always reverse biased during the hold period, and the holding voltage V _HC becomes a constant voltage regardless of the change of the input signal V _IN , and is output via the buffer amplifier 23. Output from terminal 24.

Next, the difference between the operation of the conventional example shown in FIG. 4 and that shown in FIG. 3 will be described. Transistor Q
The base of 24 is V when the control signal / φ is at H level.
It is set to the sum of _H and the base-emitter voltage V _{BE (Q24)} required to turn on the transistor Q24. With this setting, when the level of the input signal V _IN falls during the hold period and the potential of the connection point N20 becomes V _H , the transistor Q24 turns on and even if the connection point N20 becomes V _H or less, It is kept constant at V _H by Q24. Therefore, the transistor Q21 does not saturate.

Further, in order that the transistor Q23 is not turned on during the hold period, the holding voltage V _HC in the capacitor C20 needs to be V _H or higher. Therefore, the minimum voltage V _INMIN of the input signal V _IN is given by the following equation (3). V _INMIN = V _{BE (Q20)} + V _{BE (Q23)} + V _H (3) Further, the minimum voltage V _INMIN of the input signal V _IN in the conventional example shown in FIG. 3 is expressed by the following equation (4). Become. V _INMIN = V _{BE (Q20)} + I ₂₁ · R ₂₀ + V _{H ···} (4) Here, since I ₂₁ · R ₂₀ is always set to V _{BE (Q23)} or more, (5) is established. V _{BE (Q20)} + I ₂₁ · R ₂₀ + V _H > V _{BE (Q20)} + V _{BE (Q23)} + V _H ··· (5) Therefore, the conventional example shown in FIG. 4 is more input than the conventional example shown in FIG. The minimum voltage can be lowered, and as a result, the dynamic range can be expanded.

[0009]

By the way, in the sample-hold circuit shown in FIG. 3, the holding voltage V _HC in the capacitor C20 is changed to the input signal V by turning off the transistor Q23 and setting the reverse bias in the hold period. It tries to keep it constant regardless of _IN . But,
Due to the influence of the junction capacitance existing between the base and emitter of the transistor, the change of the voltage at the connection point N20 which actually changes according to the input signal V _IN is slightly caused via the junction capacitance between the base and emitter of the transistor Q23. Since it is applied to the capacitor C20 and is output via the buffer amplifier 23, the feedthrough removal ratio, which is one of the important characteristics in the hold period, is deteriorated. The sample-and-hold circuit shown in FIG. 4 has also improved the expansion of the dynamic range, but has not similarly improved the feedthrough reduction.

The present invention has been made to solve the above problems of the conventional sample and hold circuit. The invention of claim 1 provides a sample and hold circuit capable of reducing feedthrough. The purpose is to The invention according to claim 2 is a monolithic IC in which the feedthrough is reduced and the characteristics of the transistors are easily aligned.
It is an object of the present invention to provide a sample and hold circuit suitable for conversion into a digital signal.

[0011]

In order to solve the above problems, the invention according to claim 1 provides an input signal, a first output signal having the same phase as the input signal, and the first output signal. And an input amplifying means for obtaining a second output signal having a voltage change of opposite phase, and a first output signal of the input amplifying means are input to one end, and the sample period is closed and the hold period is opened. The first switching means and the second output signal of the input amplifying means are input to one end, and the second switching means which is always in the open state and the other end of the first switching means are connected to one input terminal. Also, a sample is formed by adding means in which the other end of the second switching means is connected to the other input terminal, and a capacitor connected between the output terminal of the adding means and the first reference voltage source and holding a sample voltage.・ Hold circuit And it constitutes.

In the sample-and-hold circuit configured as described above, the first switching means is turned on during the sampling period, and the first output signal output from the input amplifying means is one input terminal of the adding means. Entered in. Since the second switching means is in the off state, the first output signal is output via the adding means and held in the capacitor. Further, during the hold period, the first switching means is turned off, and the sample voltage is held in the capacitor. At this time, the leakage component when the first switching means is open in the first output signal is also transmitted to the capacitor. , The effect of changes in the input signal will appear. However, the second switching means is the sampling period,
It is always off regardless of the hold period, and only the leakage component of the second output signal when the second switching means is off is transmitted to the capacitor. Therefore, by making the first switching means and the second switching means have the same configuration, the first output signal and the second output signal have a voltage relationship in which the changes are opposite to each other, so that the hold period In addition, the leakage components from the switching means cancel each other out, the influence of the change of the input signal does not appear in the capacitor, and the feedthrough removal ratio can be improved.

According to a second aspect of the present invention, in the sample-and-hold circuit according to the first aspect, the first switching means receives the first output signal as a base, and the collector has a second reference voltage source. A first resistor having one end and the other end connected to a third reference voltage source.
A first transistor connected to one end of the constant current source, a base connected to the other end of the first resistor, and a collector connected to the second
A second transistor connected to the reference voltage source, a base connected to the input terminal of the first control signal, a collector connected to the base of the second transistor, and an emitter connected to the third terminal at the other end.
A third transistor connected to one end of a second constant current source connected to the reference voltage source, and a base to an input terminal of a second control signal whose voltage change is opposite in phase to the first control signal, The collector is composed of the emitter of the second transistor and the fourth transistor having the emitter connected to one end of the second constant current source, and the second switching means is the base of the second output signal. Is input and the collector is set to the second
A fifth transistor connected to the reference voltage source, the emitter connected to one end of a second resistor, and the other end connected to one end of a third constant current source connected to the third reference voltage source, and the base connected to the fifth transistor. A sixth transistor connected to the other end of the second resistor and having a collector connected to the second reference voltage source, a base connected to the fourth reference voltage source, and a collector connected to the base of the sixth transistor. A seventh transistor having an emitter connected to one end of a fourth constant current source whose other end is connected to a third reference voltage source; a base connected to a fifth reference voltage source; and a collector connected to the fifth reference voltage source. And an eighth transistor connected to the emitter of the sixth constant current source, the emitter connected to one end of the fourth constant current source, and the addition means has one end connected to the emitter of the second transistor. 3rd with the end connected to the capacitor A resistor, is the sixth emitter connected to one end and the other end of the transistor of what constitutes and a fourth resistor connected to said capacitor.

In the sample and hold circuit configured as described above, the first switching means and the second switching means have the same circuit configuration and it is desirable that the characteristics be uniform, so that the sample suitable for a monolithic IC is formed.・ A hold circuit can be realized.

[0015]

EXAMPLES Next, examples will be described. FIG. 1 shows the present invention
A block diagram showing a basic embodiment of such a sample and hold circuit.
It is a block diagram corresponding to the invention of claim 1.
is there. In FIG. 1, 1 is a signal input terminal and 2 is an input increase.
Input signal V input from the signal input terminal 1
_INReceiving the input signal V_INFirst output signal V in phase with
₁And the first output signal V₁And the change have a negative phase voltage relationship.
Second output signal V₂And output. 3 is the input amplifier 2
First output signal V₁The first switch connected to the output terminal of
Itching part is closed during sample period, hold period
It operates so as to be in the open state during the period, 4 is the same.
Second output signal V of input amplifier 2 ₂Connected to the output terminal of
The second switching section is connected to the sampling period and
It is open regardless of the period
It 5 is an output terminal of the first and second switching units 3 and 4
In the addition unit connected to the child, the output terminal of the addition unit 5,
Condenser with one end connected to the first reference voltage source (GND)
The buffer amplifier 6 is connected to the buffer C1
The output side of 6 is connected to the signal output terminal 7.

Next, the operation of the sample and hold circuit thus constructed will be described. First, the input signal V _IN is input to the signal input terminal 1. The input signal V _IN input to the signal input terminal 1 is input to the input amplifying unit 2, and the input amplifying unit 2 has a first output signal V ₁ and a second output signal that have mutually opposite voltage relationships. V ₂ and are output. The first output signal V ₁ is input to the first switching unit 3, and the first switching unit 3 operates so as to be closed during the sample period and open during the hold period. On the other hand, the second output signal V ₂ is input to the second switching unit 4.
The second switching unit 4 is always open regardless of the sampling period and the holding period. Therefore, in the sampling period, the first output signal V ₁ is applied to the addition unit 5 via the first switching unit 3, and the leakage component of the second switching unit 4 in the second output signal V ₂ is applied. Is applied to the adder 5. The output of the adder 5 is connected to the capacitor C1 and the buffer amplifier 6. First
Of the output signal V ₁ and the second output signal V ₂ of the output signal V ₁ and the second output signal V ₂ have opposite phases to each other. Therefore, the leakage component from the second switching unit 4 has a gain with respect to the input signal V _IN. Although it has a lowering effect, this can be corrected by adjusting the gain in the input amplifier 2 or the buffer amplifier 6. Therefore, the input signal V _IN is output from the buffer amplifier 6 in the sampling period.

On the other hand, during the hold period, both the first switching unit 3 and the second switching unit 4 are in the open state, so that the capacitor C1 holds the voltage V _HC immediately before the change from the sample period to the hold period. . However, the leak component from the first switching unit 3 of the first output signal V ₁ is applied to the adding unit 5, and the capacitor C
The voltage V _HC held at 1 is affected by changes in the input signal V _IN , resulting in increased feedthrough during the hold period. However, in this embodiment, the leakage component from the second switching section 4 of the second output signal V ₂ is also applied to the capacitor C1 via the adding section 5. And
Since the first output signal V ₁ and the second output signal V ₂ have a voltage relationship in which their changes are opposite to each other, the leakage component from the second switching unit 4 is a leakage component from the first switching unit 3. Will be offset by each other. After all, the voltage V _HC held in the capacitor C1 is output via the buffer amplifier 6 without changing due to the influence of the input signal V _IN , and it becomes possible to reduce the feedthrough during the hold period.

As described above, in this embodiment, the feedthrough can be reduced by canceling the influence of the change of the input signal on the holding voltage by the change of the opposite phase during the hold period.

Next, a concrete embodiment of the present invention will be described with reference to FIG. This embodiment corresponds to the invention described in claim 2, and the same or corresponding members as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals. The sample-and-hold circuit of this embodiment is the first amplifier from the input amplifier 2.
Output signal V ₁ of the first transistor Q1 is input to the base of the first transistor Q1, and the collector of the first transistor Q1 is connected to the second transistor Q1.
It is connected to the reference voltage source V _CC, an emitter first resistor R
1 and one end of the first constant current source I1 and the other end of the first constant current source I1 is connected to the third reference voltage source V _EE . The other end of the first resistor R1 is connected to the base of the second transistor Q2 and the collector of the third transistor Q3, the emitter of the second transistor Q2 is connected to the collector of the fourth transistor Q4, and The emitter of the third transistor Q3 and the emitter of the fourth transistor Q4 are commonly connected to one end of the second constant current source I2, and the other end of the second constant current source I2 is connected to the third constant current source I2.
Connected to the reference voltage source V _EE of. The first control signal / φ from the terminal 8 is input to the base of the third transistor Q3, and the first control signal / φ from the terminal 9 is input to the base of the fourth transistor Q4. And the second control signal φ having a voltage change of opposite phase is input, and the above configuration constitutes the first switching unit.

Next, the second output signal V 2 from the input amplifier ₂ is input to the base of the fifth transistor Q5, and the collector of the fifth transistor Q5 is supplied to the second reference voltage source V _CC . Connected to the fifth transistor Q5
The emitter of is connected to one end of the second resistor R2 and the third constant current source I
3 and one end of the third constant current source I3 is connected to a third reference voltage source V _EE . The other end of the second resistor R2 is connected to the base of the sixth transistor Q6 and the seventh
Is connected to the collector of the transistor Q7, and the collector of the sixth transistor Q6 is connected to the second reference voltage source V _CC.
The emitter of the sixth transistor Q6 is connected to the collector of the eighth transistor Q8, and the emitters of the seventh transistor Q7 and the eighth transistor Q8 are connected to one end of the fourth constant current source I4. And the other end of the fourth constant current source I4 is connected to the third reference voltage source V _EE . A fourth reference voltage source V ₃ for constantly turning on the transistor Q7 is connected to the base of the seventh transistor Q7, and a base for turning on the transistor Q8 is always connected to the base of the eighth transistor Q8. The reference voltage source V _{4 of} 5 is connected,
The above configuration constitutes the second switching unit.

Further, one end of a third resistor R3 is connected to the emitter of the second transistor Q2, one end of a fourth resistor R4 is connected to the emitter of the sixth transistor Q6, and the third resistor R4 is connected to the third resistor R4. A capacitor C having the other end of the resistor R3 and the other end of the fourth resistor R4, one end of which is connected to GND.
It is connected to the other end of 1 to form an adder.

Next, a concrete second embodiment constructed as described above.
The operation of the embodiment will be described. The control signals / φ and φ respectively applied to the terminals 8 and 9 have opposite voltage changes in voltage. When / φ is at L level and φ is at H level, it operates in the sample mode, and / φ is at H level and φ is at L level.
In the case of level, it operates in hold mode. First,
In the sampling period, the transistor Q3 is off and the transistor Q4 is on. Therefore, the constant current source I2
Current flows through the transistor Q2, and the transistor Q2 is turned on to operate as an emitter follower. The input signal V _IN is input to the input amplification unit 2 from the signal input terminal 1.
The input amplification unit 2 outputs a first output signal V ₁ that changes according to the input signal V _IN and a second output signal V ₂ that changes in a voltage relationship with the first output signal V _{1 in an} opposite phase. The first output signal V ₁ is input to the base of the transistor Q2 through the transistor Q1 and the resistor R1 which operate as an emitter follower by the constant current source I1. Here transistor Q2
Since the emitter-follower operation is performed, at the connection point N2 (emitter of the transistor Q2), the voltage obtained by subtracting the base-emitter voltage during the ON operation of the transistors Q1 and Q2 from the first output signal V ₁ , that is, A voltage represented by (6) is generated. V ₁ −V _{BE (Q1)} −V _{BE (Q2)} (6) However, the voltage drop of the resistor R1 due to the base current of the transistor Q2 is ignored here. .

On the other hand, the second output signal V ₂ is the constant current source I3.
Is input to the base of the transistor Q6 via the transistor Q5 which operates as an emitter follower and the resistor R2. However, in the pair of emitter-coupled transistors Q7 and Q8, the transistor Q7 is always on regardless of the sample period and the hold period, and the transistor Q7 is always on.
8 so that the reference voltage source V ₃ and the reference voltage source V are turned off.
₄ is set. Therefore, the current of the constant current source I4 is
The current flows through the path of the transistor Q5-resistor R2-transistor Q7, and the transistor Q6 is turned off. V ₂ −V _{BE (Q5)} −I ₄ · R ₂ <V ₁ −V _{BE (Q1)} −V _{BE (Q2)} (7) Further, the constant current source I 4 may satisfy the above formula (7). And by setting the values I ₄ and R ₂ of the resistor R2, the transistor Q6
Is always reverse biased. Therefore, a change in the second output signal V ₂ appears at the connection point N4 (emitter of the transistor Q6) via the junction capacitance between the base and emitter of the transistor Q6.

Therefore, at the connection point N5 (common connection point of the resistors R3 and R4), the signals generated at the connection points N2 and N4 appear via the resistors R3 and R4, respectively. Here, in the second output signal V ₂ appearing at the connection point N 4, the component leaking from the junction capacitance of the cut-off transistor Q 6 is changed from that of the first output signal V ₁ and that of the second output signal V _{2 in} reverse. Since there is a phase voltage relationship, the connection point N
A value of 5 lowers the gain. However, this can be corrected by adjusting the gain in the input amplifier 2 or the buffer amplifier 6.

Next, in the hold period, the transistor Q3 is turned on and the transistor Q4 is turned off. Therefore, the current of the constant current source I2 is the transistor Q1-resistor R1.
Flowing through the path of transistor Q3, turning off transistor Q2. Here, the transistors Q2 and Q4 and the transistors Q6 and Q8 are all off, and if the input bias current of the buffer amplifier 6 is ignored, the capacitor C1
There is no inflow or outflow of electric current. Therefore, the capacitor C1
Holds the voltage immediately before switching from the sample period to the hold period. When this held voltage is V _HC , V ₁ −V _{BE (Q1)} −I ₂ · R ₁ <V _HC・ ・ ・ ・ ・ ・ ・ ・ (8) It is determined that the above equation (8) is satisfied. Current source I2 and resistor R1
If the values I ₂ and R _{1 of the above} are set, the transistor Q2 becomes reverse biased, and the first output signal V ₁ does not appear at the connection point N2. However, in reality, due to the influence of the junction capacitance between the base and emitter of the transistor Q2, a slight change in the first output signal V ₁ leaks and appears at the connection point N2. As a result, the change in the first output signal V ₁ that changes according to the change in the input signal V _IN during the hold period changes the holding voltage V _HC , which is output via the buffer amplifier 6, so that the input signal There is a feedthrough issue where changes affect the output.

However, in the present embodiment, the second switching section which is always in the cut-off state and which is constituted by the transistors Q6, Q7, Q8 and the resistor R2 is provided, and in this second switching section, the sampling period is changed. As described in the description, the influence of the change in the _second output signal V ₂ appears at the connection point N4 due to the influence of the base-emitter capacitance of the transistor Q6. Here, the first output signal V ₁ and the second output signal V ₂ have a voltage relationship in which changes are in opposite phases.
Therefore, the change in the first output signal V ₁ leaking from the cut off transistor Q2 to the connection point N2 and the change in the second output signal V ₂ leaking from the cut off transistor Q6 to the connection point N4 are in opposite phases to each other. It becomes a relationship, and these work so as to offset each other. Further, the first switching unit and the second switching unit have the same circuit configuration, and (7),
The constant current source I2 and the constant current source I4 within a range satisfying the expression (8).
And the resistance R1 and the resistance R2 are set to the same value, the input signal V appearing at the connection point N2 and the connection point N4
The changes in _IN have the same amplitude, and the input signal V _IN
Does not appear and the holding voltage V _HC is held during the hold period and is output to the output terminal 7 via the buffer amplifier 6, so that feedthrough can be reduced. Further, if a monolithic IC is used, it is easy to make the characteristics of each transistor uniform, and it is possible to further reduce the feedthrough.

[0027]

As described above on the basis of the embodiments,
According to the first aspect of the invention, in the sample hold circuit, the effect of the change of the input signal on the holding voltage during the hold period is canceled by the change of the opposite phase, so that the feedthrough can be reduced. According to the second aspect of the present invention, it is desirable that the first and second switching sections have the same circuit configuration and have the same characteristics. Therefore, it is possible to realize a sample hold circuit suitable for a monolithic IC. You can

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic embodiment of a sample and hold circuit according to the present invention.

FIG. 2 is a circuit configuration diagram showing a specific embodiment of the present invention.

FIG. 3 is a circuit configuration diagram showing a configuration example of a conventional sample and hold circuit.

FIG. 4 is a circuit configuration diagram showing another configuration example of a conventional sample and hold circuit.

[Explanation of symbols]

 1 Signal Input Terminal 2 Input Amplifier Section 3 First Switching Section 4 Second Switching Section 5 Addition Section 6 Buffer Amplifier 7 Output Terminal

Claims (2)

[Claims] 1. An input amplifying means for obtaining, from an input signal, a first output signal having the same phase as that of the input signal, and a second output signal having a voltage relationship different from that of the first output signal in opposite phase. , A first output signal of the input amplifying means is input to one end, a first switching means which is closed during a sampling period and opened during a hold period, and a second output signal of the input amplifying means is input at one end A second switching means which is always open, and an adding means which connects the other end of the first switching means to one input terminal and the other end of the second switching means to the other input terminal. A sample and hold circuit comprising: a capacitor connected between an output terminal of the adding means and a first reference voltage source for holding a sample voltage. 2. The first switching means has the base to which the first output signal is input, the collector connected to a second reference voltage source, and the emitter connected to one end and the other end of the first resistor. A first transistor connected to one end of a first constant current source connected to the third reference voltage source, a base connected to the other end of the first resistor, and a collector connected to the second reference voltage source. And a second transistor having a base connected to the input terminal of the first control signal, a collector connected to the base of the second transistor, and an emitter connected to the third reference voltage source at the other end. A third transistor connected to one end of a constant current source, a base as an input terminal for a second control signal having a voltage change opposite to that of the first control signal, and a collector as the second control signal.
And a fourth transistor having an emitter connected to one end of the second constant current source, the second switching means having a base connected to the second transistor.
Output signal is input, the collector is connected to the second reference voltage source, the emitter is connected to one end of the second resistor and one end of the third constant current source whose other end is connected to the third reference voltage source. A fifth transistor connected to the sixth resistor, a base connected to the other end of the second resistor, and a collector connected to a second reference voltage source.
And a base connected to a fourth reference voltage source, a collector connected to the base of the sixth transistor, and an emitter connected at its other end to a third reference voltage source A seventh transistor connected to one end of
The base is connected to the fifth reference voltage source, and the collector is connected to the sixth reference voltage source.
And an eighth transistor having an emitter connected to one end of the fourth constant current source, the adding means connecting one end to the emitter of the second transistor and the other end. And a third resistor connected to the capacitor, and a fourth resistor having one end connected to the emitter of the sixth transistor and the other end connected to the capacitor. Sample hold circuit described.