KR0132984B1 - High-speed mode switching apparatus for cdg player system - Google Patents

Abstract

The internal synchronous signal is inverted by the inverter(71), and delivered to the data input terminal(D) of D flip-flop(73). After converted into the reversed wave by the wave form generator(72), the external synchronous signal is delivered as the clock signal of D flip-flop(73). As a result, when the transistor(61) of the oscillator(60) is turned off, the oscillating element(64) oscillates by the capacity determined by the 2nd capacitor(62). Subsequently the phase comparer(40) after comparing the internal horizontal synchronous signal with the external horizontal synchronous signal, delivers the comparison result signal to phase compensator(50). Therefore when the phase compensator(50) outputs a control signal to compensate the phase difference, the potential increases.

Description

High Speed Mode Switching Device of CDG Playback System

1 is a block diagram of a CDG playback system having a superimpose function to which the present invention is applied.

2 is a view for explaining an example of the configuration of a phase synchronization detector, an oscillator, a phase comparator, and a phase compensator in a CDG reproducing system having a superimpose function according to an embodiment of the present invention shown in FIG.

3 is a waveform diagram illustrating the operation of the fast mode switching device of the CDG playback system according to the present invention.

* Explanation of symbols for main parts of the drawings

10: synchronous detector 20: synchronous separator

30: CDG decoder 40: phase comparator

50: phase compensator 60: oscillator

61 transistor 62, 63 capacitor

67 varactor diode 70 phase synchronization detector

71: inverter 72: pulse generator

73: D flip-flop 80: RGB encoder

90: switching unit 100: reset controller

110: oscillator

The present invention relates to a high speed mode switching device of a CDG playback system, and more particularly, to a mode for signal processing graphic information in a sub code recorded on a CDG disc, and to superimpose the video signal from the external video source with the graphic information of the CDG disc. A high speed mode switching device of a CDG reproducing system in which switching between different modes is made stable and at high speed.

Now, with the development of the disk-shaped information recording medium, which is a composite medium of video and audio, we have created a new type of software such as visual music or graphic education program. With the creation of a complete A / V device that operates as a single system, the atmosphere of video and audio coexists.

As the A / V era begins in earnest, interest in pure audio culture that presupposes only auditory appreciation has been focused on the development of media where audiovisual coexists. In particular, by reading information from disc-shaped information storage media, Attention has been paid to a multi-disc player (MDP) for reproducing video signals and audio signals.

The multi-disc player reads out image information and / or audio information recorded on a disc-shaped information storage medium such as a compact disc graphic (CDG) or a laser disc (LD) and performs image signal processing and / or audio signal processing, respectively. The audio signal is output through the speaker and the video signal is displayed on the monitor.

Compact Disc Graphics (CDG), which is a kind of information recording medium employed in a multi-disc player as described above, has not only good sound quality but also high-quality randomness based on an audio code and an 8-bit sub code signal recorded on the disc. Random access and graphics disc play are possible.

Here, the 8-bit subcode signal recorded on the compact disc graphic is recorded in the channels P, Q, R, S, T, U, V, and W. Among them, the P and Q channels have already been randomly accessed by the CDG disc player, It is used for display of playback time and track number display, while the remaining R to W channels are used for graphic data transmission.

As such, in general, a superimpose function is widely employed to display graphic data on a compact disc, such as lyrics data or subtitle data, on a monitor together with a video signal provided from an external source such as a television.

According to the configuration of the CDG playback system having the superimpose function, as shown in FIG. 1, a synchronization detector 12 for detecting a synchronization signal from an external video signal provided by an external video source such as a television, and the external A sync separator 20 for extracting and separating the horizontal sync signal and the vertical sync signal from the video signal, a CDG decoder 30 for decoding the graphic information recorded in the subcode on the CDG disc, and an external horizontal from the sync separator 20 A phase comparator 40 for comparing the phase of the synchronization signal with the internal horizontal sync signal from the CDG decoder 20, and an internal horizontal sync signal to compensate for the phase difference detected as a result of the comparison in the phase comparator 40 A phase compensator 50 for controlling the oscillator 60 for oscillating a source clock of the source, and a graph applied from the CDG decoder 30 based on a composite synchronization signal from the CDG decoder 30. An external spiritual signal and a graphic signal from the RGB encoder 80 in accordance with an RGB encoder 80 for encoding R, G, and B color signals for pick information, and a superimposed timing signal from the CDG decoder 30. And a switching unit 90 for superimposing and switching at high speed, and the synchronization signal of the external video signal is separated from the synchronization separator 20 and reset for resetting the CDG decoder 30. The controller 100 and 110 adjust the color subcarrier frequency (3,5705MHz) by synchronizing the color subcarrier of the external video signal with the internal color subcarrier signal from the CDG decoder 30 applied through the switching element 20. Denotes an oscillator generating 130, and denotes a color burst gate pulse generator that takes a color subcarrier frequency (3,5795 MHz) output from the CDG decoder 30 and provides a color subcarrier pulse to the RGB encoder 80. The.

According to the CDG playback system having the superimposed function configured as described above, first, the synchronous detector 10 detects a synchronous signal from an external video signal to detect the phase compensator 50, the reset controller 150, and the switching device 120. Is applied to, for example, an external video signal processing (i.e., superimpose mode).

In addition, the synchronous separator 20 extracts and separates an external horizontal synchronous signal and an external vertical synchronous signal from an external video signal provided from an external video source such as a television, and then uses the CDG decoder 30 by the external vertical synchronous signal. The CRT controller (not shown) installed in the < RTI ID = 0.0 > 1 < / RTI > is reset by the reset controller 100, and generated by dividing 910 the preceding clock signal from the oscillator 60 input to the CDG decoder 30. An internal horizontal synchronizing signal and the separated external horizontal synchronizing signal are applied to the phase comparator 40. Accordingly, the phase comparator 40 compares the phases of the external horizontal synchronization signal and the internal horizontal synchronization signal, and the phase compensator 50 compensates for the phase difference when the phase difference is detected as a result of the comparison. A phase compensation value control signal for controlling the time of the clock signal oscillated at 60) is output, and the oscillator 60 outputs a source clock of the internal horizontal synchronization signal whose phase error is accurately compensated according to the phase compensation value control signal. It will oscillate at 14.31818MHz. The CDG decoder 30 generates a complex synchronous signal (C-sync) using the oscillation frequency and applies it to the RGB encoder 80, while the RGB encoder 80 decodes the CDG decoder 30. According to the result, the R, G, and B color signals of the output graphic information are encoded based on the complex synchronous signal (C-sync) to generate an internal image signal.

Subsequently, the switching unit 90 superimposes the external video signal from the external video source and the graphic signal (internal video signal) output from the RGB encoder 80 from the output terminal A of the CDG decoder 30. By switching based on the superimposing timing signal, it is output as a single screen (video).

However, in the case where only lyrics data for video flexible training is included on a CDG disc as an information recording medium, for example, lyrics data and a background image are displayed by superimposing a video signal reproduced on a laser disc or an external video playback medium. . In this case, for example, in a CDG disc in which an educational program is recorded, an internal mode for displaying image data based on the internal synchronization signal oscillated in FIG. 1 is required, whereas in the case of a CDG disc in which image flexible data (lyrics) is recorded. Superimpose mode for superimpose function with an external video signal is required. Therefore, in the CDG playback system, frequent mode switching between the internal mode and the superimpose mode is required. Here, switching from the superimpose mode to the CDG internal mode is achieved only by the instantaneous ON operation when the device constituting the synchronous detector 10, for example, a transistor, is switched from the CDG internal mode to the superimpose mode. PULL-IN TIME of the phase comparator 40 constituting the PLL circuit, the phase compensator 50, the oscillator 60, and the phase synchronous detector 70 until the PLL circuit is locked. Time) becomes a problem. That is, the full-in time depends on the initial frequency and phase difference of the external horizontal synchronizer signal and the internal horizontal synchronizer signal applied to the phase comparator 40, the gain of the PLL circuit, and the filter band of the phase compensator 50. Therefore, in order to minimize the full-time, the gain of the PLL circuit and the filter band of the phase compensator 50 should be set to be large, but in this case, the stability of the PLL circuit is deteriorated, resulting in accurate locking between the CDG image and the external video signal. In other words, stable superimposition is impossible.

On the other hand, taking the method of narrowing the bandwidth of the phase compensator 50, there is a disadvantage that the error in the steady state is reduced but the pull-in time is increased.

Accordingly, the present invention has been made in view of the above-described prior art, and its object is to increase the full-in time when switching from the CDG internal mode to the superimpose mode to superimpose the CDG data and the external video signal. It is to provide a high speed mode switching device of a CDG reproducing system that allows accurate mode switching at a high speed without a problem.

According to an embodiment of the present invention for achieving the above object, a synchronization detection / separation means for detecting and synchronously separating an external horizontal synchronization signal and an external vertical synchronization signal from an external video signal, and recorded in a western code on a CDG disc. A CDG decoder for decoding graphic information, a PLL circuit means for phase-synchronizing the phase difference by compensating the phase difference by comparing the phase of the external horizontal synchronization signal from the synchronization separator with the internal horizontal synchronization signal from the CDG decoder, and from the CDG decoder. An external video signal and graphics from the RGB encoder according to an RGB encoder encoding R, G, and B color signals for graphic information applied from the CDG decoder based on a composite synchronous signal, and a superimposed timing signal from the CDG decoder. A CDG reproducing system having a switching section for superimposing a signal at high speed in mode switching, wherein the PLL circuit is used. The means comprises: a phase synchronous detector for detecting a phase synchronous state of an internal synchronous signal and an external synchronous signal in a CDG inner mode and generating a signal for varying the frequency of generation; and a oscillation frequency variable signal by the phase synchronous detector. A high speed mode switching device of a CDG reproducing system, comprising an oscillator for oscillating a high speed synchronous signal when switching a mode between a CDG internal mode and a superimpose mode, is provided.

According to the present invention, a phase synchronous detector constituting the PLL circuit means includes an inverter for inverting an internal horizontal synchronous signal, a pulse generator for generating an inverted pulse of an external horizontal synchronous signal, and an internal horizontal synchronous signal inverted by the inverter. And a D flip-flop which receives the data input and outputs the phase synchronization detection result at the inverting output stage using the external dynamic base pulse of the pulse generator as the clock signal.

The oscillator of the PLL circuit means has a transistor which is switched and controlled by a phase synchronous detection result of the phase synchronous detector, a first capacitor connected to the transistor emitter side to determine the capacitance of the oscillation element when switching ON, and a collector side of the transistor. A second capacitor coupled to a second capacitor for setting a variable capacitance of the oscillation element, an inverter for stabilizing an oscillation signal of the oscillation element by the first and / or second capacitors, and a phase difference between the external horizontal synchronization signal and the internal horizontal synchronization signal. It is configured to include a varactor diode for changing the capacitance by adjusting the oscillation potential of the oscillation element.

According to the high speed mode switching device of the CDG reproducing system according to the present invention configured as described above, the phase synchronization detection result with the internal horizontal synchronization signal is obtained based on the external synchronization signal, and the oscillation capacity of the oscillator is varied according to the phase synchronization detection result. By minimizing the full-intime when switching from the CDG internal mode to the superimpose mode, stable and accurate high speed mode switching is possible even during frequent mode switching.

Hereinafter, with reference to the accompanying drawings, the present invention will be described in detail.

2 shows an internal horizontal synchronization signal for the phase synchronization detector 70 constituting the PLL circuit means in the CDG reproducing system described above with reference to FIG. 1, and an external synchronization signal detected by the phase synchronization detector 70 thereof. An oscillator 60 and an external horizontal synchronizer for capacitively oscillating a 14.31818 MHz signal, which is a source clock of the internal horizontal synchronizing signal, so that the external synchronizing signal and the internal synchronizing signal coincide at high speed during the mode switching based on the phase synchronizing detection signal A diagram showing in detail the configuration of a phase comparator 40 for comparing the phases of the internal synchronization signal and a phase compensator 50 for compensating the phase difference according to the phase comparison result of the phase comparator 40. Since the remaining components are configured the same as or similar to those shown in FIG. 1, detailed descriptions thereof will be omitted to avoid duplication.

First, the phase synchronous detector 70 shown in FIG. 2 includes an inverter 71 for inverting an internal horizontal synchronous signal, a pulse generator 72 for receiving an external horizontal synchronous signal to generate an inverted pulse, and the inverter ( 71 is configured as a data input, and an inverted pulse of the pulse generator 72 is used as a clock signal, and a D flip-flop 73 for outputting a phase synchronous detection signal from the inversion output terminal Q thereof.

The oscillator 60 is connected to a transistor 61 which is switched ON when the inverted output of the D flip-flop 73 of the phase synchronization detector 70 is at a high level, and is connected to the emitter side of the transistor 61. And a first capacitor 62 for providing a high speed oscillation capacity for a source clock of an internal horizontal synchronization signal, a second capacitor 63 connected to a collector side of the transistor 61 to vary an oscillation capacity, and the first capacitor. And / or reversely connected to the oscillation element 64 oscillating the source clock at the capacitance value determined by the second capacitors 62 and 63, both ends of the oscillation element 64 and the collector side path of the transistor 61. Inverter 65 for stabilizing the oscillation element, varactor diode 67 disposed at one end of the inverter 65, capacitor C and resistor R for setting the operating potential of the varactor diode 67. ), And one end of the capacitor (C) to the ground potential While the information, one end of the resistor (R) is set to the potential of the negative voltage (V _E).

In addition, the phase compensator 50 is connected to a phase comparator 40 for comparing the phase of the internal horizontal synchronization signal and the external synchronization signal, so that the inverting input terminal (+) is set to the ground potential, while the inverting input terminal (-). Amplifies the phase difference signal of the phase comparator 40 by the resistor 51, the capacitor 52, and the resistors 53 and 54, for example, between the synchronous detector 20 and the oscillator 60 composed of transistors. The OP amplifier 55 which applies a phase compensation difference is comprised.

The high speed mode switching device of the CDG reproducing system according to the present invention having the PLL circuit means configured as described above will be described with reference to the waveform diagram shown in FIG.

The phase synchronous detector 70 is inverted (see FIG. 3 (a)) in the inverter 71 when there is an internal horizontal synchronous signal, and then applied to the data input terminal D of the D flip-flop 73. The external synchronous signal becomes a waveform inverted by the waveform generator 72 (see FIG. 3 (b)) and is applied as a clock signal of the D flip-flop 73.

Here, in the D flip-flop 73, if both horizontal synchronization signals are not synchronized, a low level is output, and accordingly, the transistor 62 of the oscillator 60 is turned off, so that the capacitor 62 is in a circuit non-circuit. The connection state is established. Therefore, the internal horizontal synchronizing signal and the external horizontal synchronizing signal are outside the range of the capture range, so that they quickly cross each other, and the oscillation element 64 is formed by the second capacitor 62 and the varactor diode 67. Oscillation is performed at a predetermined capacitance value. At this time, the phase comparator 40 compares the internal horizontal synchronizing signal with the external horizontal synchronizing signal, and applies the comparison result value (ie, phase difference) signal to the ideal compensator 50, and accordingly, the phase compensator 50 provides a phase difference. By outputting a control signal for the compensation of the oscillator 60, the potential applied to the varactor diode 67 side is increased so that the oscillation capacity of the oscillation element 64 is maintained in a large state.

Subsequently, when the internal horizontal synchronization signal and the external synchronization signal coincide with each other (ie, phase synchronization) as shown in FIGS. 3A and 3B, the inverted output terminal Q of the D flip-flop 73 is used. ), The output level of C1 becomes high as shown in FIG. 3C, and the transistor 61 of the oscillator 60 is turned ON, so that the capacitor 62 is connected in a circuit and the oscillation element The oscillation capacity of 64 is varied. Therefore, the phase of the PLL circuit means is momentarily locked, and the influence of the full-in time can be minimized especially when switching from the CDG internal mode to the superimpose mode.

As described above, according to the high speed mode switching device of the CDG playback system according to the present invention, the oscillation capacity of the oscillator is variably controlled based on the phase synchronization state of the external horizontal synchronization signal and the internal horizontal synchronization signal, and both horizontal synchronization signals are used. By switching the CDG mode to the superimpose mode at a high speed without matching the full-in time, the stabilization of the system can be achieved even if frequent mode switching is performed in the CDG playback system.

Claims (3)

Synchronous detection / separation means (10,20) for detecting and synchronously separating the external horizontal synchronous signal and the external vertical synchronous signal from the external video signal, and a CDG decoder (30) for decoding the graphic information recorded in the western code on the CDG disc; PLL circuit means for controlling phase synchronization so that the phase difference is compensated by comparing the phase of the external horizontal synchronization signal from the synchronization separating unit 20 with the internal horizontal synchronization signal from the CDG decoder, and the composite synchronization from the CDG decoder 30. Based on the signal, an external video signal according to the RGB encoder 80 for encoding R, G, and B color signals for graphic information applied from the CDG decoder 30 and the superimposition timing signal from the CDG decoder 30. And a switching unit (90) for mode-shifting and superimposing graphic signals from the RGB encoder at high speed, wherein the PLL circuit means is internally synchronized with the CDG internal mode. And a phase synchronous detector 12 for detecting a phase synchronous state of the external synchronous signal to generate a signal for varying the generated frequency, and a capacitance based on the oscillation frequency variable signal generated by the phase synchronous detector 12. An oscillator oscillating oscillating a high speed synchronization signal based on a phase compensation control signal from the phase compensator 50 according to the phase comparison result of the phase comparator 40 when the mode is switched between the CDG internal mode and the superimpose mode ( 60. A fast mode switching device for a CDG playback system, comprising: The phase synchronization detector (70) constituting the PLL circuit means includes: an inverter (71) for inverting an internal horizontal synchronization signal, a pulse generator (72) for generating an inversion pulse of an external horizontal synchronization signal, and D flip-flop (73) for receiving the internal horizontal synchronizing signal inverted by the inverter (71) as a data input and outputting the phase synchronizing detection result at the inverting output stage using the external synchronizing base pulse of the pulse generator (72) as a clock signal. High speed mode switching device of the CDG playback system, characterized in that the configuration. The oscillator 60 of the PLL circuit means is connected to the transistor 61 which is switched and controlled by the phase synchronous detection result of the phase synchronous detector 70, and the emitter side of the transistor 61. A first capacitor 62 which determines the capacitance of the oscillation element 64 when switching on, a second capacitor 63 coupled to the collector side of the transistor 61 to set the variable capacitance of the oscillation element 64, An inverter 65 for stabilizing an oscillation signal of the oscillation element 64 by the first and / or second capacitors 63, the first and / or second capacitors 62, 63, and the external horizontal synchronization signal. And a varactor diode (67) for adjusting the oscillation potential of the oscillation element (64) by changing the capacitance by the phase difference of the internal horizontal synchronization signal.