KR940006886B1 - Graphic signal and video signal filing-up system - Google Patents

Abstract

The superposing circuit adding graphic signal and video signal comprises a synchronizing signal separator (220) extracting the horizontal/vertical synchronizing signal; a reset circuit (230) initilizing the CRT controller; a decorder (240) separating the intensity signal and the chromatic signal; a lock detector (270) confirming the locking state of the external video signal and the internal graphic video signal; a phase comparator (250) generating the phase difference signal between two video signals; a VCO (310) generating color subcarrier signal; an encorder (320) producing the composite signal; a switch (330) superposing the graphic signal and video signal.

Description

Superposition system of graphic signal and video signal

1 is a block diagram of a conventional graphic signal processing system.

2 is an overall block diagram of a superposition system of a graphic signal and a video signal according to an embodiment of the present invention.

3 is a circuit diagram of a phase comparator, a lock detector, a voltage controlled oscillator, and a reset unit according to an embodiment of the present invention.

4 is a detailed circuit diagram of a switching switch unit according to an embodiment of the present invention.

The present invention relates to a superposition system of a graphic signal and a video signal. More specifically, the present invention relates to a graphic signal stored in a compact disc (CD) and an external device stored in a medium such as a laser disc (LD). A superimposition system of a graphic signal and a video signal capable of superimposing a video signal.

The optical compact disc, developed and released by Philips of the Netherlands in 1978, has since been put into practical use by a compromise with Sony, Japan, and its standards have been established and started to be commercialized by each company in 1982. did

Compact discs have a tiny pit in microns (μ) that is hard to see with the naked eye, which is aligned with regularity and spirals outward from the center of the compact disc. This spiral wound pit group is called a track.

When the track of the compact disc is enlarged, a specific pit arrangement is repeated which is repeated at regular intervals. This specific pit arrangement is used as a synchronization signal, and the pitable force from one synchronization signal to the next synchronization signal is framed. It is called. In such a frame, a graphic image information such as a still picture, a sub code containing various kinds of service information, and the like are recorded, starting with a synchronization signal indicating the head of the frame.

In order to reproduce a graphic signal such as a still picture signal recorded on the R to W channel of a compact disc on a screen of a display device such as a television as described above, R, G, The B data signal needs to be converted into a composite video signal for graphics. Such a conversion device is called a graphic signal processing system.

Hereinafter, a conventional graphic signal processing system will be described with reference to the accompanying drawings.

1 is a block diagram of a conventional graphic signal processing system. As shown in FIG. 1, the structure of a conventional graphic signal processing system includes a graphic decoder 110 having an input terminal connected to a data signal line CDS, and a composite synchronization signal line CSYNC of the graphic decoder 110. A color burstgate pulse generator 120 connected to an input terminal, a VCO (Voltage Controlled) having an input terminal connected to an output terminal of the frequency signal line Fsc and the killer burst gate pulse generator 120 of the graphic decoder 110. Oscillator 130, the graphic decoder 110, the color burst gate pulse generator 120 and the encoder 140 is connected to the output terminal of the output terminal of the VCO (130).

The encoder unit 140 includes an RGB matrix 141 connected to an input terminal of the color signal lines R, G, and B of the graphic decoder 110, and color difference signal lines BY and RY of the RGB matrix 141. A low pass filter (142, 143) having an input terminal connected to each other, a modulator (144, 145) having an input terminal connected to an output signal line of the VCO 130 and an output terminal of the low pass filter (142, 143), and a color burst gate pulse generator. A control terminal is connected to the output signal line of 120 and a switch SW41 is connected to one terminal of the output signal line of the VCO 130.

The operation of the conventional graphic signal processing system according to the above configuration is as follows.

The color signals R, G, and B are decoded by the graphic decoder 110 from the subcode of the data signal CDS input from the compact disc to the graphic decoder 110, so that the encoder 140 and the color burst gate pulse generator ( 120).

The RGB matrix 141 of the encoder 140 generates and outputs a luminance signal Y and a color difference signal B-Y and R-Y using the color signals R, G, and B input from the graphic decoder 110. The color difference signals B-Y and R-Y output from the RGB matrix 141 are input to the modulators 144 and 145 after the high pass components are removed through the low pass filters 142 and 143.

The modulators 144 and 145 use a lowpass filter using the color subcarrier signal input from the VCO 130 controlled by the output signal of the Curly Burst Gate pulse generator 120 and the frequency signal Fsc of the graphics decoder 110. Output signals by modulating (142,143) output signals. The output signals of the low pass filters 144 and 145 are combined with each other, and then synchronized with the operation of the switch SW41 controlled by the signal output from the killer burst gate pulse generator 120 to synchronize the composite synchronization signal CSYNC and By combining with the luminance signal Y, it becomes a composite video signal which is the final output signal and is output to an external display device such as a television.

However, the conventional graphic signal processing system has a disadvantage of processing and reproducing only a graphic signal recorded on a compact disc. This drawback is inconvenient to use the signals stored in other media, such as laser disks, in providing an audio / video system that can make viewers feel more vivid.

Accordingly, an object of the present invention is to solve the above-mentioned disadvantages, and it is possible to superimpose a graphic signal recorded on a compact disc and an external video signal recorded on another storage medium such as a laser disc, and have high stability and response. It is to provide a superimposition system of a fast time graphic signal and a video signal.

A configuration of the present invention for achieving the above object comprises a synchronization detector for detecting the presence or absence of input of an external video signal; A synchronization separator for separating vertical and horizontal synchronization signals from an external video signal; A reset unit for outputting a reset signal for a CRT controller when an external video signal is input; A graphics decoder for separating color signals and sync signals from data signals read out from a compact disc and inputted therein; A lock detector which detects whether the horizontal synchronizing signal of the external video signal and the horizontal synchronizing signal of the graphic signal are synchronized with each other and which can change the position of the overlapping graphic screen from side to side; A phase comparison unit for calculating a phase difference between the horizontal synchronization signal of the external video signal and the horizontal synchronization signal of the graphic signal; A phase compensator for compensating the phase difference signal of the phase comparator; A voltage controlled oscillator for outputting a clock signal synchronized using the output signals of the phase compensator and the lock detector; A switching switch unit which preferentially switches and transfers an external video signal among the external video signal and an output signal of the graphic decoder; A color burst gate pulse generator connected to the graphics decoder; A VCO for generating a color subcarrier signal in accordance with the signal transmitted from the switching switch; An encoder for generating a composite video signal; Switching is performed according to the superimposition timing signal inputted from the graphic decoder, so as to superimpose the external video signal and the output video signal of the encoder.

With reference to the accompanying drawings, a preferred embodiment of the present invention by the above configuration will be described in detail.

2 is an overall block diagram of a superposition system of a graphic signal and a video signal according to an embodiment of the present invention. As shown in FIG. 2, the configuration of the superimposition system of the graphic signal and the video signal according to the embodiment of the present invention includes a sync detector 210 and a sync separator 220 having an input terminal connected to an external video signal line EVS, respectively. The reset unit 230 having an input terminal connected to the output signal line DN of the sync detector 210 and the vertical sync signal line V-SYNC of the sync separator 220, and an output signal line of the reset unit 230 ( ) And a graphic decoder 240 having an input terminal connected to the data signal line CDS, a horizontal sync signal line H-SYNC of the sync separator 220, and a horizontal sync signal line HSYNC of the graphic decoder 240, respectively. A phase compensator 260 connected to the phase comparator 250 and the lock detector 270, an output signal line DN of the synchronization detector 210, an output signal line of the phase comparator 250, and a phase compensator; A voltage controlled oscillator 280 having an input terminal connected to an output terminal of the unit 260 and the lock detector 270, an output signal line DP of the external video signal line EVS, the synchronization detector 210, and a frequency of the graphic decoder 240. A switching switch unit 290 having an input terminal connected to the signal line Fsc, a color burst gate pulse generator 300 having an input terminal connected to the horizontal synchronization signal line HSYNC of the graphic decoder 240, and a switching switch unit 290. The VCO 310 having an input terminal connected to an output terminal of the color burst gate pulse generator 300, and An output terminal (CSYNC, R, G, B) of the decoder 240, an output terminal of the color burst gate pulse generator 300 and an output terminal of the VCO 310, an external video signal line EVS, The input terminal is connected to an output terminal of the encoder 320 and an overlapping timing signal line ST of the graphic decoder 240.

3 is a detailed circuit diagram of a phase comparator, lock detector, voltage controlled oscillator, and reset unit according to an embodiment of the present invention. As shown in FIG. 3, the configuration of the phase compensator 260 according to the exemplary embodiment of the present invention includes a resistor R261 connected to one terminal of an output signal line of the phase comparator 250 and another resistor R261. The inverting input terminal is connected to one terminal and the non-inverting input terminal is grounded op amp OP26l, capacitor C261 with one terminal connected to the inverting input terminal of the op amp OP261, and the other side of the capacitor C261. A resistor is connected between the terminal and the output terminal of the operational amplifier OP261, a resistor R263 connected to one end of the output terminal of the operational amplifier OP261, and a collector connected to the other terminal of the resistor R263. The emitter consists of a grounded transistor Q261 and a resistor R264 connected between the base of the transistor Q261 and the output signal line DN of the synchronization detector 210.

In addition, the lock detector 270 is configured to be input to an inverter I271 having an input terminal connected to the horizontal sync signal line HSYNC of the graphic decoder 240 and to a horizontal sync signal line H-SYNC of the sync separator 220. A pulse generator 271 connected with a terminal and an input terminal D are connected to an output terminal of the inverter I271 and a D-type flip-flop 272 connected to a clock terminal to an output terminal of the pulse generator 271.

The voltage controlled oscillator 280 includes a resistor R281 connected to one terminal of the inverted output terminal (-Q) of the D flip-flop 272 of the lock detector 270 and the other of the resistor R281. A transistor Q281 having a base connected to the terminal, a capacitor C281 connected between the emitter of the transistor Q281 and the ground, a variable capacitor C282 connected between the collector and the ground of the transistor Q281, and a phase compensator A resistor R283 having one terminal connected to the collector of transistor Q261 at 260, a varactor diode D281 having a cathode connected to the other terminal of the resistor R283, and an anode of the varactor diode D281; Inverter I281 and inverter I281 connected to a resistor R284 and capacitor C284 respectively connected between ground, an input terminal connected to the other terminal of capacitor C283, and an output terminal connected to the collector of transistor Q281. Resistor (R282) connected between the input and output terminals of Modification is made to the oscillator (X281), an inverter (I282) input terminals coupled to the output terminal of the inverter (I281).

The reset unit 230 includes a resistor R231 having one terminal connected to the horizontal synchronization signal line HSYNC of the graphic decoder 240, and a collector connected to the other terminal of the resistor R231 and having a synchronization detector 210. The base is connected to the output signal line (DN) of the () and the emitter is a grounded transistor (Q231), and the inverter (I231) connected to the input terminal to the collector of the transistor (Q231).

4 is a detailed circuit diagram of a switching switch unit according to an embodiment of the present invention.

As shown in FIG. 4, the configuration of the switching switch unit according to the embodiment of the present invention includes a transistor Q291 connected to the base of the output signal line DP of the synchronization detector 210 and the emitter is grounded, and the graphic decoder 240. Resistor R291 connected between the frequency signal line Fsc of the transistor and the collector of the transistor Q291, the coils L2291 and the capacitor C291 connected between the collector of the transistor Q291 and ground, respectively, A capacitor C292 having one terminal connected to the collector of Q291), a transistor Q292 having a base connected to the other terminal of the capacitor C292 and a collector connected to the power supply voltage Vcc, and a base of the transistor Q292; A resistor R292 coupled between the power supply voltage Vcc, a resistor R293 coupled between the base of the transistor Q292 and ground, a resistor R294 coupled between the emitter and ground of the transistor Q292, and a transistor Emitter and external zero at (Q292) The resistor R295 is connected between the phase signal line EVS.

The operation of the overlapping system of the graphic signal and the video signal according to the embodiment of the present invention by the above configuration is as follows.

Generally, compact discs include music accompaniment (commonly referred to as "karaoke"), storytelling, and educational purposes.The graphic signals output from the music accompaniment compact disc are all on the background color except for the beginning and end of the song. In order to provide the viewer with an image containing a scene related to a song, it is required to heavy-chip the graphic signal output from the compact disc to an external video signal (EVS) output from a medium such as a laser disc. Gina's compact or educational compact discs are complete with graphics signals stored on the compact disc itself and do not need to be superimposed with an external video signal (EVS).

The synchronization detector 210 detects whether the external video signal EVS is being input, outputs a high output signal DP when the external video signal EVS is input, and outputs the external video signal EVS. ) Outputs the output signal DP in the low state. The two signals DP and DN output from the synchronization detector 210 are signals having complementary values to each other.

In addition, the synchronization separator 220 outputs the vertical synchronization signal V-SYNC in the high state to the reset unit 230 when the external video signal EVS is input.

Therefore, when the external image signal EVS is input, the output signal of the inverter I231 of the reset unit 230 is turned off by turning off the transistor Q231 of the reset unit 230. ) Is reset to reset the CRT controller (not shown) inside the graphics decoder 240.

At this time, in order to superimpose the graphic signal of the compact disc with the external video signal EVS, the vertical and horizontal synchronizing signals of the compact disc graphic signal must be accurately synchronized with the vertical and horizontal synchronizing signals of the external projection signal EVS, and the encoder ( The color subcarrier signal used at 320 must also be synchronized with the external color burst gate pulse.

In order to vertically synchronize the external video signal EVS and the compact disc graphic signal, the graphics decoder 240 may have a vertical synchronization signal V-SYNC separated from the external video signal EVS by the synchronization separation unit 220. The horizontal sync signal HYNC generated by dividing the clock signal inside the graphic decoder 240 and the horizontal sync signal H-SYNC separated by the sync separator 220 after resetting the CRT controller in FIG. Is applied to the phase comparator 250.

The phase comparator 250 obtains a phase difference between the horizontal sync signal H-SYNC input from the sync separator 220 and the horizontal sync signal HYNC input from the graphic decoder 240, and supplies the phase compensator 260 with the phase compensator 260. Output

The phase compensator 260 amplifies and phase-compensates the circuit after the phase difference signal input from the phase comparator 250 using an op amp OP261, a capacitor C261, and the like, and then outputs the voltage to the voltage controlled oscillator 280. do. When the external image signal EVS is input, since the transistor Q261 of the phase compensator 260 is turned off, the output signal of the amplification and phase compensating circuit including the operational amplifier OP261 and the capacitor C261 is turned off. The output is normally output to the voltage controlled oscillator 280.

The voltage controlled oscillator 280 uses a signal input from the phase compensator 260 and a signal input from the lock detector 270 to synchronize the two horizontal synchronizing signals H-SYNC and HSYNC with each other. CLK) to the graphics decoder 240.

The lock detector 270 receives the horizontal sync signal H-SYNC from the sync separator 220 and the horizontal sync signal HSYNC from the graphic decoder 240 to receive the D-type flip-flop 272. The two horizontal synchronization signals H-SYNC and HSYNC are detected to be synchronized with each other, and output to the voltage controlled oscillator 280. That is, when two input signals (H-SYNC, HSYNC) are synchronized with each other, a low signal ( ) And high signal when two input signals (H-SYNC, HSYNC) are not synchronized with each other. )

Therefore, when the two horizontal synchronizing signals H-SYNC and HSYNC are not synchronized with each other, the transistor Q281 of the voltage controlled oscillator 280 is turned off so that the capacitor C281 is not connected to the capacitor C282 in parallel. As a result, the two horizontal synchronizing signals (H-SYNC, HSYNC) try to pass through each other at a high speed.

However, the inversion of the D-type flip-flop 272 at the moment when the rising edge of the output pulse of the pulse generator 271 that generates the pulse by inputting the horizontal synchronizing signal H-SYNC meets the low portion of the horizontal synchronizing signal HSYNC. Output signal ) Is in a high state, and the transistor Q281 of the oscillator 280 is turned on so that the capacitor C281 is connected in parallel with the capacitor 282 so that the two horizontal synchronizing signals HSYNC and H-SYNC are completely synchronized at that moment. .

At this time, the phase difference between the two horizontal synchronizing signals (HSYNC, H-SYNC) synchronized with each other is changed according to the output pulse width of the pulse generator 271. Therefore, the position of the compact disc graphic screen superimposed on the external screen can be moved left and right on the television screen.

As can be seen from above, the phase comparator 250, the phase compensator 260, the lock detector 270, and the voltage controlled oscillator 280 constitute a phase locked loop (PLL) circuit. In the case of using a general PLL, the speed of switching from the graphics processing mode to the superimposition mode is the initial frequency and phase difference between the two signals input to the phase comparator 250 and the total loop gain and phase compensator 260. It is related to the pull-in time (the time taken for the PLL to be synchronized) having a functional relationship with the filter band and the like.

In order to reduce the pull-in time, the overall loop gain of the PLL and the filter band of the phase compensator 260 should be increased. However, in this case, the stability is lowered. On the contrary, if the filter band is reduced, the steady state error is small but the pull-in Time increases. In the embodiment of the present invention, two horizontal synchronizing signals H-SYNC and HSYNC are instantaneously using the lock detector 270, the transistor Q281 and the capacitor C281 of the voltage controlled oscillator 280 as described above. By using the PLL to reach steady state, it is possible to provide a system with high stability and low pull-in time.

As the synchronous frequency signal Fsc is output from the graphic decoder 240, the switching switch unit 290 may synchronize the synchronous frequency signal Fsc of the graphic decoder 240 when the external image signal EVS is not input. ) To the VCO 310. However, when the external image signal EVS is input, the transistor Q291 of the switching switch unit 290 is turned on so that the synchronization frequency signal Fsc input from the graphic decoder 240 is cut off, thereby causing the external image signal EVS. Is output to the VCO 300.

The VCO 310 uses a signal input from the color burst gate pulse generator 300 when an external image signal EVS is input, and an external image signal EVS transmitted through the switching switch unit 290. After generating the color subcarrier signal, the color subcarrier signal is output to the encoder 320. In this way, a color subcarrier synchronized with the horizontal synchronizing signal H-SYNC is obtained, and a graphic screen reproduced by being superimposed faithfully on the external screen can be obtained.

However, when there is no input of the external video signal EVS, the transistor Q291 of the switching switch unit 290 is turned off and output from the graphic decoder 240, and is turned on by the transistor Q292 of the switching switch unit 290. When the amplified sync frequency signal Fsc is input, the VCO 300 uses a signal input from the color burst gate pulse generator 300 and a sync frequency signal Fsc transmitted through the switching switch unit 290. After generating the color subcarrier signal, the color subcarrier signal is output to the encoder 320. Therefore, by obtaining a color subcarrier synchronized with the horizontal synchronizing signal HSYNC, a stable graphic screen can be reproduced.

The encoder 320 uses the color subcarrier signal input from the VCO 310, the output signal of the color burst gate pulse generator 300, and the signals CSYNC, R, G, and B output from the graphic decoder 240. A composite video signal is generated and output to the overlap switch 330. In this case, the composite video signal output from the encoder 320 is synchronized with the external video signal EVS. Since the signal processing performed inside the encoder 320 is the same as the conventional graphic signal processing system, description thereof will be omitted to avoid duplication.

When the composite video signal and the external video signal EVS output from the encoder 320 are input to the overlap switch 330, the overlap switch 330 switches according to the overlap timing signal ST input from the graphic decoder 240. As a result, the external video signal EVS overlaps the composite video output signal of the encoder 320.

However, when the external image signal EVS is not being input, the transistor R264 of the phase compensator 260 is turned on by the high signal DN output from the synchronization detector 210, so that the voltage controlled oscillator ( 280 is applied to the low signal. Accordingly, a clock signal CLK having a frequency according to the oscillation signal of the voltage controlled oscillator 280 is generated and output to the graphic decoder 240, thereby switching to a mode for processing only a graphic signal.

As described above, in the exemplary embodiment of the present invention, the graphic signal recorded on the compact disk and the external video signal recorded on another storage medium such as a laser disk can be superimposed on each other, and the response time is high while the stability is high. It is possible to provide a superposition system of the graphics signal and the video signal. This effect of the invention can be used in the field of audio / video equipment.

Claims (5)

A synchronization detector for detecting the presence or absence of input of an external video signal; A synchronization separator for separating vertical and horizontal synchronization signals from an external video signal; A reset unit for outputting a reset signal for a CRT controller when an external video signal is input; A graphic decoder for separating color signals and sync signals from data signals read out from a compact disc and inputted therein; A lock detector which detects whether the horizontal synchronizing signal of the external video signal and the horizontal synchronizing signal of the graphic signal are synchronized with each other and which can change the position of the overlapping graphic screen from side to side; A phase comparison unit for obtaining a phase difference between a horizontal synchronization signal of an external video signal and a horizontal synchronization signal of a graphic signal; A phase compensator for compensating the phase difference signal of the phase comparator; A voltage controlled oscillator for outputting a clock signal synchronized using the output signals of the phase compensator and the lock detector; A switching switch unit which preferentially switches and transfers the external video signal among the external video signal and the output signal of the graphic decoder; A color burst gate pulse generator coupled to the graphics decoder; A VCO for generating a color subcarrier signal in accordance with a signal transmitted from a switching switch; An encoder for generating a composite video signal; A superimposition system of a graphic signal and a video signal, comprising: a superposition switch for switching an external video signal and an output video signal of an encoder by switching according to the superimposition timing signal input from the graphic decoder. The non-inverting input terminal of claim 1, wherein the phase compensator has a resistor R261 connected to one terminal of an output signal line of the phase comparator 250 and an inverting input terminal connected to the other terminal of the resistor R261. Is connected between a grounded operational amplifier OP261, a capacitor C261 having one terminal connected to an inverting input terminal of the operational amplifier OP261, and the other terminal of the capacitor C261 and an output terminal of the operational amplifier OP261. A resistor (R263), a resistor (R263) having one terminal connected to the output terminal of the operational amplifier OP261, a collector connected to the other terminal of the resistor (R263), and the emitter connected to a ground (Q261); And a resistor (R264) connected between the base of (Q261) and the output signal line (DN) of the synchronization detection unit (210). 2. The lock detector of claim 1, wherein the lock detector is connected to an inverter I271 connected to an input terminal of the horizontal sync signal line HSYNC of the graphic decoder 240, and to a horizontal sync signal line H-SYNC of the sync separator 220. A pulse generator 271 connected to an input terminal, and a D-type flip-flop 272 connected to an output terminal of the inverter I271 and a clock terminal connected to an output terminal of the pulse generator 271. Characterized in the chip and video signal of the chip system. The inverting output terminal of the D-type flip-flop 272 of the lock detector 270 is formed. Resistor R281 connected to one terminal thereof, transistor Q281 having a base connected to the other terminal of resistor R281, capacitor C281 connected between the emitter of transistor Q281 and ground, and a transistor ( A variable capacitor C282 connected between the collector of Q281 and ground, a resistor R283 connected at one terminal to the collector of transistor Q261 of the phase compensator 260, and a cathode at the other terminal of the resistor R283. Is connected to the varactor diode (D281), the resistor (R284) and capacitor (C284) connected between the anode and the ground of the varactor diode (D281), and a capacitor connected to one terminal of the cathode of the varactor diode (D281). C283 and an inverter I281 having an input terminal connected to the other terminal of the capacitor C283 and having an output terminal connected to the collector of the transistor Q283, and a resistor R282 connected between the input terminal and the output terminal of the inverter I281. ) And crystal oscillator (X281) And an inverter (I282) having an input terminal connected to an output terminal of the inverter (I281). The transistor of claim 1, wherein the switching switch unit has a base connected to an output signal line DP of the synchronization detector 210, and an emitter is grounded, a frequency signal line Fsc of the graphic decoder 240, and a transistor. A resistor (R291) connected between the collector of (Q291), the coil (L291) and capacitor (C291) connected between the collector and ground of the transistor (Q291), respectively, and a capacitor having one terminal connected to the collector of the transistor (Q291). C292, a transistor Q292 having a base connected to the other terminal of the capacitor C292 and a collector connected to the power supply voltage vcc, and a resistor R292 connected between the base of the transistor Q292 and the power supply voltage Vcc. ), A resistor R293 connected between the base of the transistor Q292 and ground, a resistor R294 connected between the emitter of the transistor Q292 and ground, an emitter of the transistor Q292 and an external video signal line ( Resistor (R29) connected between EVS 5) a superimposition system of a graphic signal and a video signal.