JPS61229316A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61229316A
JPS61229316A JP60071721A JP7172185A JPS61229316A JP S61229316 A JPS61229316 A JP S61229316A JP 60071721 A JP60071721 A JP 60071721A JP 7172185 A JP7172185 A JP 7172185A JP S61229316 A JPS61229316 A JP S61229316A
Authority
JP
Japan
Prior art keywords
substrate
semiconductor layer
semiconductor
seed
single crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60071721A
Other languages
Japanese (ja)
Inventor
Hisao Hayashi
久雄 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP60071721A priority Critical patent/JPS61229316A/en
Publication of JPS61229316A publication Critical patent/JPS61229316A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To increase the area of heat radiation using a seed part as well as to expand the region which is turned to single crystal by a method wherein a heat radiating region, with which the direction of recrystallization of a semiconductor layer is determined, is formed on a substrate. CONSTITUTION:After the semiconductor layer 3 on a substrate having an insulative surface is fused, it is recrystallized and formed into a semiconductor device. At that time, a heat radiating region 4 with which the direction of recrystallization of the semiconductor layer 3 is formed is provided on the substrate. As a result, the part on which heat is radiated through a seed part 1a when the semiconductor layer 3 is fused and recrystallized, is expanded and the region which is turned to single crystal is increased in the amount of the above-mentioned expansion of the heat radiating part.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は表面が絶縁性である基板上の半導体層ｔ？浴融
した後再結晶化する様にした半導体装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a semiconductor layer t? on a substrate whose surface is insulating. The present invention relates to a semiconductor device which is recrystallized after being melted in a bath.

〔発明の概要〕[Summary of the invention]

本発明は例えば半導体基板の一部ｔ−ａｔ結晶として、
この半導体基板上の絶縁層上の半導体ＮＩＩを浴融した
後再結晶化する様にした半導体装置において、この半導
体基板にこの半導体層の再結晶化方向を決定する熱放散
領域を形成して、種結晶よりより遠くまで単結晶を得る
様にしたものである。The present invention can be applied, for example, as a part of a t-at crystal of a semiconductor substrate.
In the semiconductor device in which the semiconductor NII on the insulating layer on the semiconductor substrate is bath-melted and then recrystallized, a heat dissipation region that determines the recrystallization direction of the semiconductor layer is formed on the semiconductor substrate, This allows single crystals to be obtained further away from the seed crystal.

〔従来の技術〕[Conventional technology]

先に、第２図に示す如くシリコンの半導体基板の一部を
種結晶としてこの半導体基板上の絶縁層上に単結晶薄膜
を形成し、半導体基板の他にこの単結晶薄膜にも素子を
形成する様にし、３次元的に素子を形成する様にした半
導体装置が提案されている。First, as shown in FIG. 2, a single crystal thin film is formed on the insulating layer on this semiconductor substrate using a part of a silicon semiconductor substrate as a seed crystal, and elements are formed on this single crystal thin film in addition to the semiconductor substrate. A semiconductor device has been proposed in which elements are formed three-dimensionally.

斯る第２図に示す如き半導体ａｔを製造する場合シリコ
ンの半導体基板（１）上を種部（１１）を残してエツチ
ングして穴部を形成し、この穴部に有機浴剤に溶かした
ガラスであるスピンオングラス（ＳＯＧ）を注入し、そ
の後熱処理して５ｔＯ２のｌｅ縁鳩（２）を形成し、そ
の後この絶縁層（２）の上面を研磨して平坦にすると共
に種部（ｌ＆）を露呈するようにし、その上に例えはシ
ランガス（ＳｉＨ２）を用いたＣｖＤにより多結晶のシ
リコン（８１）ＩＩ（３）ｔ−被着し、その後この多結
晶５ｉｌｉ！（３）を電子ビーム等の解融再結晶を行い
薄膜単結晶半導体層を形成するようにしていた。When manufacturing a semiconductor AT as shown in FIG. 2, a silicon semiconductor substrate (1) is etched to form a hole, leaving a seed portion (11), and an organic bath agent is dissolved in the hole. Spin-on glass (SOG), which is glass, is injected and then heat treated to form a 5tO2 layer (2), and then the top surface of this insulating layer (2) is polished to make it flat and a seed part (L&). is exposed, polycrystalline silicon (81)II(3)t- is deposited thereon by CVD using silane gas (SiH2), and then this polycrystalline 5ili! (3) was melted and recrystallized using an electron beam or the like to form a thin single crystal semiconductor layer.

〔発明が解決しようとする間哩点〕[The intermittent point that the invention attempts to solve]

斯る第２図に於いて溶融再結晶によシ薄膜単結晶半導体
層（３）ヲ得る場合例えば電子ビームで走査された場合
でも、このビームサイズ、ビームの速度に比して種部（
１為）及びこの種部（１ａ）に連続して得られる再結晶
半導体層（３）の幅が小さいときは定常的に多結晶ｓｉ
層（３）は全面溶けて、熱の一番速く逃ける（この場合
熱伝導率はＳｔの方が絶縁＃（２）である８１０２よシ
大きい。）種部（１１）から固化が始まり、そして、こ
の種部（１ａ）がヒートシンクとなって徐々に横方向に
固化していく。ところが種部（１＆）からある程度以上
離れた所ではこの種部（１ａ）よシも下側に存する絶縁
層（８１０２Ｎｊ　）　（２）ｆｆｉ通して勢の逃げが
大きく、種部（１ａ）とは関係なく固化してし１い、こ
の領域は単結晶とならない不都合があった。When the thin film single crystal semiconductor layer (3) is obtained by melt recrystallization in FIG. 2, for example, even when scanned with an electron beam, the seed portion (
1) and when the width of the recrystallized semiconductor layer (3) continuously obtained in this seed part (1a) is small, the polycrystalline Si
Layer (3) melts all over, and heat escapes the fastest (in this case, the thermal conductivity of St is higher than that of 8102, which is insulation #(2)). Solidification begins from the seed part (11), This seed portion (1a) then becomes a heat sink and gradually solidifies in the lateral direction. However, at a certain distance from the seed part (1&), there is a large escape of force through the insulating layer (8102Nj) (2)ffi that exists below the seed part (1a), and the difference between the seed part (1a) and the However, this region had the disadvantage that it would not become a single crystal.

斯る単結晶とならない領域をなくす為には第３図に示す
如く第２図の絶縁１ｉｉ　（８１０２層）（２）を種部
（］＆）から離れるに従って順次その層厚を厚くするこ
とが考えられる。In order to eliminate such a region that does not become a single crystal, as shown in FIG. 3, the layer thickness of insulation 1ii (8102 layer) (2) in FIG. Conceivable.

然しなから、半導体基板（１）に傾斜したエツチングを
行うことは極めて困難であり実用的でない。However, it is extremely difficult and impractical to perform inclined etching on the semiconductor substrate (1).

本発明は斯る点に鑑み作成が容易で種部（１ｍ）よシよ
り遠くまで単結晶が得られる様にすることを目的とする
。In view of these points, it is an object of the present invention to make it possible to easily produce a single crystal and to obtain a single crystal from a distance beyond the seed part (1 m).

［問題点を解決するための手段〕 本発明は第１図に示す如く少なくとも表面が絶縁性であ
る基板上の半導体層（３）全溶融した後再結晶化してな
る半導体装置において、この基板にこの半導体＠　（３
）の再結晶化方向を決定する熱放牧領域（４）を形成し
たものである。[Means for Solving the Problems] As shown in FIG. 1, the present invention provides a semiconductor device in which a semiconductor layer (3) on a substrate having at least an insulating surface is completely melted and then recrystallized. This semiconductor @ (3
) is formed with a thermal grazing region (4) that determines the recrystallization direction.

〔作用〕[Effect]

斯る本発明に依れは基板に半導体Ｎ（３）の再結晶化方
向を決定する熱放＃、領域（４）全形成したので種部（
１ａ）に関連して熱放牧がなされる領域が増大し、との
種部（１ａ）よりよシ遠く１で単結晶を得ることができ
る。According to the present invention, since the heat dissipation region (4) which determines the recrystallization direction of the semiconductor N (3) is completely formed on the substrate, the seed part (
In relation to 1a), the area subjected to thermal grazing is increased, and single crystals can be obtained further away from the seed part (1a).

［実施例］ 以下第１図を参照しながら本発明半導体装置の一実施例
につき説明しよう。この第１図に於いて第２図及び第３
図に対応する部分には同一符号を付し、その詳細説明は
省略する。[Embodiment] An embodiment of the semiconductor device of the present invention will be described below with reference to FIG. In this figure 1, figures 2 and 3
Portions corresponding to those in the figures are given the same reference numerals, and detailed explanation thereof will be omitted.

本例に依る半導体装置の構成を製造工程に従って説明す
るに、シリコンの半導体基板（１）の−面側に先ず第２
図に示す如く種部（１ｍ）’を残してエツチングによシ
所定深さの穴部を形成し、その後この穴部に種部（１ａ
）より遠ざかるに従って順次幅が広くなく所定深さの溝
（４ｍ）　、　（４ｂ）　、　（４ｃ）・・・（４ｈ）
を形成する。この穴部及びｕ　（４ｍ）　、　（４ｂ）
　、　（４ａ）・・・（４ｈ）に有機浴剤に浴かしたガ
ラスであるスピンオングラス（ＳＯＧ）　ｉ注入し、そ
の後熱処理してこのＳＯＧをＳＩＯ□とし、絶縁層（２
）及びその絶縁＃　（２）の下側に種部（１ａ）よシ遠
ざかるに従って熱伝導性が悪くなる再結晶方向を決定す
る熱放牧領域（４）全形成する。To explain the structure of the semiconductor device according to this example according to the manufacturing process, first, a second
As shown in the figure, a hole with a predetermined depth is formed by etching, leaving a seed part (1m)', and then the seed part (1a) is placed in this hole.
) The grooves gradually become wider as they get further away, but have a predetermined depth (4m), (4b), (4c)...(4h)
form. This hole and u (4m), (4b)
, (4a)...(4h), spin-on glass (SOG), which is glass bathed in an organic bath agent, is injected and then heat treated to form SIO□, and an insulating layer (2
) and its insulation # (2), a thermal grazing region (4) which determines the direction of recrystallization where the thermal conductivity worsens as it gets farther away from the seed part (1a) is entirely formed.

その後このＳｌＯ□の絶縁層（２）の上面全研磨して平
坦にすると共に種部（ｌａ）　ｔ−露呈するようにし。Thereafter, the entire upper surface of this SlO□ insulating layer (2) was polished to make it flat and to expose the seed portion (la) t-.

その上に例えばシランガス（８１Ｈ４）　？用いたＣＶ
Ｄにより所足厚の多結晶のシリコン（ｓｉ）層（３）を
被着する。その後、この多結晶５ｌｌ（３）を電子ビー
ム等の溶融再結晶を行い薄膜単結晶半導体層とする。こ
の場合多結晶Ｓ口１３）は全面溶けて熱の一番速く逃げ
る種部（１ｍ）から固化が始まり、そして、この種部（
１ａ）がヒートシンクとなって徐々に横方向ｑ化してい
く。このとき本例に於いては種部（１ｍ）より遠ざかる
に従って基板の熱伝導性が悪くなっているので、この種
部（１＆）より比較的遠くに離れた所でもこの溶融８１
層（３）の熱放散はこの種部（１ｋ）を通して行なわれ
単結晶となる領域を拡大することができる。その他は従
来のものと同様に構成する。On top of that, for example, silane gas (81H4)? CV used
A polycrystalline silicon (Si) layer (3) of sufficient thickness is deposited by step D. Thereafter, this polycrystal 5ll(3) is melted and recrystallized using an electron beam or the like to form a thin film single crystal semiconductor layer. In this case, the entire surface of the polycrystalline S port 13) melts, and solidification begins from the seed part (1 m) where heat escapes fastest, and then this seed part (1 m) begins to solidify.
1a) becomes a heat sink and gradually becomes q in the lateral direction. At this time, in this example, since the thermal conductivity of the substrate becomes worse as the distance from the seed part (1 m) increases, this melting 81
Heat dissipation from the layer (3) takes place through this seed portion (1k), making it possible to expand the area of the single crystal. The rest of the structure is the same as the conventional one.

本例に依れば多結晶ＳＩＩ曽（３）を溶融再結晶すると
きに種部（１ａ）を通して熱放散が行なわれる部分が拡
大するので、それだけ単結晶となる領域が拡大する。According to this example, when melting and recrystallizing the polycrystalline SII (3), the area where heat is dissipated through the seed part (1a) is expanded, so the area that becomes a single crystal is expanded accordingly.

尚上述実施例に於いては絶縁層（２）の下側に設けた再
結晶方向を決定する熱放散領域（４）ｆｔ構成する溝（
４１Ｌ）　、　（４ｂ）　、　（４Ｃ）−＜４ｈ）に絶
縁層（２）と同じＳｌよりも熱伝導性の悪い８１０２ｉ
注入したが、この（１１１（４ｍ）　、　（４ｂ）　、
　（４ｃ）　・＝　（４ｈ）に８１よりも熱伝導性の良
い例えば多結晶ｓｔ　２入れるときにはこの溝（４ｍ）
　、　（４ｂ）　＝　（４ｃ）　・＝　（４ｈ）の幅全
種部（１ａ）よシ遠ざかるに従って小さくすれば上述同
様の作用効果が得られることは容易に理解できよう。In the above-mentioned embodiment, a groove (4) ft forming a heat dissipation region (4) which determines the recrystallization direction provided under the insulating layer (2) is used.
41L), (4b), (4C)-<4h) with 8102i, which has poorer thermal conductivity than Sl, which is the same as the insulating layer (2).
This (111 (4m), (4b),
(4c) ・= When inserting polycrystalline ST 2, which has better thermal conductivity than 81, into (4h), use this groove (4m).
, (4b) = (4c) .= (4h) It is easy to understand that the same effect as described above can be obtained if the width of the entire width of the part (1a) is made smaller as the distance increases.

また本発明は上述実施例に限ることなく本発明の要旨を
逸脱することなく、その他種々の構成が取り得ることは
勿論である。Further, the present invention is not limited to the above-described embodiments, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

〔発明の効果〕〔Effect of the invention〕

本発明に依れば基板に半導体層（３）の再結晶化方向を
決定する熱放散領域＜４）ヲｄ　シ”ので冷部（１＆）
に関連して熱放散がなされる領域が増大しそれだけ単結
晶となる領域が拡大する利益がある。According to the present invention, there is a heat dissipation region <4) on the substrate that determines the recrystallization direction of the semiconductor layer (3).
There is an advantage that the area where heat is dissipated increases in relation to this, and the area that becomes single crystal increases accordingly.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明半導体装置の一実施例を示す拡大断面図
、第２図は従来の半導体装置の例を示す拡大断面図、第
３図は半導体装置の例を示す拡大断面図である。 （１）は半導体基板、（２）は絶縁層、（３）は半導体
１曽、（４）は再結晶化方向を決定する熱放散領域であ
る。FIG. 1 is an enlarged sectional view showing an embodiment of the semiconductor device of the present invention, FIG. 2 is an enlarged sectional view showing an example of a conventional semiconductor device, and FIG. 3 is an enlarged sectional view showing an example of a semiconductor device. (1) is a semiconductor substrate, (2) is an insulating layer, (3) is a semiconductor layer, and (4) is a heat dissipation region that determines the recrystallization direction.

Claims (1)

【特許請求の範囲】 　少なくとも表面が絶縁性である基板上の半導体層を溶
融した後再結晶化してなる半導体装置において、 上記基板に上記半導体層の再結晶化方向を決定する熱放
散領域を形成したことを特徴とする半導体装置。[Claims] A semiconductor device formed by melting and recrystallizing a semiconductor layer on a substrate having at least an insulating surface, wherein a heat dissipation region that determines the recrystallization direction of the semiconductor layer is formed on the substrate. A semiconductor device characterized by:
JP60071721A 1985-04-04 1985-04-04 Semiconductor device Pending JPS61229316A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60071721A JPS61229316A (en) 1985-04-04 1985-04-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60071721A JPS61229316A (en) 1985-04-04 1985-04-04 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61229316A true JPS61229316A (en) 1986-10-13

Family

ID=13468667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60071721A Pending JPS61229316A (en) 1985-04-04 1985-04-04 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61229316A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63169023A (en) * 1987-01-07 1988-07-13 Agency Of Ind Science & Technol Growing method for soi crystal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63169023A (en) * 1987-01-07 1988-07-13 Agency Of Ind Science & Technol Growing method for soi crystal

Similar Documents

Publication Publication Date Title
US5371381A (en) Process for producing single crystal semiconductor layer and semiconductor device produced by said process
US4564403A (en) Single-crystal semiconductor devices and method for making them
JPS62206816A (en) Manufacture of semiconductor crystal layer
JPS5939790A (en) Production of single crystal
JPS61229316A (en) Semiconductor device
JPS61251115A (en) Growth of semiconductor single crystal on insulating film
KR970063578A (en) Manufacturing method of wiring
JPS6362893B2 (en)
JPS5958821A (en) Manufacture of semiconductor single crystal film
JPS63265464A (en) Manufacture of semiconductor device
JPS6079711A (en) Manufacture of semiconductor device
JPS6144787A (en) Manufacture of thin film of semiconductor single crystal
JPH0560668B2 (en)
JPS60189218A (en) Manufacture of semiconductor integrated circuit substrate
JP2999212B2 (en) Manufacture of semiconductor thin film by melting recrystallizing method
JPS61125169A (en) Manufacture of semiconductor device
JPS61136219A (en) Formation of single crystal si film
JPS62130510A (en) Manufacture of semiconductor substrate
JPS61123125A (en) Manufacture of semiconductor device
JPH01290219A (en) Manufacture of semiconductor device
JPH02151019A (en) Manufacture of semiconductor single crystal layer
JPS6167218A (en) Manufacture of semiconductor device
JPS60106124A (en) Formation of semiconductor thin film on insulating substrate
JPH0652711B2 (en) Semiconductor device
JPS60260124A (en) Manufacture of semiconductor substrate