JPS6122821B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automated diagnostic system for fault detection circuits.

Whether the fault detection circuit can correctly detect faults is
It is extremely important for computer equipment. Therefore, consideration must be given to how to diagnose the fault detection circuit.

Conventionally, fault detection circuits have been diagnosed by manually lowering the fault detection circuit's inlet (assuming the signal level is TTL level) to ground or raising it to around +3V, and checking the operation of the fault detection circuit. There were many things.

As another method, some methods have been used in which the normality of the fault detection circuit is diagnosed by intentionally causing a fault through program operation. However, even with this method, it is necessary to confirm that the system has stopped due to the occurrence of a failure and proceed to the next test, which requires intervention. In other words, there are problems that occur in software and can be handled by software, such as circuit data errors, but there are also problems such as memory validity errors and
Faults detected by hardware, such as 2-bit errors caused by ECC (error correction code), will either cause the program to stop once set (the program cannot be self-detected as it becomes a problem with reading the program itself), or will cause a fault to be detected by the hardware. The test was simply repeating the generation program, and it was impossible to move on to the next test without manual intervention.

Here, the conventional technology will be specifically explained by taking as an example the diagnosis of a fault detection circuit that detects a memory fault.

FIG. 1 is a block diagram of the fault detection circuit, and FIG. 2 is its operation time chart.

In FIG. 1, the output line (PTYER line) of the failure detection unit 1 (which corresponds to the parity generate unit in the case of a memory failure) is connected to the signal line (RD line) 51 indicating the failure detection condition (meaning that the memory is being read). and is ANDed by an AND gate 2, and the output thereof is supplied to a data input terminal D of a flip-flop 4 (hereinafter referred to as FF) 3. Fault detection timing line 4
CHK line) 52 is input to the T (trigger) terminal of FF3. A timing line (TI line) 53 for initializing FF3 at a constant cycle and an initialization signal line (RST line) 54 generated at power-on or in response to a reset request from a panel, etc. are ORed by an OR gate 4, and the FF3 is R (reset)
connected to the terminal. The “1” output line (PERR line) 55 of the FF3 and the line 56 used to suppress the propagation of fault detection results from the outside (which is at level “1” when not suppressed) are ANDed by the AND gate 5. The output line (MPER line) 57 of this AND gate 5 is input to a fault detection section 6 (which detects the occurrence of a fault and reports the fault state to a higher level).

Here, the AND gate 5 uses a gate (referred to as an open collector in TTL) that can wire-OR another fault detection signal to the output 57. Although ordinary gates may be used, such types of gates will be used in connection with the description of the invention. It is clear that isolation of the ORed fault detection signal is possible by using line 56.

A failure report line (ERROR line) 58, which is the output of the failure detection section 6, is connected to a higher-level system (circuit or device, such as a supervisor section, a microprocessor, etc.). On the other hand, the fault details are transferred from the fault detection section 6 to the data input/output section 7, and the output of the fault type line (STATUS line) 59 is connected to the host system.

In FIGS. 1 and 2, consider a case where a memory read failure is detected by the failure detection unit 1. When a memory read failure is detected, the RTYER line 50 is activated (becomes "1"). At this time, since the memory is being read, the RD line 51 is "1", the AND condition is satisfied, and the input terminal of FF3 becomes "1".
Therefore, when CHK line 52 is activated (becomes "1"), FF3 is set to "1". Since FF3 is reset by the T1 line 53 which is activated thereafter, a pulse-like signal is applied to the PERR line 55. And if the line 56 is not "0", AND gate 5 will take the AND.
A pulse-like signal is output to the MPER line 57 and input to the fault detection section 6. Here MPER line 57
The reason why is made into a pulse-like signal is because we want to detect other signals to be ORed, and if it can be initialized from the host system, it may be made into a level signal.

When a pulse-like signal is output to the MPER line 57, the ERROR line 58 of the failure detection section 6 is set to "1".
The failure is reported to the upper system. The host system can know the type of failure from the input/output unit data unit 7. This is because the STATUS line 59 carries the information ERR (details of the failure).

Diagnosis of such a fault detection circuit will be explained. Conventionally, the common method for diagnosing the failure detection section 6 has been to manually ground the MPER line 57 (or connect it to an appropriate potential point) and check its operation. When the MPER line 57 falls to the ground, the failure detection unit 6 detects a failure and reports the failure to the host system.
The operator can know the result by lighting the fault lamp or the like.

In addition, the failure detection unit 1 was changed to detect even parity (normally odd parity is detected,
(Memory data is also written with odd parity), and there are methods to intentionally detect and diagnose memory read failures. However, it may become a problem when reading the program itself, or even if it does not cause such a problem, it may be necessary to change to even parity detection, confirm the problem detection, or intervene in acquisition to move to the next test. is necessary.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a diagnostic method that allows diagnosis of a fault detection circuit without any intervention.

However, the features of the present invention include a circuit that generates a pseudo-failure signal when receiving a command from the host system via the data input/output section of the fault detection circuit, and a fault holding section (FF3 in FIG. 1) of the fault detection circuit. A means is provided for inputting the pseudo-failure signal to the fault detection unit 6 of the fault detection circuit on the condition that no fault detection signal is output from the corresponding device (equivalent), and the pseudo-fault signal is sent to the host system via the data input/output unit. Configuring it so that it can be detected.

FIG. 3 is a block diagram showing one embodiment of the present invention, and FIG. 4 is an operation time chart during diagnosis of the same embodiment. Note that parts equivalent to those in FIGS. 1 and 2 are given the same reference numerals.

The parts numbered 8 to 12 constitute the diagnostic control circuit added according to the present invention, and the other parts constitute the fault detection circuit shown in FIG.

In Figure 3, from the data input/output unit 7 to the DPER
Line 61 and DCMD line 63 are input to data input terminals of FF9 and FF12, respectively. Furthermore, the SETFF line 60 is input from the data input/output section 7 to the trigger terminal of FF9, and further passed through the inverter 11 to the FF1
It is input to the trigger terminal of No.2. The output of OR gate 4 that resets FF3 is input to the reset terminal of FF12, and the initialize signal line (RST line) 54 and the output line (PERR line) 55 of FF3 are input.
The result obtained by ORing with OR gate 8 is input to the reset terminal of FF9. An output line (PERSTS line) 62 of the FF 9 is input to the AND gate 10 and the data input/output section 7. The output line (CMDFF line) 64 of FF12 is an AND gate 10.
ANDed with PERSTS line 62 and its output is MPER
It is wired ORed with the line 57 and input to the fault detection section 6.

Next, the diagnostic operation will be explained with reference to FIGS. 3 and 4.

When the host system wants to generate a pseudo fault for diagnosis, it first sends it via the data input/output unit 7.
Set FF9 and FF12. That is, the DPER line 61 of the data input/output section 7 is set to "1", and at the same time, the DCMD line 63 is set to "1". Then, the SETFF line 60 is set to "1". FF9 is set to "1" at the rising edge of the SETFF line 60, and its output, the PERSTS line 62, becomes "1". On the other hand, FF12 is set to 1 when the SETFF line 60 falls, but is then reset by the reset T1 line 53, so a pulse signal is output to the CMDFF line 64 which is its output.

Therefore, from AND gate 10, PERSTS line 6
The signal on 2, that is, the pseudo failure signal, is sent to the MPER line 57 as a pulsed signal, which activates the failure detection unit 6 and reports the failure to the host system.

The host system activates the data input/output unit 7 in order to know the status and type of the failure, but at this time
Since the PERSTS line 62, which is the output of the FF9, is "1", it can be known that there is a pseudo failure.
In other words, by generating a pseudo fault and obtaining the result, the program of the host system can diagnose the fault detection circuit without intervening an acquisition operation, and can move on to the next test.

Incidentally, since the report signal from an actual failure can be suppressed by setting the INH line, which is a propagation inhibiting signal line, to "0", a pseudo failure can be caused correctly only once.

On the other hand, if an actual failure occurs during pseudo failure processing, it is necessary to interrupt the diagnosis and process the actual failure with top priority. To achieve this purpose, the FF9 is configured to be reset by the PERR line 55, which is the output line of the FF3. If an actual failure is detected during diagnosis, the FF9 is reset and the PERSTS line 62 becomes "0", so the gate identifies that there is an actual failure and moves on to the main process.

In FIG. 3, FF12 may be a one-shot circuit (generates a pulse only for a certain period of time determined by the time constant of the capacitor and low resistor) activated by the SETFF line 60, or FF9 may be set. It may be a counter that counts a fixed number from 9 and generates a pulse as a result, or a shift register that sets the FF at a fixed time after setting the FF9.

As described above, according to the present invention, a fault detection circuit can be diagnosed without requiring any intervention.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a fault detection circuit, Fig. 2 is an operation time chart of the fault detection circuit, Fig. 3 is a block diagram showing an embodiment of the present invention, and Fig. 4 is a block diagram of the same embodiment. This is an operation time chart during diagnosis. 1...fault detection unit, 2, 5...and gate,
3...Flipflop, 4...Orgate, 6
...Failure detection section, 7...Data input/output section, 8...
OR gate for diagnostic control, 9, 12...Flip-flop for diagnostic control, 10...OR gate for diagnostic control, 11...Inverter for diagnostic control.

Claims (1)

[Claims] 1 A fault detection unit that detects a fault, a fault holding unit that captures and holds the output of the fault detection unit, and a data input that receives the output of the fault holding unit and sends a fault report to the higher-level system and that can be accessed from the higher-level system. A fault detection circuit comprising a fault detection section that transfers fault details to a host system via an output section, a means for generating a pseudo fault signal upon receiving a command from the host system via the data input section, and a means for holding the fault. means for inputting the pseudo signal to the fault detection section on the condition that no fault detection signal is output from the section, so that the pseudo fault signal can be detected by the host system via the data input/output section. A diagnostic method for a fault detection circuit characterized by comprising: