JPS5840771B2 - Memory element diagnosis method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus, and particularly to a method for diagnosing a flip-flop and memory in an information processing apparatus.

In recent years, information processing devices have come to be used in important fields of society, and there is a strong desire to improve their reliability and maintainability.

Along with this, automatic diagnosis of information processing devices has become widespread.

The FLP method is a typical method for this automatic diagnosis.

This involves scanning a test pattern into a flip-flop in the device, sending out a clock, scanning out the contents of the flip-flop that stores the calculation results based on the test pattern, and comparing it with the correct value calculated in advance by software. This is a method for diagnosing the combinational circuit between the scan-in side flip-flop and the scan-out side flip-flop.

As described above, this FLP method uses flip-flops as a diagnostic tool (hardcore).

Therefore, when diagnosing a combinational circuit using the FLP method, the normality of the flip-flops must be confirmed in advance.

For this reason, flip-flops are diagnosed before diagnosing combinational circuits.

This diagnosis is performed by scanning 0'' or 1'' data (test pattern) into the flip-flop and confirming that the same value is scanned out.

However, scan-in/out is usually performed in fixed units (for example, 4-byte units), but generally not all bits in the scan-in/out unit are valid.
Various tooth extractions are organized into states.

For this reason, diagnosis must be performed in the following steps for each scan-in and scan-out unit: test pattern scan-in, scan-out, masking of invalid bits, and comparison with expected values, resulting in a huge amount of diagnostic programs. , its creation is also difficult.

The present invention aims to eliminate this drawback and provides a method for easily diagnosing flip-flops or memories.

However, the feature of the present invention is that a counter and a check circuit are provided, and a flip-flop or memory is provided with a 1" or 'O
After scanning in the data of ``, scan out the contents of the flip-flop or memory, count the number of ``1'' bits of this scanned-out data by the counter, and check whether the count result matches a specified value. The object of the present invention is to diagnose a flip-flop or a memory by checking whether the flip-flop or the memory is not present or not using the check circuit.

FIG. 1 is a block diagram showing one embodiment of the present invention.

1 is a flip-flop group that can be scanned in/out within the information processing device, 2 is an AND gate, and 3 is a 4-bit counter.

AND gate 2 contains scanout data 15 from flip-flop group 1 and scanout trigger signal 11.
is connected, and the output line of this AND gate 2 is connected to the trigger terminal of the counter 3.

4 is a 4-bit register, and data can be set using a microinstruction.

Numerals 5 to 8 are exclusive OR gates operated by two people, and constitute a circuit for checking the contents of the register 4 and the counter 3. Numeral 9 is an AND gate, and numeral 10 is a flip-flop.

The output lines of the counter 3 and the register 4 are connected to the exclusive OR gates 5 to 8 for one bit each.

A signal 15 obtained by ORing the output lines of exclusive ORs 5 to 8 and a check instruction signal 13 are connected to the AND gate 9, and the output line thereof is connected to a set terminal of a flip-flop 10.

The output 14 of the flip-flop 10 is used as a stop control signal for the information processing device.

Next, the operation will be explained.

The details of the scan-in and scan-out operations for the flip-flop group 1 are not directly related to the present invention, so the explanation will be omitted.

However, for convenience of explanation, it is assumed that scan-in and scan-out are performed bit serially.

When the scan-out command is executed and the scan-out operation is started, scan-out data 15 is input to the AND gate 2.

The scanout trigger 11, which is another input to the AND gate 2, becomes 1'' for each bit scanned out.

Therefore, AND gate 2 is scan out data 15
When the bit is 1'', the AND condition is satisfied and a trigger signal for the counter 3 is output.

In other words, by counter 3, the scanout data is "1".
``The number of bits is counted.

Roughly, the outputs of the counter 3 and the register 4 are led bit by bit to exclusive OR gates 5 to 8 and compared.

The connected OR signal 12 output from the exclusive ORs 5 to 8 indicates the comparison result, and becomes 0" if they match, and becomes "1" if they do not match.

The check instruction signal 13 is a signal that can be specified by a microinstruction.

By executing the microinstruction for sending a check instruction signal, the comparison result between the contents of the counter 3 and the register 4 is set in the flip-flop 10.

In other words, the 61 calculated corresponding to the scan-in data
``The number of bits is set in the register 4 as a specified value, and the contents of the register 4 and the contents of the counter 3 are compared.

Therefore, if there is no failure in the flip-flop group 1, the flip-flop 10 remains reset, but if there is a failure, the count value does not match the specified value, the flip-flop 10 is set, and its output 14 is inverted.

FIG. 2 shows a schematic flowchart of the diagnostic program.

In the flowchart, BOXIO to 50 are processes for detecting a “1” bit failure (bit failure), and BO
X60 to X100 are processes for detecting O'' bit failures (bit omission is a failure).

Detection of '1' bit failure condition is performed by flip-flop group 1.
O” is scanned into all flip-flops in the counter 3, and then scanned out all flip-flops and
This is done by checking whether the value of is O (the specified value set in register 4).

0" bit failure condition is detected by scanning 61'" into all flip-flops in flip-flop group 1, then scanning out all flip-flops so that the value of counter 3 matches the specified value in register 4, that is, the flip-flop This is done by checking whether the number matches the number of groups.

Since the embodiment of FIG. 1 uses a 4-bit counter, the register 4 that stores the correct value is set with a value obtained by counting the total number of flip-flops in the device modulo 16.

If you want to know the scan address of a faulty flip-flop, you can do so by adding the circuit shown in FIG. 3 to the one shown in FIG.

Details will be explained below using FIG. 3.

As a premise of the circuit shown in FIG. 3, it is assumed that the scan-out data 15 is composed of data for each scan address and parity for each scan address (the parity is an even parity).

17 and 19 are AND gates, 18 is a 1-bit counter, 16 is an OR gate, and 20 is an inverter.

The AND gate IT is connected to the output line of the OR gate 16 which is the OR gate of the scan out data 15 and the scan out trigger 11 shown in FIG. 1 and the parity trigger 21 for each scan address.

Further, the output line of the AND gate 1γ is connected to the trigger terminal of the counter 18.

A scan-out signal 22 indicating that the scan-out is in progress is connected to the reset terminal of the counter 18 .

The output line of the counter 18 and the signal of the scan-out signal 22 via the inverter 20 are connected to the AND gate 19 .

The output signal 14' of the AND gate 19 is used for stop control of the information processing apparatus, similar to the signal 14 shown in FIG.

The timing relationships among the signals 11, 15, 21, and 22 are as shown in FIG.

Next, the operation will be explained.

The input of the AND gate 17 is scan out data 1.
5, the scan out trigger 11, and the OR signal of the parity trigger 21 for each scan address are input.

Therefore, scanout data 15 n IF? When the bit is , the input condition of the AND gate 17 is satisfied and a trigger signal for the 1-bit counter 18 is output.

The 1-bit counter 18 is reset at the start of scan-out, and the bit that is "1" in the scan-out data regarding one scan address is set modulo 1 as described above.
Count with .

In other words, if the final value of the 1-bit counter is 1, the number of 1'' bits in the scan-out data for one scan address is an odd number, and if it is O, it is an even number.

In this embodiment, the scan-out data has even parity, so when the scan-out ends, the 1-bit counter 18
If is 1, it is a parity error.

The AND gate 19 contains "1" of the 1-bit counter 18.
' side output signal and the inverted signal of the scan-out signal 22 are input, and if the value of the 1-bit counter 18 is 1 at the end of scan-out, the input condition of the AND gate 19 is satisfied, and the error signal 14' becomes 1. ” and stops the information processing device.

Therefore, by referring to the contents of the scan address register (not shown) at the time when the information processing device stopped due to an error, it is possible to know the scan address that includes the error flip-flop.

Although the details of one embodiment of the present invention have been described above, the present invention is applicable not only to flip-flops but also to memories (
register) can also be applied to diagnosis.

Further, although a 4-bit counter is used in the embodiment, the counter is not limited to 4 bits.

Furthermore, in the embodiment, the information processing device is stopped when a failure is detected, but the error flip-flop is referenced in the program.
Appropriate error handling may be performed.

As described above, according to the present invention, by providing a simple circuit, storage elements such as flip-flops and memories can be easily diagnosed using a simple diagnostic program.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a schematic flowchart showing an example of a diagnostic program for implementing the present invention, and FIG. 3 is a block diagram showing an example of a diagnostic program for implementing the present invention. FIG. 4 is a circuit diagram showing an example of a circuit added to the one in FIG. 1, and FIG. 4 is a time chart of the signals in FIG. 3. 1...Flip-flop group, 3...Counter, 4...Register, 5-8...
Exclusive OR gate that constitutes a check circuit.

Claims (1)

[Claims] 1. In an information processing device having a scan-in and scan-out function for an internal memory element, a counter and a check circuit are provided, and the memory element is provided with a 191 or 0
After scanning in the data of ``, scan out the contents of the storage element, count the number of 1'' bits of the scanned out data by the counter, and check whether or not the count result matches a specified value. A method for diagnosing a memory element, characterized in that the memory element is diagnosed by checking with the check circuit.