JPS6122358U - ピングリツドアレイパツケ−ジ - Google Patents

ピングリツドアレイパツケ−ジ

Info

Publication number
JPS6122358U
JPS6122358U JP1984105600U JP10560084U JPS6122358U JP S6122358 U JPS6122358 U JP S6122358U JP 1984105600 U JP1984105600 U JP 1984105600U JP 10560084 U JP10560084 U JP 10560084U JP S6122358 U JPS6122358 U JP S6122358U
Authority
JP
Japan
Prior art keywords
window
pin
wiring pattern
wiring
grid array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1984105600U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0134355Y2 (enrdf_load_stackoverflow
Inventor
一弘 須田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP1984105600U priority Critical patent/JPS6122358U/ja
Publication of JPS6122358U publication Critical patent/JPS6122358U/ja
Application granted granted Critical
Publication of JPH0134355Y2 publication Critical patent/JPH0134355Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP1984105600U 1984-07-12 1984-07-12 ピングリツドアレイパツケ−ジ Granted JPS6122358U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984105600U JPS6122358U (ja) 1984-07-12 1984-07-12 ピングリツドアレイパツケ−ジ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984105600U JPS6122358U (ja) 1984-07-12 1984-07-12 ピングリツドアレイパツケ−ジ

Publications (2)

Publication Number Publication Date
JPS6122358U true JPS6122358U (ja) 1986-02-08
JPH0134355Y2 JPH0134355Y2 (enrdf_load_stackoverflow) 1989-10-19

Family

ID=30664913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984105600U Granted JPS6122358U (ja) 1984-07-12 1984-07-12 ピングリツドアレイパツケ−ジ

Country Status (1)

Country Link
JP (1) JPS6122358U (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02230762A (ja) * 1989-03-02 1990-09-13 Nec Corp 半導体装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57107059A (en) * 1980-12-25 1982-07-03 Fujitsu Ltd Semiconductor package
JPS5810846A (ja) * 1981-07-10 1983-01-21 Nec Corp 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57107059A (en) * 1980-12-25 1982-07-03 Fujitsu Ltd Semiconductor package
JPS5810846A (ja) * 1981-07-10 1983-01-21 Nec Corp 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02230762A (ja) * 1989-03-02 1990-09-13 Nec Corp 半導体装置

Also Published As

Publication number Publication date
JPH0134355Y2 (enrdf_load_stackoverflow) 1989-10-19

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