JPS61222248A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to form a polycrystalline silicon resistor highly accurately, by determining the particle diameter of the polycrystalline silicon at or above the specified value, and reducing the elution of the silicon into Al, which is in contact with the silicon. CONSTITUTION:On a field oxide film 2 on a semiconductor substrate 1, a polycrystalline silicon film, in which impurities are not added, is formed at 650 deg.C or more. A polycrystalline silicon film 31 is made to remain selectively by photoetching method. The field oxide film 2 is selectively etched away, and a buffer oxide film 4 is formed. Then, <+>B<11> ions are implanted, and an upper part other than the polycrystalline silicon film 3 is covered by an ion- implantation resisting material 10. Ions of V-group inactive atoms are implanted. After heat treatment in an nitrogen atmosphere, a silicon nitride film 6 and an Al electrode 7 are formed. Then, the particle diameter of the crystal of the polycrystalline silicon film 3 becomes 3000Angstrom or more. Thus, local disappearance of the polycrystalline silicon during the electrode processes can be extremely reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device having a structure in which polycrystalline silicon and Al (aluminum) or an Al alloy are in direct contact with each other, and a method for manufacturing the same.

[Technical background of the invention and its problems]

Conventional examples of this type of semiconductor device and its manufacturing method are described in the sixth section.
As shown in the figure. That is, as shown in FIG. 6(c), an impurity-free polycrystalline silicon film 3 is formed on the field oxide film 2 on the semiconductor substrate l, and is selectively left by photolithography. Thereafter, the field oxide film 2 is selectively etched to form a buffer oxide film 4 for an ion implant take 1 of 1 m, which is necessary for forming a resistor.

Next, as shown in FIG. 6(C), the ion implantation voltage of B is applied, for example, at an accelerating voltage of 1! ! v=50ka
V, dose amount Qdx & 0xlO”m and row now.

Thereafter, a heat treatment is performed to activate the resistor, thereby forming a polycrystalline silicon resistor 3 and a single crystal silicon resistor 5 together. Next, as shown in FIG. 6(e) K, a silicon nitride film 6 is formed, an electrode formation window is formed, and an electrode r is formed.
It is a turtle that undergoes heat treatment at a temperature of 400 to 500 degrees Celsius.

However, the above conventional example has the following problems. FIG. 6(b) is an enlarged view of portion A in FIG. 6(a). As shown in this figure, the grain size of polycrystalline silicon after depositing polycrystalline silicon is dl* 1200λ, and this grain size is Bl
Even after ion implantation and further heat treatment at 1000°C, the grain size d of polycrystalline silicon remains unchanged as shown in FIG. 6(d).

It is about 1500λ in the middle. Figure 6(d) is Figure 6(C)
It is an enlarged view of part B of . At this particle size, Al
Alternatively, electrodes of FiA7 alloy are formed and heated at low temperature (400℃).
When heat treatment is performed at a temperature of 500 DEG C.), the silicon in the polycrystalline silicon 3 diffuses into the M1 in contact with the silicon and precipitates at the grain boundaries of the AI. This phenomenon continues until the isocapacity limit of silicon in M at that temperature.
Eventually this polycrystalline silicon disappears. Figure 6 (e
), 8 is a polycrystalline silicon precipitation region, and 9 is a polycrystalline silicon disappearance region. Therefore, the optimum conditions for minimizing the contact resistance between single crystal silicon and Al alloy (for example, 450°C
When heat treatment is performed for 30 minutes in a nitrogen atmosphere, silicon in the polycrystalline silicon locally disappears, and the contact resistance between the polycrystalline silicon 3 and the At alloy 7 increases.
The uniformity of resistance formation deteriorates. If this phenomenon progressed further, the resistor would become disconnected, which was rare.

[Object of the invention].

The present invention has been made in view of the above-mentioned circumstances, and it prevents the solid phase elution of silicon in polycrystalline silicon into AI and the disappearance of polycrystalline silicon, and provides a highly accurate polycrystalline silicon resistor with good uniformity. The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same.

[Summary of the invention]

In the present invention, for example, the formation temperature of polycrystalline silicon is set to 650°C.
After the ion implantation necessary for forming a resistor into the polycrystalline silicon, inert ions of group V are implanted and annealed to make the grain size of the polycrystalline silicon 3000λ or more. This reduces the elution of silicon into the silicon, making it possible to form highly accurate polycrystalline silicon resistors.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a process diagram of the same embodiment, but since this is an example corresponding to the one in FIG. 6, the same reference numerals are used for corresponding parts. As shown in FIG. 1(a), a semiconductor substrate 1
An impurity-free polycrystalline silicon film 3t is formed on the upper field oxide film 2. The temperature for forming the polycrystalline silicon film at this time is 650° C. or higher. Next, by photolithography, the polycrystalline silicon film 3□ is selectively left, and then the field oxide film 2 is selectively etched away to form a buffer oxide film 4 necessary for forming a resistor. Next, as shown in FIG. 1(b), ion implantation of 10B11 is carried out at an acceleration voltage of g
v=50keV, dose amount Qd=5. OX1
Perform at 0” cm.

Next, as shown in FIG. 1C, the upper part of the film other than the polycrystalline silicon film 31 where the resistor is to be formed is covered with an ion implantation resistant material (
For example, cover with photosensitive resin resist (1O). Then V
Inert atoms of the group (for example, H34) are ion-implanted.The ion-implantation conditions at this time are: acceleration voltage Ey=5QkeV, )'-xJIQa=1.
Performed at 0xlQ"e-". Furthermore, heat treatment is performed for 30 minutes at 1000° C. in a nitrogen atmosphere to electrically activate the ion-implanted region. Next, as shown in FIG. 1(d), a silicon nitride film 6 is formed, an electrode formation window is formed, and an electrode 1 is formed.
Heat treatment is performed for a minute.

By the way, as shown in FIG. 4, when looking at the grain size of the polycrystalline silicon film and the number of polycrystalline silicon disappearing, the grain size is aooo
When expressed below i, the number of disappearances increases, compared to 1000 in the conventional technology.
In the case of 1500λ, the number of disappearances is 100 (1200μ
(per m) reaches 4. Further, as shown in FIG. 5, when the number of disappearances approaches 100 (1200 μm hits), the resistance difference ΔR of 4 μm #A between adjacent portions becomes 80 to 100 g, and the dispersion becomes large.

On the other hand, as shown in FIG.
By setting the deposition temperature to 650°C or higher,
The initial particle size after deposition can be maintained at 150oX. Further, particle size and +N14 dose tQd when N14 ion implantation is performed after K Bll ion implantation and heat treatment is performed for 30 minutes in a nitrogen atmosphere at 1000°C.
The relationship is shown in Figure 3. As you can see from this figure,
+N14 Qd=LOXIO"Ql)-" particle size>3
000 people are formed. Therefore, as mentioned above, by setting the grain size of polycrystalline silicon to 3000 or more, the local loss of polycrystalline silicon in the electrode process is drastically reduced, and high f#
This makes it possible to form a polycrystalline silicon resistor with a high degree of resistance.

〔Effect of the invention〕

As explained above, according to the present invention, solid-phase elution of silicon in polycrystalline silicon into Al and disappearance of polycrystalline silicon can be prevented, and a polycrystalline silicon layer with good uniformity and high precision can be obtained. be.

[Brief explanation of drawings]

Figure 1 is a manufacturing process diagram of an embodiment of the present invention, Figure 2 is a characteristic diagram showing the relationship between polycrystalline silicon deposition temperature and grain size, and Figure 3 is a characteristic diagram showing the relationship between Nt4 dose and grain size. , Figure 4 is a characteristic diagram showing the relationship between the grain size and the number of polycrystalline silicon vanishes, Figure 5 is a characteristic diagram showing the relationship between the number of polycrystalline silicon vanishes and resistance St, and Figure 6 is a manufacturing process diagram of a conventional device. be. l...Semiconductor substrate, 2...Field oxide film, 3m
...Polycrystalline silicon film, 4...Buffer oxide film, 5
...Single crystal silicon resistance layer, 1...AI! electrode, 1
0...Photosensitive resin layer.

Claims (3)

[Claims] (1) A semiconductor device comprising a polycrystalline silicon layer with a grain size of 3000 Å or more and an Al or Al alloy layer in contact with the layer. (2) forming a polycrystalline silicon layer; ion-implanting electrically inactive group V atoms into the polycrystalline silicon layer to increase the grain size of the polycrystalline silicon layer to 3000 Å or more; Al or Al in contact with polycrystalline silicon
1. A method for manufacturing a semiconductor device, comprising the step of forming an alloy layer. (3) The method for manufacturing a semiconductor device according to claim 2, wherein the temperature at which the polycrystalline silicon is formed is 650° C. or higher.