JPS6122087U - display control circuit - Google Patents

display control circuit

Info

Publication number
JPS6122087U
JPS6122087U JP1984105860U JP10586084U JPS6122087U JP S6122087 U JPS6122087 U JP S6122087U JP 1984105860 U JP1984105860 U JP 1984105860U JP 10586084 U JP10586084 U JP 10586084U JP S6122087 U JPS6122087 U JP S6122087U
Authority
JP
Japan
Prior art keywords
control circuit
display control
dynamic memory
address
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984105860U
Other languages
Japanese (ja)
Inventor
清和 西尾
Original Assignee
カシオ計算機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by カシオ計算機株式会社 filed Critical カシオ計算機株式会社
Priority to JP1984105860U priority Critical patent/JPS6122087U/en
Publication of JPS6122087U publication Critical patent/JPS6122087U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の第1の実施例に於ける装置全体の構成
を示すブ爾ツク図、第2図は上記実施例に於けるアドレ
ス変検回路16の内部回路構成を示す回路ブロック図、
第3図は上記第2図に示すアドレス変換回路16の具体
的なアドレス変換例を示す図、第4図は上記実施例に於
ける各部の信号タイミングを示すタイムチャート、第5
図は本考案の第2の実施例に於けるアドレス変換回路1
6Aの内部回路構成を示す回路ブロック図、第6図は上
記第5図に示すアドレス変換回路16Aの具体的なアド
レス変換例を示す図である。 11・・・CRTコントローラ、11A・・・表示カウ
ンタ、12・・・表示メモリ(D−RAM)、13,1
4,15・・・選択回路、16,16A・・・アドレス
変換回路、17・・・パラレルーシリアル変換回路、1
訃・・データバツファ、21,22,31,32・・・
ドライバ向路。
FIG. 1 is a block diagram showing the overall structure of the device in the first embodiment of the present invention, and FIG. 2 is a circuit block diagram showing the internal circuit structure of the address modification circuit 16 in the above embodiment. ,
3 is a diagram showing a specific address conversion example of the address conversion circuit 16 shown in FIG. 2, FIG. 4 is a time chart showing the signal timing of each part in the above embodiment, and FIG.
The figure shows an address conversion circuit 1 in a second embodiment of the present invention.
FIG. 6 is a circuit block diagram showing the internal circuit configuration of 6A, and is a diagram showing a specific address conversion example of the address conversion circuit 16A shown in FIG. 5 above. 11...CRT controller, 11A...display counter, 12...display memory (D-RAM), 13,1
4, 15... Selection circuit, 16, 16A... Address conversion circuit, 17... Parallel-to-serial conversion circuit, 1
Death...data buffer, 21, 22, 31, 32...
Driver direction.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ロウアドレスとカラムアドレスとでアドレス指定される
ダイナミックメモリと、このダイナミックメモリに格納
された表示データの読出し時に於ける表示動作に同期し
て計数されるカウンタと、このカウン・タの各ビット出
力のうち、最上位ビット及び該ビットに連続する複数の
上位ビットと最下位ビットを含む少なくとも下位1ビッ
トを前記タイナミツクメモリのカラムアドレスへ入力し
、残りの複数ビットをロウアドレスへ入力するアドレス
変換回路とを具備してなることを特徴とする表示制御回
路。
A dynamic memory that is addressed by a row address and a column address, a counter that counts in synchronization with the display operation when reading display data stored in this dynamic memory, and each bit output of this counter. an address conversion circuit that inputs at least one lower bit, including the most significant bit and a plurality of upper bits and least significant bits consecutive to the most significant bit, to a column address of the dynamic memory, and inputs the remaining plurality of bits to a row address; A display control circuit comprising:
JP1984105860U 1984-07-13 1984-07-13 display control circuit Pending JPS6122087U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984105860U JPS6122087U (en) 1984-07-13 1984-07-13 display control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984105860U JPS6122087U (en) 1984-07-13 1984-07-13 display control circuit

Publications (1)

Publication Number Publication Date
JPS6122087U true JPS6122087U (en) 1986-02-08

Family

ID=30665165

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984105860U Pending JPS6122087U (en) 1984-07-13 1984-07-13 display control circuit

Country Status (1)

Country Link
JP (1) JPS6122087U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5994095A (en) * 1982-11-22 1984-05-30 Fujitsu Ltd Permeation type optical sensor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5994095A (en) * 1982-11-22 1984-05-30 Fujitsu Ltd Permeation type optical sensor

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