JPS6233095U - - Google Patents
Info
- Publication number
- JPS6233095U JPS6233095U JP12406685U JP12406685U JPS6233095U JP S6233095 U JPS6233095 U JP S6233095U JP 12406685 U JP12406685 U JP 12406685U JP 12406685 U JP12406685 U JP 12406685U JP S6233095 U JPS6233095 U JP S6233095U
- Authority
- JP
- Japan
- Prior art keywords
- display
- circuit
- display data
- memory circuit
- encoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Description
第１図は本考案による表示回路の実施例を示す
回路図、第２図はその動作を示すタイミング線図
、第３図は他の実施例を示す回路図、第４図は従
来の表示回路を示す回路図である。
１……設定器、２……エンコーダ、３……記憶
回路、４ａ〜４ｄ……表示器、５ａ〜５ｄ……７
セグメントデコーダ、６ａ〜６ｄ……７セグメン
トＬＥＤ、７……選択回路、８……発振回路、９
……カウンタ、１０……デコーダ、１１……デー
タ線。
Fig. 1 is a circuit diagram showing an embodiment of the display circuit according to the present invention, Fig. 2 is a timing diagram showing its operation, Fig. 3 is a circuit diagram showing another embodiment, and Fig. 4 is a conventional display circuit. FIG. 1...Setting device, 2...Encoder, 3...Storage circuit, 4a-4d...Display device, 5a-5d...7
Segment decoder, 6a to 6d... 7 segment LED, 7... Selection circuit, 8... Oscillation circuit, 9
... Counter, 10 ... Decoder, 11 ... Data line.
Claims (1)
の設定器で設定された条件を符号化するエンコー
ダと、このエンコーダからの符号を入力してアド
レスが指定されると共にそのアドレスに対応した
表示データを出力する記憶回路と、この記憶回路
からの表示データを表示する複数の表示器とを有
してなる表示回路において、上記記憶回路と表示
器との間に、上記複数の表示器を時分割で順次選
択すると共にこの選択された表示器に同期して上
記記憶回路から対応する表示データを時分割で出
力させる選択回路を設けたことを特徴とする表示
回路。 A setting device that sets the conditions of the information to be displayed, an encoder that encodes the conditions set by this setting device, and an address is specified by inputting the code from this encoder, and display data corresponding to that address is provided. In a display circuit comprising a memory circuit that outputs display data, and a plurality of display devices that display display data from the memory circuit, the plurality of display devices are time-shared between the memory circuit and the display device. 1. A display circuit comprising: a selection circuit that sequentially selects a display device and outputs corresponding display data from the storage circuit in a time-sharing manner in synchronization with the selected display device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12406685U JPS6233095U (en) | 1985-08-14 | 1985-08-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12406685U JPS6233095U (en) | 1985-08-14 | 1985-08-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6233095U true JPS6233095U (en) | 1987-02-27 |
Family
ID=31015742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12406685U Pending JPS6233095U (en) | 1985-08-14 | 1985-08-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6233095U (en) |
-
1985
- 1985-08-14 JP JP12406685U patent/JPS6233095U/ja active Pending
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